A continuous integer divider with 50% duty cycle output

Abstract

The present application relates to the technical field of frequency divider, and particularly relates to a continuous integer frequency divider with 50% duty cycle, comprising: a traditional target frequency divider, whose frequency division ratio is dynamically configured by a control word; a two-input NAND gate, whose first input end is connected to the least significant bit of the control word, and whose second input end is connected to the output end of a two-frequency divider; an XOR-NOT gate, whose first input end is connected to an input clock, whose second input end is connected to the output end of the two-input NAND gate, and whose output end is connected to the first input end of the traditional target frequency divider; an adder, whose first input end receives the high n-1 bits of the control word, and whose second input end receives the least significant bit of the control word; the output end of the adder is connected to the second input end of the traditional target frequency divider; and a two-frequency divider, whose input end is connected to the output end of the target frequency divider, and whose output end generates a final frequency division clock with a constant duty cycle of 50%. The present application can realize the continuous integer frequency division function with 50% duty cycle, and has simple structure and reduced design cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of frequency divider, and particularly relates to a continuous integer frequency divider with 50% duty cycle. BACKGROUND

[0002] The frequency divider is a very critical basic circuit, which is widely used in many fields such as communication, computer and automation control. The main function of the frequency divider is to process the input clock signal to obtain clock signals with different frequencies, so as to meet the diversified needs of different modules in the system for clock frequency.

[0003] Although the traditional continuous integer programmable frequency divider can realize continuous integer frequency division of the input clock signal, it has certain flexibility and programmability, but it has obvious limitations in the output duty cycle. In many practical application scenarios, the output clock signal after frequency division is required to have a precise 50% duty cycle to ensure the stability and reliability of the system. However, the traditional continuous integer programmable frequency divider cannot achieve this goal, and the duty cycle of the output clock signal will change with the change of the frequency division coefficient, and cannot always remain at 50%.

[0004] In the above scheme, the instability of the duty cycle will affect the working state of the subsequent circuit module, and then cause problems such as signal distortion and data transmission error, which seriously reduces the performance and reliability of the entire electronic system. SUMMARY

[0005] Therefore, the present application provides a continuous integer frequency divider with 50% duty cycle to solve the problem that the traditional continuous integer programmable frequency divider cannot ensure that the duty cycle of the output clock signal always remains at 50%.

[0006] In a first aspect, the present application provides a continuous integer frequency divider with 50% duty cycle, which comprises:

[0007] a traditional target frequency divider, the frequency division ratio of the traditional target frequency divider being dynamically configured by a control word;

[0008] a two-input NAND gate, a first input end of the two-input NAND gate being connected to the least significant bit of the control word, and a second input end of the two-input NAND gate being connected to the output end of the two-frequency divider;

[0009] an XOR-NOT gate, a first input end of the XOR-NOT gate being connected to the input clock, a second input end of the XOR-NOT gate being connected to the output end of the two-input NAND gate, and an output end of the XOR-NOT gate being connected to a first input end of the traditional target frequency divider;

[0010] an adder, a first input of the adder receiving high n-1 bits of the control word, a second input of the adder receiving the lowest bit of the control word and complementing to the same bit number as the high n-1 bits, an output of the adder being connected to a second input of the conventional target frequency divider; wherein n is the bit number of the control word;

[0011] a half frequency divider, an input of the half frequency divider being connected to an output of the target frequency divider, an output of the half frequency divider generating a final frequency division clock with a constant duty cycle of 50%.

[0012] The above scheme can realize the continuous integer frequency division function with a duty cycle of 50% by adding some simple peripheral circuits (such as a two-input NAND gate, an XNOR gate, an adder and a half frequency divider) to the conventional continuous integer programmable frequency divider. This design has a simple structure, is easy to understand and implement, and reduces the design cost.

[0013] In an optional embodiment, a first input of the conventional target frequency divider is a clock input for receiving the output signal of the XNOR gate as a working clock, and a second input of the conventional target frequency divider is a frequency division ratio control end for receiving the control signal output by the adder to determine the frequency division ratio of the conventional target frequency divider.

[0014] In an optional embodiment, the conventional target frequency divider is a conventional continuous integer programmable frequency divider, a dual-mode frequency divider or a multi-mode frequency divider, and the conventional target frequency divider includes a timing state machine composed of a group of resettable flip-flops and adopts a countdown mode.

[0015] In an optional embodiment, when the target preset frequency division ratio N is even, the output of the XNOR gate is in phase with the input clock, and the output of the adder is N / 2, the frequency division ratio of the conventional target frequency divider is N / 2, and the actual total frequency division ratio of the output after the half frequency divider is N.

[0016] In an optional embodiment, when the target preset frequency division ratio N is odd, the two-input NAND gate and the XNOR gate in cascade are equivalent to an XOR gate, and the output of the adder is (N+1) / 2, the frequency division ratio of the conventional target frequency divider is N / 2, and the actual total frequency division ratio of the output after the half frequency divider is N.

[0017] In an optional embodiment, an adjustable delay unit is arranged on a feedback path of the XNOR gate, and the adjustable delay unit is used to increase the width of the short high pulse output by the XNOR gate when the target preset frequency division ratio N is odd.

[0018] In an alternative embodiment, the continuous integer frequency divider further comprises a selector, a first input of the selector is connected to an output of the half frequency divider, a second input of the selector is connected to a half frequency signal of the input clock, and a control terminal of the selector is used to select whether to be compatible with the half frequency function.

[0019] In an alternative embodiment, the adder and the conventional target frequency divider have the same bit number, both of which are n_1 bits, and the highest bit of the adder has no overflow.

[0020] In an alternative embodiment, the continuous integer frequency divider has a minimum frequency division ratio of 3 and a maximum frequency division ratio of 2 n -2, and when the bit number of the control word is expanded, the bit number of the adder and the conventional target frequency divider is expanded synchronously.

[0021] In an alternative embodiment, the input clock of the continuous integer frequency divider has a duty cycle of 50%.

[0022] The technical solution provided by the present application can include the following beneficial effects:

[0023] The present application can realize the continuous integer frequency division of 3 to 2 n -2 by adding some simple peripheral circuits (such as two-input NAND gate, XOR-NAND gate, adder and half frequency divider) to the conventional continuous integer programmable frequency divider. The frequency division ratio range can be further expanded by expanding the bit number of the frequency divider control word, so that the frequency divider can adapt to a wider range of application scenarios. In the case of even target preset frequency ratio, the duty cycle of the output clock remains 50%, which is not affected by the duty cycle of the input clock. In the case of odd target preset frequency ratio, by adding appropriate delay in the feedback path, the width of the short high pulse can be increased, and the anti-interference performance of the circuit can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 is a structural schematic diagram of a continuous integer frequency divider with a 50% duty cycle output according to an embodiment of the present application;

[0026] Figure 2is a simplified circuit schematic diagram of a frequency divider with an even frequency division ratio according to an embodiment of the present application;

[0027] Figure 3 is a simplified circuit schematic diagram of a frequency divider with an odd frequency division ratio according to an embodiment of the present application;

[0028] Figure 4 is a waveform timing schematic diagram of a frequency divider with a frequency division ratio of 7 according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0030] It should be noted that the design principle of a conventional continuous integer programmable frequency divider is that a general programmable counter is the core, and the structure is usually a timing state machine composed of a group of reset / set flip-flops DFF. The working mode is usually to program the initial state value of the state machine first, that is, to preset the count value or the frequency division ratio. When a valid clock edge arrives, the timing state machine starts counting. In the design of a high-speed analog counter, a common counter is usually a countdown from large to small. That is, the state value of the state machine decreases by one for each input of a valid clock edge. When the state value decreases to the preset state value, the counter outputs a clock edge, completing a counting period. The high-level time of the output clock is only one input clock period. Therefore, the output waveform duty cycle of the conventional continuous integer programmable frequency divider is 1 / N. Unless N is 2, a 50% duty cycle output frequency clock cannot be obtained.

[0031] Furthermore, there are two more advanced continuous programmable frequency dividers, namely a dual-mode frequency divider and a multi-mode frequency divider. The dual-mode frequency divider includes an N / (N+1) pre-divider, a programmable P counter, and a programmable S counter. The multi-mode frequency divider includes a series of 2 / 3 frequency divider units. Both of the two frequency dividers can expand the duty cycle of the output frequency clock, such as expanding from 1 / N to 2 / N, 4 / N, and the like, but cannot obtain a 50% duty cycle clock output.

[0032] The application relates to the duty cycle processing of the frequency-divided clock inside an integrated circuit chip. According to the above analysis, the traditional continuous programmable integer frequency divider cannot realize the 50% frequency-divided output. In the use occasion with strict requirements on the output clock duty cycle, the traditional programmable continuous integer frequency divider cannot be used. The application provides a new circuit which can realize the function by adding some simple peripheral circuits on the basis of the existing traditional programmable continuous integer frequency divider. In the case of continuous integer frequency division, the output clock with the 50% output duty cycle can be obtained.

[0033] In the embodiment, a continuous integer frequency divider with the 50% output duty cycle is provided, Figure 1 which is a structural schematic diagram of the continuous integer frequency divider with the 50% output duty cycle according to the embodiment of the application, as shown in the figure, the continuous integer frequency divider comprises: Figure 1

[0034] a traditional target frequency divider, the frequency division ratio of the traditional target frequency divider is dynamically configured by a control word; the control word is a binary value.

[0035] a two-input NAND gate, the first input end of the two-input NAND gate is connected to the least significant bit of the control word, and the second input end is connected to the output end of the two-frequency divider;

[0036] an XOR-NOT gate, the first input end of the XOR-NOT gate is connected to the input clock, the second input end is connected to the output end of the two-input NAND gate, and the output end of the XOR-NOT gate is connected to the first input end of the traditional target frequency divider;

[0037] a summer, the first input end of the summer receives the high n-1 bits of the control word, the second input end receives the least significant bit of the control word, and the same number of bits as the high n-1 bits are added up; the output end of the summer is connected to the second input end of the traditional target frequency divider; wherein n is the bit number of the control word;

[0038] a two-frequency divider, the input end of the two-frequency divider is connected to the output end of the target frequency divider, and the output end generates the final frequency-divided clock with the constant 50% duty cycle.

[0039] Further, the traditional target frequency divider (i.e. Figure 1 P in the figure) is the core component of the embodiment, and the frequency division ratio (i.e. the ratio of the input frequency to the output frequency) can be dynamically configured by an n-1 bit control word output by the summer. The control word is a binary value, for example, if the control word is 4-bit 0111, the corresponding decimal value is 7, that is, the input clock frequency can be changed to 1 / 7 of the original.

[0040] a two-input NAND gate (i.e. Figure 1 ​The NAND2 logic gate has two inputs. The first input is connected to the least significant bit b0 of the control word (the rightmost bit in the binary representation of the control word), which determines whether the division ratio is odd or even. The second input is connected to the output of the divider and is used to receive the feedback signal.

[0041] XOR NOT gate (i.e. Figure 1 The XNOR in the circuit also has two inputs. The first input is directly connected to the input clock (i.e., ...). Figure 1 The first input (Fin) is the original clock source that needs to be divided; the second input is connected to the output of the two-input NAND gate. The output of the XOR gate is then connected to the first input of the conventional target frequency divider, providing the conventional target frequency divider with a logic-processed clock signal.

[0042] Adder (i.e.) Figure 1 The Adder in the standard frequency divider (CFD) processes the control word to generate the control signals required by the conventional target frequency divider. The first input of the adder receives the high n-1 bits of the control word (e.g., if the control word is 4 bits, the high 3 bits are 011), and the second input receives the least significant bit of the control word and extends it to the same number of bits as the high n-1 bits (filling the high bits with 0s). The adder adds these two parts, and the output is connected to the second input of the conventional target frequency divider to control the divider's division ratio.

[0043] Frequency divider (i.e.) Figure 1 The input of Div2 is connected to the output of a conventional target frequency divider to receive the signal after initial frequency division. The function of the frequency divider is to divide the input signal again so that the duty cycle of the final output clock signal is constant at 50%. For example, if the frequency of the signal output by the conventional target frequency divider is N, then the frequency of the signal output by the frequency divider will be N / 2, and the high and low level times will be equal.

[0044] In this embodiment, when the input clock enters the continuous integer divider, it first undergoes preliminary logic processing via an XOR gate. The processed signal is then fed into a conventional target divider, which sets the division ratio based on the control signal output by the adder (this signal is obtained by processing the control word through the adder), thereby dividing the clock signal to a set multiple. The divided signal is then fed into a divider by two, outputting the final divided clock (i.e.,... Figure 1 The output clock (Fout) in the input clock not only has a frequency that is 1 / N of the input clock (N is an integer), but its duty cycle is also stably maintained at 50%.

[0045] In an alternative embodiment, the first input terminal of the conventional target frequency divider is a clock input terminal for receiving the output signal of the XNOR gate as a working clock; and the second input terminal of the conventional target frequency divider is a frequency ratio control terminal for receiving the control signal output by the adder to determine the frequency ratio of the conventional target frequency divider.

[0046] Further, the first input terminal (i.e. the clock input terminal) of the conventional target frequency divider is used to receive the output signal of the XNOR gate as a working clock of the frequency divider. The clock input terminal is the clock source of the conventional target frequency divider, which determines the working rhythm of the conventional target frequency divider. After logical processing, the output signal of the XNOR gate provides a synchronous clock signal for the conventional target frequency divider, ensuring that the conventional target frequency divider performs counting and frequency dividing operations according to correct timing.

[0047] The second input terminal (i.e. the frequency ratio control terminal) of the conventional target frequency divider is used to receive the control signal output by the adder, which determines the frequency ratio of the frequency divider. The frequency ratio control terminal controls the frequency multiplication of the frequency divider. The adder calculates a control signal according to the high n-1 bits and the lowest bit of the control word, and the conventional target frequency divider adjusts its internal counting logic according to the signal, thereby realizing different frequency ratios.

[0048] In an alternative embodiment, the conventional target frequency divider is a conventional continuous integer programmable frequency divider, a dual-mode frequency divider or a multi-mode frequency divider, and the conventional target frequency divider includes a timing state machine composed of a group of resettable flip-flops and adopts a countdown mode.

[0049] Further, the conventional continuous integer programmable frequency divider is a basic frequency divider capable of dynamically configuring the frequency ratio according to the control word to realize continuous integer frequency division. The dual-mode frequency divider includes an N / (N+1) pre-divider, a programmable P counter and a programmable S counter, which can expand the duty cycle of the output frequency clock. The multi-mode frequency divider includes a series of 2 / 3 frequency dividing units, which can also expand the duty cycle of the output frequency clock. The internal structure of any of the above frequency dividers includes a group of resettable flip-flops and a timing state machine. The flip-flop is a basic storage unit in digital circuits, which can store one bit of binary information. The timing state machine composed of these flip-flops is responsible for changing its internal state according to the input clock signal and control signal according to the preset logic sequence, thereby realizing the frequency division function.

[0050] The conventional target frequency divider adopts a countdown mode for counting. In this mode, the frequency divider starts from a preset initial value, and the count value decreases by one each time a valid clock edge is received. When the count value decreases to zero, the frequency divider outputs a clock edge and reloads the initial value to continue counting.

[0051] In an alternative embodiment, when the target preset division ratio N is even, the output of the XNOR gate is in phase with the input clock, and the output of the adder is N / 2, the division ratio of the conventional target divider is N / 2, and the actual total division ratio of the output after the two-stage divider is N.

[0052] Further, the target preset division ratio N refers to the preset division multiple in the design of the divider, which determines the frequency of the output clock signal after the input clock Fin is divided. When the target preset division ratio N is even, the lowest bit b0 of the control word is 0. According to the circuit design, the output of the two-input NAND gate NAND2 is 1. The second input of the XNOR gate receives the output 1 of the two-input NAND gate NAND2, and at this time, the output of the XNOR gate is equal to the signal of the first input, i.e., the input clock Fin. Therefore, the output of the XNOR gate is in phase with the input clock Fin. The high n-1 bits and the lowest bit b0 of the control word are processed by the adder. Since b0 is 0, the output of the adder is equal to the value of the high n-1 bits, i.e., N / 2. The conventional target divider sets its division ratio to N / 2 according to the control signal N / 2 output by the adder. The two-stage divider further divides the output signal of the conventional target divider, and the division ratio is 2. Therefore, the division ratio of the final output clock Fout is N / 2*2=N.

[0053] In an alternative embodiment, when the target preset division ratio N is odd, the two-input NAND gate and the XNOR gate are equivalent to an XOR gate in cascade, and the output of the adder is (N+1) / 2. The division ratio of the conventional target divider is N / 2, and the actual total division ratio of the output after the two-stage divider is N.

[0054] Further, when the target preset division ratio N is odd, the lowest bit b0 of the control word is 1. According to the circuit design, the output of the two-input NAND gate NAND2 is related to the inverted signal of the output signal of the two-stage divider, i.e., the output clock Fout. The second input of the XNOR gate receives the output signal of the NAND gate. In this case, the combination logic of the NAND gate and the XNOR gate is equivalent to an XOR gate. The output signal of the XOR gate is XORed with the input clock to generate the required clock signal. The high n-1 bits and the lowest bit b0 of the control word are processed by the adder. Since b0 is 1, the output of the adder is equal to the value of the high n-1 bits plus 1, i.e., (N+1) / 2. Since a half-integer divider is included at this time, the division ratio of the conventional target divider P is the division ratio of its control end minus 0.5, and therefore the conventional target divider sets its division ratio to N / 2 according to the control signal (N+1) / 2-0.5 output by the adder. The two-stage divider further divides the output signal of the conventional target divider, and the division ratio is 2. Therefore, the division ratio of the final output clock signal is N / 2*2=N.

[0055] In an alternative embodiment, an adjustable delay unit is provided in the feedback path of the XNOR gate, which is used to increase the width of the short high pulse output by the XNOR gate when the target preset division ratio N is odd.

[0056] Further, the embodiment provides an adjustable delay unit in the feedback path of the XNOR gate. The feedback path refers to the signal loop from the output end of the XNOR gate to its input end. The adjustable delay unit is used to increase the width of the short high pulse output by the XNOR gate. When N is odd, the output of the XNOR gate will appear a short high pulse. The width of these short high pulses can be very short and easily disturbed by noise. By providing an adjustable delay unit in the feedback path, the width of these short high pulses can be artificially increased to make them more stable, thereby improving the anti-interference ability of the circuit.

[0057] In an alternative embodiment, the continuous integer divider further comprises a selector, a first input end of the selector is connected to the output end of the two-divider, a second input end of the selector is connected to the two-division signal of the input clock, and a control end of the selector is used to select whether to be compatible with the two-division function.

[0058] Further, the embodiment adds a selector based on the basic design of the continuous integer divider to provide compatibility with the two-division function. This means that the divider can not only achieve continuous integer division from 3 to 2 n -2, but also can achieve the two-division function of the input clock through the selector. The selector is used to select whether to use the output signal of the traditional target divider (first input end) or the two-division signal of the input clock (second input end). When the control end selects the first input end, the divider divides according to the target preset division ratio N. When the control end selects the second input end, the divider directly outputs the two-division signal of the input clock, i.e., the division ratio is fixed to 2.

[0059] In an alternative embodiment, the adder and the traditional target divider have the same number of bits, both n_1 bits, and the highest bit of the adder has no overflow.

[0060] Further, the control word is an n-bit binary number, denoted as {b n-1 b n …b2b1b0}, the first input end of the adder receives the high n-1 bits of the control word, i.e., {b n-1 b n…b2b1b0}. The second input of the adder receives the least significant bit b0 of the control word and extends it to n-1 bits (padded with 0s in the high-order bits). The adder adds the high-order n-1 bits and the extended least significant bit to generate an n-1 bit output. When b0 is 0, the adder output is equal to the value of the high-order n-1 bits; when b0 is 1, the adder output is equal to the value of the high-order n-1 bits plus 1.

[0061] In one optional implementation, the minimum division ratio of the continuous integer frequency divider is 3, and the maximum division ratio is 2. n -2, and when the number of bits of the control word is expanded, the number of bits of the adder and the conventional target frequency divider are expanded synchronously.

[0062] Furthermore, this continuous integer frequency divider design excludes division ratios of 1 (no division required) and 2 (achievable through a simple divide-by-two circuit), focusing on higher division requirements. When the division ratio is ≥3, a 50% duty cycle output must be achieved through programmable logic and a feedback path to avoid the duty cycle limitation of traditional frequency dividers at low division ratios. If the control word is an n-bit binary number, its theoretical maximum value is 2. n -1, but here it is set to 2. n -2 is because the adder needs to ensure that the most significant bit does not overflow, when the frequency division ratio is 2. n When the value is -1, the adder output may exceed the capacity of n-1 bits, leading to a logic error. The number of bits in the adder and the conventional target divider must match the number of bits in the control word. For example, if the control word is extended from 4 bits to 5 bits, the number of bits in the adder and the conventional target divider also needs to be extended from 3 bits to 4 bits to ensure that the extended control word can be processed correctly.

[0063] In one optional implementation, the duty cycle of the input clock of the continuous integer divider is 50%. When the duty cycle of the input clock deviates from 50%, the duty cycle of the divided output will deviate from 50% if the target preset division ratio N is odd, while the duty cycle of the divided output will remain at 50% if the division ratio is even.

[0064] In summary, the continuous integer programmable frequency divider with a 50% output duty cycle presented in this embodiment is based on the traditional target frequency divider P, with the addition of a two-input NAND gate (NAND2), an XOR gate (XNOR), an adder (Adder), and a two-divider (Div2) on the periphery. Assume the control word of the frequency divider is converted to n bits in binary, denoted as {b n- 1b n …b2b1b0}, then it can achieve 3 to 2 n -2 is a series of consecutive integer divisions. The duty cycle of the output clock from these consecutive divisions is 50%. The adder acts as a frequency divider correction. This adder is n-1 bits long, with one input being {b...}n-1 b n …b2b1b0}, the value of the second input is b0. After padding it to n-1 bits, it is added to the first input (all high bits are padded with 0), and the resulting output is also n-1 bits. The highest bit of this adder cannot overflow, otherwise the frequency division function will fail. The output of the adder controls the division ratio of the traditional target frequency divider P, so the number of bits controlling the division coefficient of the traditional target frequency divider P is also n-1 bits.

[0065] Next to Figure 1 Further analysis of the circuit's working principle is needed, assuming... Figure 1 The total division value of the frequency divider is N (i.e., the target preset division ratio N), which is analyzed in two cases. The first case is if N is even, then the binary representation of the target preset division ratio N is {b n-1 b n In {b2b1b0}, b0 must be 0, so the output of the NAND gate must be 1. Since the second input of the XOR gate is 1, its output equals the first input, meaning the input clock Fin, after passing through a non-phase buffer, is directly fed into the clock input of the traditional target frequency divider P. The output of the adder equals {b...} n-1 b n …b2b1b0}, which is N / 2. Therefore, the division ratio of the traditional target frequency divider P is N / 2. After the traditional target frequency divider P divides the frequency, it passes through the subsequent two-divider, so the total division ratio is N (that is, the actual total division ratio of the output after the two-divider is N). Moreover, because of the existence of the subsequent two-divider, the duty cycle of the output clock must be 50%, and its equivalent circuit is as follows. Figure 2 As shown.

[0066] The second case is when the target preset division ratio N is an odd number. In this case, the binary representation of the division ratio N is {b n-1 b n In the sequence …b2b1b0}, b0 must be 1. Through simple logical analysis, the frequency divider circuit can be simplified to… Figure 3 A cascaded two-input NAND gate and an XOR gate can be equivalent to an XOR gate. The division ratio control word sent to the conventional target frequency divider P is (N+1) / 2. Figure 3 The simplified circuit actually includes a half-integer frequency divider. In this case, the division ratio of the conventional target frequency divider P is the division ratio at its control terminal minus 0.5, i.e., (N+1) / 2 - 0.5 = N / 2. At the output of the divider, the division ratio of its output clock is 2*N / 2 = N. Furthermore, the duty cycle of the output clock is 50%.

[0067] Frequency division analysis is performed using a target preset division ratio N=7 as an example. The timing waveform is shown below. Figure 4 As shown. The division ratio control word sent to the traditional target frequency divider P is (N+1) / 2 = 4. WhenFigure 3 When the conventional target divider P counts down from 4 to 1, an up edge appears at the output of the conventional target divider P, which triggers the two-divider and causes the output of the two-divider to flip. The flipped clock signal goes through the feedback signal path and is XORed with the input clock signal, resulting in a narrow pulse. The narrow pulse triggers the conventional target divider P again, causing the actual division ratio of the internal programmable counter to be 4 minus 0.5, i.e. 3.5. Therefore, from the output of the two-divider, a 7-division is generated. The duty cycle of the output clock Fout is 50%.

[0068] The embodiment achieves a continuous integer programmable divider with a 50% duty cycle by adding some peripheral circuits to the conventional target divider P with a 1 / N duty cycle. The circuit is simple and has no complex analog part. It is easy to understand and implement, and the design cost is low, so it is very practical. The highest operating frequency of the divider of the embodiment is mainly determined by the used process and the highest operating frequency of the conventional target divider P. In a 40nm CMOS process, the highest input frequency can be not less than 1GHz. In more advanced process nodes, higher input operating frequencies can be achieved. The minimum division ratio of the divider is 3 and the maximum division ratio is 2 n -2, where n is the number of bits of the divider control word. If you want to be compatible with two-division, you can add a two-input selector at the output of the circuit of the embodiment, and the other input of the selector inputs the two-division circuit of the clock. The maximum division ratio of the divider is determined by the number of bits of the divider, which can be expanded indefinitely. If you want a larger division ratio, you can directly expand the number of bits of the conventional target divider P and the number of bits of the adder.

[0069] The continuous integer divider described in the embodiment assumes that the duty cycle of the input clock is 50%. If the duty cycle of the input clock deviates from 50%, then in the case of odd division ratio, the duty cycle of the division output will also deviate from 50%. In the case of even division ratio, the duty cycle of the division output will remain 50% and will not be affected. When dividing by an odd number, a short high pulse will appear at the output of the XOR-NOT gate, at which time some appropriate delay can be artificially added to the feedback path to increase the width of the short high pulse, so that the anti-interference performance of the circuit will be better. The conventional target divider P in the embodiment can be any continuous integer programmable divider, i.e. not only a conventional continuous integer programmable divider, but also a continuous integer programmable divider composed of more advanced and higher speed dual-mode dividers or multi-mode dividers, which is very flexible in design.

[0070] In summary, the embodiment adds some simple peripheral circuits (such as two-input NAND gate, XOR-NOR gate, adder and two-divider) on the basis of the traditional continuous integer programmable frequency divider, so as to realize the continuous integer frequency division function with a duty cycle of 50%. The design structure is simple, easy to understand and implement, and reduces the design cost. The application can realize 3 to 2 n continuous integer frequency division, and by expanding the bit number of the frequency divider control word, the range of the frequency division ratio can be further expanded. The frequency divider can adapt to a wider range of application scenarios. In the case of an even target preset frequency division ratio, the duty cycle of the output clock remains 50%, which is not affected by the duty cycle of the input clock. In the case of an odd target preset frequency division ratio, by adding an appropriate delay in the feedback path, the width of the short high pulse can be increased, and the anti-interference performance of the circuit can be improved.

[0071] Although the embodiments of the application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and changes fall within the scope defined.

Claims

1. A continuous integer frequency divider with an output duty cycle of 50%, characterized in that, The continuous integer frequency divider includes: A conventional target frequency divider, wherein the division ratio of the conventional target frequency divider is dynamically configured by a control word; A two-input NAND gate, wherein the first input of the two-input NAND gate is connected to the least significant bit of the control word, and the second input is connected to the output of the frequency divider. An XOR gate, wherein the first input terminal of the XOR gate is connected to the input clock, the second input terminal is connected to the output terminal of the two-input NAND gate, and the output terminal of the XOR gate is connected to the first input terminal of the conventional target frequency divider; An adder, wherein the first input terminal of the adder receives the high n-1 bits of the control word, the second input terminal receives the least significant bit of the control word, and pads it to the same number of bits as the high n-1 bits; the output terminal of the adder is connected to the second input terminal of the conventional target frequency divider; wherein n is the number of bits of the control word; A frequency divider is provided, wherein the input of the frequency divider is connected to the output of the target frequency divider, and the output generates a final frequency-divided clock with a constant duty cycle of 50%.

2. The continuous integer frequency divider according to claim 1, characterized in that, The first input terminal of the conventional target frequency divider is a clock input terminal, used to receive the output signal of the XOR gate as the working clock; the second input terminal of the conventional target frequency divider is a division ratio control terminal, used to receive the control signal output by the adder to determine the division ratio of the conventional target frequency divider.

3. The continuous integer frequency divider according to claim 1, characterized in that, The conventional target frequency divider is a conventional continuous integer programmable frequency divider, dual-mode frequency divider, or multi-mode frequency divider, and the conventional target frequency divider includes a timing state machine composed of a set of resettable triggers and adopts a countdown mode.

4. The continuous integer frequency divider according to claim 1, characterized in that, When the target preset division ratio N is even, the output of the XOR gate is in phase with the input clock, and the output of the adder is N / 2. The division ratio of the conventional target divider is N / 2, and the actual total division ratio output after the divider is N.

5. The continuous integer frequency divider according to claim 1, characterized in that, When the target preset frequency division ratio N is odd, the cascaded two-input NAND gate and the XOR gate are equivalent to an XOR gate, and the output of the adder is (N+1) / 2. The frequency division ratio of the traditional target frequency divider is N / 2, and the actual total frequency division ratio output after the two frequency dividers is N.

6. The continuous integer frequency divider according to claim 5, characterized in that, An adjustable delay unit is provided on the feedback path of the XOR gate. The adjustable delay unit is used to increase the width of the short-time high pulse output by the XOR gate when the target preset frequency division ratio N is odd.

7. The continuous integer frequency divider according to claim 1, characterized in that, The continuous integer divider also includes a selector. The first input terminal of the selector is connected to the output terminal of the divider, and the second input terminal is connected to the divider signal of the input clock. The control terminal of the selector is used to select whether to be compatible with the divider function.

8. The continuous integer frequency divider according to claim 1, characterized in that, The adder and the conventional target frequency divider have the same number of bits, n-1 bits, and the highest bit of the adder has no overflow.

9. The continuous integer frequency divider according to claim 1, characterized in that, The minimum division ratio of the continuous integer frequency divider is 3, and the maximum division ratio is 2. n -2, and when the number of bits of the control word is expanded, the number of bits of the adder and the conventional target frequency divider are expanded synchronously.

10. The continuous integer frequency divider according to claim 1, characterized in that, The duty cycle of the input clock of the continuous integer divider is 50%.

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