Variable resistance memory device and electronic device including same

Abstract

A variable resistance memory device and an electronic device including the same are provided. The variable resistance memory device includes a resistance change layer having a resistance characteristic that varies according to an applied voltage, a channel layer disposed on the resistance change layer, and a gate electrode disposed on the channel layer. The resistance change layer includes a metal nitride or a metal oxynitride.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Korean Patent Application No. 10 - 2024 - 0006308, filed with the Korean Intellectual Property Office on January 15, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Devices and methods consistent with example embodiments relate to variable - resistance memory devices (memory devices) and electronic devices including the same. Background art

[0004] Non - volatile memory devices include a plurality of memory cells that retain information even when the power is turned off and, thus, the stored information can be reused when the power is turned on. These non - volatile memory devices are widely applicable to mobile phones, digital cameras, personal digital assistants (PDAs), portable computer devices, and the like.

[0005] Recently, due to the need for memory devices with high integration and low power consumption, vertical NAND (VNAND) flash memory devices have been developed, and due to the increased integration, vertical NAND flash memory devices including a resistive - change material have been studied to overcome the limitations of vertical NAND flash memory devices having a charge - trapping (trap) layer. Summary of the invention

[0006] One or more example embodiments provide a variable - resistance memory device and an electronic device including the same.

[0007] According to an aspect of the present disclosure, a variable - resistance memory device may include: a resistive - change layer having a resistance characteristic that varies according to a voltage applied to the resistive - change layer; a channel layer disposed on the resistive - change layer; and a gate electrode disposed on the channel layer, wherein the resistive - change layer may include a metal nitride or a metal oxynitride.

[0008] The ratio of the nitrogen content in the resistive - change layer to the sum of the nitrogen content and the oxygen content may be in the range of 0.01 to 1.

[0009] The ratio of the nitrogen content in the resistive - change layer to the sum of the nitrogen content and the oxygen content is less than or equal to 0.9.

[0010] The resistive - change layer may include tantalum nitride (TaN) or tantalum oxynitride (TaON).

[0011] The metal may include a transition metal, aluminum (Al), or gallium (Ga).

[0012] The channel layer may include silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V semiconductor, oxide semiconductor, nitride semiconductor, oxynitride semiconductor, two-dimensional semiconductor material, quantum dot, or organic semiconductor.

[0013] The gate electrode may include a metal material, a metal nitride, silicon doped with impurities, or a two-dimensional conductive material.

[0014] The variable resistance memory device may further include a gate insulating layer disposed between the gate electrode and the channel layer.

[0015] The gate insulating layer may include silicon oxide, silicon nitride, or silicon oxynitride.

[0016] According to one aspect of the present disclosure, a variable resistance memory device may include a plurality of cell strings, wherein each of the plurality of cell strings may vertically extend on a substrate and includes: a channel layer; a resistance change layer disposed inwardly (inside) with respect to the channel layer, the resistance change layer having a resistance characteristic that varies according to a voltage applied to the resistance change layer; and a plurality of gate electrodes disposed outwardly (outside) with respect to the channel layer, wherein the resistance change layer may include a metal nitride or a metal oxynitride.

[0017] The ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content in the resistance change layer may be in the range of 0.01 to 1.

[0018] The ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content in the resistance change layer may be less than or equal to 0.9.

[0019] The resistance change layer may include tantalum nitride (TaN) or tantalum oxynitride (TaON).

[0020] The metal may include a transition metal, aluminum (Al), or gallium (Ga).

[0021] A channel hole extending in a direction perpendicular to the substrate may be formed inwardly (inside) with respect to the channel layer.

[0022] The channel layer and the resistance change layer may each be formed in a cylindrical shape surrounding the channel hole.

[0023] The plurality of gate electrodes may be arranged spaced apart from each other in a direction perpendicular to the substrate, and the plurality of gate electrodes may surround the channel layer.

[0024] The variable resistance memory device may further include an interlayer insulating layer disposed between the plurality of gate electrodes.

[0025] The variable resistance memory device may further include a gate insulating layer disposed between the plurality of gate electrodes and the channel layer.

[0026] According to another aspect of the present disclosure, a variable resistance memory device may include a cell string, where the cell string may include: a gate layer including a plurality of gate electrodes spaced apart from each other in the axial direction of the cell string; a plurality of inner layers disposed inward from the gate layer toward the center of the cell string in the radial direction, where the plurality of inner layers may include: a resistive change layer having a resistance that varies according to a voltage applied to the resistive change layer; and a channel layer disposed between the resistive change layer and the gate layer in the radial direction. The resistive change layer may include a metal nitride or a metal oxynitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings, in which:

[0028] Figure 1 is a perspective view schematically showing a variable resistance memory device according to one or more embodiments;

[0029] Figure 2 shows Figure 1 a cross-section of the cell string shown in;

[0030] Figure 3 is Figure 2 an enlarged view of part A of the memory cell (storage cell) shown in;

[0031] Figure 4 is Figure 2 an enlarged view of part B in;

[0032] Figure 5 shows simulation results of oxygen vacancy (Vo) formation energy and nitrogen vacancy (Vn) formation energy for resistive change layers of tantalum oxide (TaO), tantalum oxynitride (TaON), and tantalum nitride (TaN) obtained using a discrete Fourier transform (DFT);

[0033] Figure 6 shows simulation results of band gaps according to vacancy concentration for resistive change layers of TaO, TaON, and TaN obtained using DFT;

[0034] Figure 7A shows the structure of a variable resistance memory device according to a comparative example;

[0035] Figure 7B shows the structure of a variable resistance memory device according to one or more embodiments;

[0036] Figure 8A shows the result of Figure 7A the TaO resistive change layer shown in measured by transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM EDS);

[0037] Figure 8B Show the results of the TaON resistive change layer measured by using TEM EDS; Figure 7A as shown in;

[0038] Figure 9A Show Figure 7A the I-V characteristics of the variable resistance memory device according to the comparative example as shown in;

[0039] Figure 9B Show Figure 7B the I-V characteristics of the variable resistance memory device according to the embodiment as shown in;

[0040] Figure 10 Illustrate Figure 1 an example of the equivalent circuit diagram of the variable resistance memory device according to one or more embodiments as shown in;

[0041] Figure 11 Illustrate a variable resistance memory device according to another embodiment;

[0042] Figure 12 is a block diagram of a memory system according to one or more embodiments; and

[0043] Figure 13 is a block diagram showing a neuromorphic device according to one or more embodiments and external devices connected thereto. Detailed Description of the Invention

[0044] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0045] In the following description, the same reference numerals are used for the same elements even in different drawings. Matters defined in the specification, such as detailed configurations and elements, are provided to assist in a comprehensive understanding of the example embodiments. However, it is clear that the example embodiments can be practiced without those specifically defined matters. In addition, well-known functions or configurations are not described in detail because they may obscure the description with unnecessary details.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When the expression such as “… at least one (each)” is before or after a list of elements, it modifies the entire list of elements, rather than individual elements of the list.

[0047] It will also be understood that when an element is referred to as being “on” or “above” another element, the element can be in direct contact with the other element or there can be intervening elements. Unless the context clearly dictates otherwise, the singular forms include the plural forms. It should be understood that when a component “includes” or “comprises” an element in the specification, other elements are not excluded from the component unless otherwise defined and the component can further include other elements.

[0048] In the context of describing the present disclosure, the terms “a,” “an,” and “the” and similar reference terms are to be construed to cover both the singular and the plural. Unless otherwise stated herein or clearly contradicted by context, the steps of all methods described herein can be performed in any suitable order.

[0049] Although terms such as “first,” “second,” etc. may be used to describe various elements, such elements are not necessarily limited to the above terms. The above terms may be used only to distinguish one element from another.

[0050] In addition, terms such as “… unit,” “… module,” etc. refer to a unit that performs at least one function or operation, and the unit can be implemented as hardware or software or as a combination of hardware and software.

[0051] The connecting lines or connectors shown in the various figures presented are intended to represent exemplary functional relationships and / or physical or logical couplings between the various elements. It should be noted that there may be many alternative or additional functional relationships, physical connections, or logical connections in an actual device.

[0052] Unless otherwise stated, any and all uses of example or exemplary language provided herein are only intended to better illustrate the present disclosure and do not impose a limitation on the scope of the present disclosure.

[0053] Figure 1 is a perspective view schematically showing a variable resistance memory device 100 according to one or more embodiments. Figure 1 The variable resistance memory device 100 shown in may be, for example, a vertical NAND flash memory device.

[0054] Referring to Figure 1 , the variable resistance memory device 100 may include a plurality of cell strings CS disposed on a substrate 101. Each cell string CS may be disposed to extend in a direction ( Figure 1 the z-axis direction in ) perpendicular to the surface of the substrate 101 on which a plurality of cell strings CS are stacked. The z-axis direction may refer to the axial direction of the cell string. The plurality of cell strings CS may be arranged in various shapes on the substrate 101.

[0055] Figure 2 shows Figure 1 the cross-section of the cell string CS shown in Figure 3 is Figure 2 an enlarged view of part A of the memory cell MC shown in

[0056] Referring to Figure 2 and 3 ,the cell string CS includes a plurality of memory cells MC stacked in a direction perpendicular to the substrate 101 (i.e., the z-axis direction). The substrate 101 may include a variety of materials. For example, the substrate 101 may include, but is not limited to, a single-crystalline silicon substrate, a compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate. In addition, the substrate 101 may further include, for example, impurity regions doped therethrough, peripheral circuits for selecting and controlling electronic devices such as transistors, or memory cells for storing data.

[0057] The cell string CS includes an outermost layer OL, and the outermost layer OL includes a plurality of gate electrodes 121 stacked in the axial direction and spaced apart from each other. The outermost layer OL may also be referred to as a gate layer. The cell string CS further includes a gate insulating layer 123, a channel layer 125, and a resistive change layer 129, which are sequentially arranged inward in a direction from the outermost layer OL toward the center of the cell string CS (i.e., Figure 2 the x-axis direction in Figure 4 ). The x-axis direction may refer to the radial direction of the cell string CS. The gate insulating layer 123, the channel layer 125, and the resistive change layer 129 may each be arranged to extend perpendicular to the substrate 101 and may be shared by a plurality of memory cells MC. The source ( Figure 4 S in

[0058] The gate electrode 121 controls the corresponding channel layer 125, and the word line may be electrically connected to the gate electrode 121. A voltage for turning on / off the corresponding channel layer 120 may be selectively applied to the gate electrode 121.

[0059] The gate electrode 121 may include, for example, a metal material having excellent electrical conductivity such as gold (Au), a metal nitride, silicon doped with impurities, or a two-dimensional conductive material. However, this is only an example, and the gate electrode 121 may include a variety of other materials. The interlayer insulating layer 115 may be disposed between the gate electrodes 121, and the interlayer insulating layer 115 may serve as a spacer layer for insulation between the gate electrodes 121. The interlayer insulating layer 115 may include, for example, silicon oxide, silicon nitride, but is not limited thereto.

[0060] Channel holes are formed to penetrate the interlayer insulating layer 115 and the gate electrode 121 in the axial direction. For example, these channel holes may be formed to have a circular cross-section. The gate insulating layer 123, the channel layer 125, and the resistive change layer 129 are sequentially disposed on the inner wall of the channel holes in the radial direction. Here, the gate insulating layer 123, the channel layer 125, and the resistive change layer 129 may each be formed to have a cylindrical shape extending in a direction perpendicular to the substrate 101. The filling insulating layer 130 may be disposed inwardly with respect to the resistive change layer 129 to fill the channel holes. The filling insulating layer 130 may include, for example, silicon oxide or air, but is not limited thereto.

[0061] The channel layer 125 may include a semiconductor material. The channel layer 125 may include, for example, Si, Ge, SiGe, or a III-V group semiconductor. As an example, the channel layer 125 may include polycrystalline Si, but is not limited thereto. The channel layer 125 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include, for example, transition metal dichalcogenide (TMD) or graphene, and the quantum dots may include colloidal quantum dots (colloidal QD), nanocrystal structures, etc. However, this is only an example, and the present embodiment is not limited thereto.

[0062] The channel layer 125 may further include a dopant. Here, the dopant may include a p-type dopant or an n-type dopant. The p-type dopant may include, for example, group III elements such as boron (B), aluminum (Al), gallium (Ga), indium (In), and the n-type dopant may include, for example, group V elements such as phosphorus (P), arsenic (As), antimony (Sb).

[0063] The gate insulating layer 123 is disposed between the gate electrode 121 and the channel layer 125. The gate insulating layer 123 may include various types of insulating materials. For example, silicon oxide, silicon nitride, or oxynitride may be used in the gate insulating layer 123.

[0064] The resistive change layer 129 is disposed inwardly with respect to the channel layer 125. The resistive change layer 129 may include a material having a resistance characteristic that varies depending on the applied voltage. The resistive change layer 129 may include a metal nitride or a metal oxynitride. Here, the metal may include a transition metal. For example, the transition metal may include tantalum (Ta), titanium (Ti), molybdenum (Mo), vanadium (V), zinc (Zn), etc. However, this is only an example. In addition, the metal may include Al or Ga. As an example, the resistive change layer 129 may include a metal nitride such as tantalum nitride (TaN) or a metal oxynitride such as tantalum oxynitride (TaON).

[0065] The ratio of the nitrogen content in the resistive change layer 129 to the sum of the nitrogen content and the oxygen content (i.e., nitrogen content + oxygen content) may be about 0.01 or more to about 1 or less. Here, the content refers to the atomic percentage, which is the same hereinafter. When the resistive change layer 129 includes a metal nitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be 1. When the resistive change layer 129 includes a metal oxynitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be about 0.01 or more to less than about 1. For example, when the resistive change layer 129 includes a metal oxynitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be about 0.1 or more to about 0.9 or less.

[0066] When the resistive change layer 129 includes a metal nitride, the resistance characteristic of the resistive change layer 29 is determined by whether a conductive filament is formed due to the behavior of nitrogen occurring within the resistive change layer 129 according to the applied voltage. Specifically, when a certain voltage is applied to the resistive change layer 129, nitrogen vacancies Vn are formed within the resistive change layer 29, and the thus-formed nitrogen vacancies Vn aggregate to form a conductive filament. Nitrogen ions located in the nitrogen vacancies Vn move toward the channel layer 125 by diffusion. By forming the conductive filament, the resistance of the resistive change layer 129 decreases. That is, the resistive change layer 129 changes from a high resistance state (HRS) to a low resistance state (LRS). The HRS may be defined as having a resistance greater than a first predetermined value (e.g., 1 megaohm (MΩ)), and the LRS may be defined as having a resistance less than a second predetermined value (e.g., 100 kiloohm (kΩ)). When the resistive change layer 129 includes a metal oxynitride, a conductive filament may be formed through nitrogen vacancies and oxygen vacancies.

[0067] The resistive change layer 129 may have a low resistance state or a high resistance state depending on whether a conductive filament is formed, and may record information of "1" or "0" accordingly. The applied voltage that changes the resistive change layer 129 from the high resistance state to the low resistance state is called the set voltage V 设定 and the applied voltage that changes from the low resistance state to the high resistance state is called the reset voltage V 复位 .

[0068] The operation of the variable resistance memory device 100 described above will be described below with reference to Figure 4 FIG. Figure 4 is Figure 2 an enlarged view of part B of

[0069] With reference to Figure 4 FIG.

[0070] In Figure 4 FIG. 设定 or the reset voltage V 复位 , a desired information of 1 or 0 can be written into the selected memory cell MC2.

[0071] In the read operation, similarly, the selected memory cell MC2 can be read. That is, after adjusting the gate voltage applied to each gate electrode 121 such that the selected memory cell MC2 is in the channel-off state and the unselected memory cells MC1, MC3 are in the channel-on state, the state (1 or 0) of the memory cell MC2 can be identified by measuring the current flowing through the memory cell MC2 via the voltage V 读取 applied between the source S and the drain D.

[0072] In a variable resistance memory device according to the related art, an oxide such as HfO2 can be used as the resistance change layer, but in this case, the content of oxygen vacancies in the thin film formed by atomic layer deposition (ALD) is low, and thus it may be difficult to form a conductive filament, which may result in poor resistance change characteristics.

[0073] In the variable resistance memory device 100 according to the present embodiment, by using a metal nitride or a metal oxynitride as the resistance change layer, a conductive filament can be easily formed through nitrogen vacancies, and thus, the resistance change characteristics can be improved to reduce the operation voltage, and the yield can also be increased.

[0074] The following [Table 1] shows the band gap (Eg), oxygen vacancy (Vo) formation energy, and nitrogen vacancy (Vn) formation energy of tantalum oxide (TaO), TaON, and TaN resistive change layers. Figure 5 Shows simulation results of the oxygen vacancy (Vo) formation energy and nitrogen vacancy (Vn) formation energy of TaO, TaON, and TaN resistive change layers obtained using the discrete Fourier transform (DFT). In [Table 1] and Figure 5 "N / (O+N)" refers to the ratio of nitrogen content to the sum of oxygen content and nitrogen content, and the same hereinafter.

[0075] [Table 1]

[0076]

[0077] Referring to [Table 1] and Figure 5 , it can be seen that the oxygen vacancy (Vo) formation energy of the TaO resistive change layer is greater than the nitrogen vacancy (Vn) formation energy of the TaN resistive change layer. In addition, it can be seen that as N / (O+N) increases from 0.18 to 0.4 to 0.67, the nitrogen vacancy (Vn) formation energy first increases from 3.12 to 3.16 and then decreases from 3.16 to 1.05. As described above, it is easier to form nitrogen vacancies (Vn) than oxygen vacancies (Vo), and therefore, the TaN resistive change layer changes from the high resistance state (HRS) to the low resistance state (LRS) at a lower voltage than the TaO resistive change layer, and the yield can also be improved.

[0078] Figure 6 Shows simulation results of the band gap according to the vacancy concentration of TaO, TaON, and TaN resistive change layers obtained using DFT.

[0079] Referring to Figure 6 , conductive filaments can be formed at a lower vacancy concentration in the TaN resistive change layer or the TaON resistive change layer with a large nitrogen content. As vacancies are formed in the resistive change layer, the band gap (Eg) decreases due to an increase in trapping (traps) caused by dangling bonds. As Figure 6 shown, in the TaN resistive change layer or the TaON resistive change layer with a large nitrogen content, a low resistance state (i.e., Eg = 0) can be achieved with a smaller vacancy concentration, thereby reducing the operating voltage of the device. In addition, since the conductive filaments are not too thick due to the low vacancy concentration, the reset operation can be easy and the durability of the device can be improved.

[0080] Figure 7A Illustrates the structure of the variable resistance memory device 20 according to the comparative example. Referring to Figure 7A, the lower electrode 21 and the upper electrode 22 are disposed on one side of the channel layer 25, and the insulating layer 23 is disposed between the lower electrode 21 and the upper electrode 22. Further, a TaO resistive change layer 29 is disposed on the other side of the channel layer 25.

[0081] Figure 7B Shows the structure of a variable resistive memory device 200 according to one or more embodiments. Referring to Figure 7B , the lower electrode 210 and the upper electrode 220 are disposed on one side of the channel layer 225, and the insulating layer 223 is disposed between the lower electrode 210 and the upper electrode 220. In addition, a TaON resistive change layer 229 is disposed on the other side of the channel layer 225.

[0082] Figure 8A Shows the results of measuring the TaO resistive change layer 29 shown in Figure 7A using transmission electron microscopy (TEM EDS) with energy-dispersive X-ray spectroscopy. Referring to Figure 8A , it was found that the TaO resistive change layer 29 is a TaO thin film having a nitrogen content of 0 atomic percent (at%).

[0083] Figure 8B Shows the results of measuring the TaON resistive change layer 229 shown in Figure 7B using TEM EDS. Referring to Figure 8B , it was found that the TaON resistive change layer 229 is a TaON thin film having an N / (O + N) of 0.9.

[0084] Figure 9A Shows Figure 7A the I-V characteristics of the variable resistive memory device 20 according to the comparative example shown in Figure 9B Shows Figure 7B the I-V characteristics of the variable resistive memory device 200 according to the embodiment shown in

[0085] As Figure 9A shown in, even when a voltage of +10 V is applied, the TaO resistive change layer 29 does not show a resistance change characteristic from the high resistance state (HRS) to the low resistance state (LRS). Instead, the high voltage causes film separation in the resistive change layer, preventing current flow. However, as Figure 9B shown in, when a voltage of about +6 V is applied, a set operation is performed in the TaON resistive change layer 229 having a large nitrogen content. This is because the formation of nitrogen vacancies is easier than the formation of oxygen vacancies and the operating voltage is reduced by forming conductive filaments with a lower concentration of nitrogen vacancies. Referring to Figure 9B, a reset operation of changing from the low resistance state (LRS) to the high resistance state (HRS) again at a voltage of -4.5 V is performed. In addition, there are set / reset operations in the second cycle. As a result of the experiment on 36 devices, in the first cycle, a set operation exists in 81% of the devices in the TaON resistance change layer with N / (O+N) of 0.9, and in the second cycle, a set operation exists in 33% of the devices in the TaON resistance change layer with N / (O+N) of 0.9. In contrast, there is no switching in the TaO resistance change layer in the first and second cycles. Therefore, it can be seen that the TaON resistance change layer has a higher switching yield (switching success rate) than the TaO resistance change layer.

[0086] As described above, in the variable resistance memory device 100 according to the embodiment, by forming the resistance change layer 129 via using a metal nitride or a metal oxynitride, a conductive filament with a lower vacancy concentration can be formed, and thus the operation voltage can be reduced. In addition, because the conductive filament does not become too thick due to the low vacancy concentration, the reset operation can be easy, and the durability of the variable resistance memory device 100 can be improved.

[0087] Figure 10 shows Figure 1 An example of an equivalent circuit diagram of the variable resistance memory device 100 according to the embodiment shown in

[0088] Referring to Figure 10 , k*n cell strings CS can be provided and arranged in a matrix form, and are referred to as CSij (1≤i≤k, 1≤j≤n) according to the positions of each row and column. Each cell string CSij is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL. Each cell string CSij includes a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST of each cell string CSij can be stacked in the height direction.

[0089] Rows of the multiple cell strings CS are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk. Columns of the multiple cell strings CS are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and the string selection transistors SST of the cell strings CS11 to CSk1 can be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistors SST of the cell strings CS1n to CSkn can be commonly connected to the bit line BLn.

[0090] Rows of multiple cell strings CS can be respectively connected to different common source lines CSL1 to CSLk. For example, the string select transistors SST of cell strings CS11 to CS1n can be commonly connected to the common source line CSL1, and the string select transistors SST of cell strings CSk1 to CSk n can be commonly connected to the common source line CSLk. The gate electrodes 121 of the memory cells MC located at the same height from the substrate 101 or the string select transistors SST can be commonly connected to one word line WL, and the gate electrodes 121 of the memory cells MC located at different heights from each other can be respectively connected to different word lines WL1 to WL n.

[0091] Figure 10 The circuit structure shown is provided as an example, and the embodiments of the present disclosure are not limited thereto. For example, the number of rows of the cell strings CS can be increased or decreased. As the number of rows of the cell strings CS changes, the number of string select lines connected to the rows of the cell strings CS and the number of cell strings CS connected to one bit line can also change. As the number of rows of the cell strings CS changes, the number of common source lines connected to the rows of the cell strings CS can also change. The number of columns of the cell strings CS can also be increased or decreased. As the number of columns of the cell strings CS changes, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string select line can also change.

[0092] The height of the cell strings CS can also be increased or decreased. For example, the number of memory cells MC stacked in each cell string CS can be increased or decreased. As the number of memory cells MC stacked in each cell string CS changes, the number of word lines WL can also change. For example, the number of string select transistors provided for each cell string CS can be increased. As the number of string select transistors provided for each cell string CS changes, the number of string select lines or common source lines can also change. As the number of string select transistors increases, the string select transistors can be stacked in the same form as the memory cells MC.

[0093] For example, writing and reading can be performed in units of rows of the cell strings CS. The cell strings CS can be selected in units of rows through the common source line CSL, and the cell columns CS can be selected in units of rows through the string select line SSL. In addition, a voltage can be applied to the common source line CSL as a unit of at least two common source lines. The voltage can be applied to the common source line CSL as a single unit.

[0094] In the selected rows of the cell strings CS, writing and reading can be performed in units of pages. A page can be a row of memory cells connected to one word line WL. In the selected rows of the cell strings CS, the memory cells can be selected in units of pages through the word line WL.

[0095] The memory cell MC has the following circuit structure: A transistor including a gate electrode 121, a gate insulating layer 123, and a channel layer 125 is connected to a variable resistor formed through a resistance change layer 129 in parallel with each other. The parallel connection structure is continuously arranged in the vertical direction (z-axis direction) to form a cell string CS. In addition, a common source line CSL and a bit line BL can be connected to both ends of the cell string CS. By applying voltages to the common source line CSL and the bit line BL, programming, reading, and erasing processes can be performed on multiple memory cells MC.

[0096] For example, when a memory cell MC to be written is selected, the gate voltage value of the corresponding memory cell MC is adjusted such that no channel is formed in the selected memory cell MC, that is, the channel is turned off, and the gate voltage of the unselected memory cell MC is adjusted such that the channel of the unselected memory cell MC is turned on. Therefore, the current path of the voltage applied to the common source line CSL and the bit line BL passes through the resistance change layer 129 of the selected memory cell MC, and here, the applied voltage can be set to a set voltage V 设定 or a reset voltage V 复位 to form a low resistance state or a high resistance state, and desired information of 1 or 0 can be recorded in the selected memory cell MC.

[0097] In a read operation, similarly, reading of the selected cell can be performed. That is, after adjusting the gate voltage applied to each gate electrode 121 such that the selected memory cell MC is in a channel-off state and the unselected memory cell MCs are in a channel-on state, the state (1 or 0) of the corresponding memory cell MC can be identified by measuring the current flowing through the corresponding memory cell MC via a voltage V 读取 applied between the common source line CSL and the bit line BL.

[0098] The variable resistance memory device 100 as a vertical NAND flash memory device has been described above, where the memory cells MC are arranged in a direction perpendicular to the substrate 101 along the cell string CS. However, the present disclosure is not limited thereto, and as will be described later, a variable resistance memory device in which the memory cells are arranged in a direction parallel to the substrate can also be implemented.

[0099] Figure 11 A variable resistance memory device 300 according to another embodiment is shown. Hereinafter, the description will focus on the differences from the above-described embodiment.

[0100] Refer to Figure 11, a plurality of memory cells MC are arranged in a direction parallel to the substrate 301. A resistive change layer 329, a channel layer 325, and a gate insulating layer 323 may be sequentially stacked on the substrate 301 in a direction perpendicular to the substrate 301. On the gate insulating layer 323, a plurality of gate electrodes 321 are arranged spaced apart from each other in a direction parallel to the substrate 301, and an interlayer insulating layer 315 is provided between the gate electrodes 321, respectively.

[0101] A voltage for turning on / off the corresponding channel layer 325 may be selectively applied to the gate electrode 321. The channel layer 325 may include a semiconductor material. The channel layer 325 may further include a dopant. Both ends of the channel layer 325 may be connected to a source S and a drain D, respectively.

[0102] The resistive change layer 329 may include a material having a resistance characteristic that varies according to an applied voltage. The resistive change layer 329 may include a metal nitride or a metal oxynitride. Herein, the metal may include a transition metal. For example, the transition metal may include Ta, Ti, Mo, V, Zn, etc. However, this is only an example. In addition, the metal may include Al or Ga. As an example, the resistive change layer 329 may include a metal nitride such as TaN or a metal oxynitride such as TaON.

[0103] The ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content in the resistive change layer 329 may be about 0.01 or more to about 1 or less. Herein, the content refers to the atomic percentage, which is the same hereinafter. When the resistive change layer 329 includes a metal nitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be 1. When the resistive change layer 329 includes a metal oxynitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be about 0.01 or more to less than about 1. For example, when the resistive change layer 329 includes a metal oxynitride, the ratio of the nitrogen content to the sum of the nitrogen content and the oxygen content may be about 0.1 or more to about 0.9 or less.

[0104] In the variable resistive memory device according to the present embodiment, by using a metal nitride or a metal oxynitride as the resistive change layer, a conductive filament can be easily formed through nitrogen vacancies, and thus the operating voltage can be reduced and the yield can be improved.

[0105] The variable resistive memory devices 100 and 300 according to the above embodiment can be used as a memory system for various electronic devices. The variable resistive memory devices 100 and 300 can be implemented as a chip-shaped storage block (storage area) and used as a neuromorphic computing platform, or can be used to configure a neural network.

[0106] Figure 12 is a block diagram of a memory system 1600 according to one or more embodiments.

[0107] Refer to Figure 12, the memory system 1600 may include a memory controller 1601 and a memory device 1602. The memory controller 1601 performs control operations on the memory device 1602. For example, the memory controller 1601 may provide an address ADD and a command CMD to the memory device 1602 to perform programming (or recording), reading, and / or erasing operations on the memory device 1602. In addition, data for programming operations and read data may be transferred between the memory controller 1601 and the memory device 1602.

[0108] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines cross each other. The memory cell array 1610 may include variable resistance memory devices 100 and 300 according to the above embodiments.

[0109] The memory controller 1601 may include processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. Examples of the processing circuitry may include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), programmable logic, a microprocessor, an application specific integrated circuit (ASIC), etc., but are not limited thereto. The memory controller 1601 may operate in response to a request from a host and may be configured to access the memory device 1602 and control the above control operations (e.g., write / read operations) to convert the memory controller 1601 into a dedicated controller. The memory controller 1601 may generate an address ADD and a command CMD to perform programming / reading / erasing operations on the memory cell array 1610. In addition, in response to a command from the memory controller 1601, the voltage generator 1620 (e.g., a power supply circuit) may generate a voltage control signal to control the voltage level of the word line for programming the memory cell array 1610 or reading data from the memory cell array 1610.

[0110] In addition, the memory controller 1601 may perform a decision operation on the data read from the memory device 1602. For example, based on the data read from the memory cells, the number of turned-on cells and / or the number of turned-off cells may be determined. The memory device 1602 may provide a pass / fail signal P / F to the memory controller 1601 according to the read result of the read data. The memory controller 1601 may control the write and read operations of the memory cell array 1610 by referring to the pass / fail signal P / F.

[0111] Figure 13is a block diagram showing a neuromorphic device 1700 and external devices connected thereto according to one or more embodiments.

[0112] Referring to Figure 13 , the neuromorphic device 1700 may include processing circuitry 1710 and on-chip memory 1720. The neuromorphic device 1700 may include variable resistance memory devices 100 and 300 according to the above embodiments.

[0113] In some embodiments, the processing circuitry 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuitry 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuitry may include hardware such as logic circuitry, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, but is not limited thereto. In some embodiments, the processing circuitry 1710 may be configured to read various data from or write various data to the external device 1730, and / or execute the neuromorphic device 1700 by using the read / written data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor circuit).

[0114] In some embodiments, Figure 13 the neuromorphic device 1700 may be applied to a machine learning system. As the machine learning system, various artificial neural network systems and processing models may be used, such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) (optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRU)), a stacked neural network (SNN), a state space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM).

[0115] Alternatively or additionally, these machine learning systems may be implemented using other forms of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or ensembles such as random forests or combinations thereof. These machine learning models may be used to provide various services and / or applications, and for example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistance services, automatic speech recognition (ASR) services, etc. may be executed by an electronic device.

[0116] According to the above-described embodiments, by forming a resistive change layer via using a metal nitride or a metal oxynitride, a conductive filament can be formed with a lower vacancy concentration, and thus the operation voltage can be reduced. In addition, since the conductive filament is not overly thick due to the low vacancy concentration, the reset operation can be easy, and the durability of the memory device can be improved. The variable resistive memory devices 100 and 300 have been described above according to the embodiments shown in the drawings. However, these descriptions are merely examples, and those of ordinary skill in the art can understand that various modifications and equivalent embodiments are possible from the descriptions.

[0117] The above-described exemplary embodiments are merely exemplary and should not be construed as restrictive. The present teachings can be easily applied to other types of devices. In addition, the description of the exemplary embodiments is intended to be illustrative and does not limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A variable resistance memory device, comprising: A resistance change layer having a resistance characteristic that changes according to a voltage applied to the resistance change layer; A channel layer provided on the resistance change layer; And A gate electrode provided on the channel layer, Wherein the resistance change layer includes a metal nitride or a metal oxynitride.

2. A variable resistance memory device, comprising a plurality of cell strings, wherein the plurality of cell strings each extend vertically on a substrate and include: A channel layer; A resistance change layer provided inwardly with respect to the channel layer, the resistance change layer having a resistance characteristic that changes according to a voltage applied to the resistance change layer; And A plurality of gate electrodes provided outwardly with respect to the channel layer, Wherein the resistance change layer includes a metal nitride or a metal oxynitride.

3. The variable resistance memory device according to claim 2, wherein a channel hole extending in a direction perpendicular to the substrate is formed inwardly with respect to the channel layer.

4. The variable resistance memory device according to claim 3, wherein the channel layer and the resistance change layer are each formed in a cylindrical shape surrounding the channel hole.

5. The variable resistance memory device according to claim 4, wherein the plurality of gate electrodes are arranged at intervals of each other in a direction perpendicular to the substrate, and the plurality of gate electrodes surround the channel layer.

6. The variable resistance memory device according to claim 5, further comprising an interlayer insulating layer provided between the plurality of gate electrodes.

7. A variable resistance memory device, comprising a cell string, wherein the cell string includes: A gate layer including a plurality of gate electrodes spaced apart from each other in an axial direction of the cell string; A plurality of inner layers provided inwardly from the gate layer toward the center of the cell string in a radial direction, wherein the plurality of inner layers include: A resistance change layer having a resistance that changes according to a voltage applied to the resistance change layer; And A channel layer provided between the resistance change layer and the gate layer in a radial direction, and Wherein the resistance change layer includes a metal nitride or a metal oxynitride.

8. The variable resistance memory device according to claim 1, 2 or 7, wherein a ratio of a nitrogen content in the resistance change layer to a sum of the nitrogen content and an oxygen content is in a range of 0.01 to 1.

9. The variable resistance memory device according to claim 8, wherein the ratio of the nitrogen content in the resistance change layer to the sum of the nitrogen content and the oxygen content is less than or equal to 0.

9.

10. The variable resistance memory device according to claim 1, 2 or 7, wherein the resistance change layer includes tantalum nitride (TaN) or tantalum oxynitride (TaON).

11. The variable resistance memory device according to claim 1, 2 or 7, wherein the metal includes a transition metal, aluminum (Al), or gallium (Ga).

12. The variable resistance memory device according to claim 1, 2 or 7, wherein the channel layer includes silicon (Si), germanium (Ge), silicon germanium (SiGe), a III-V group semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor material, a quantum dot, or an organic semiconductor.

13. The variable resistance memory device according to claim 1, 2 or 7, wherein the gate electrode comprises a metal material, a metal nitride, silicon doped with impurities, or a two-dimensional conductive material.

14. The variable resistance memory device according to claim 1, 2 or 7, further comprising a gate insulating layer disposed between the gate electrode and the channel layer.

15. The variable resistance memory device according to claim 14, wherein the gate insulating layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

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