Interconnection method of stacked transistor and stacked transistor

Abstract

The invention provides an interconnection method of a stacked transistor and the stacked transistor. The method comprises the following steps: forming an active structure on a semiconductor substrate; forming a front stacked transistor based on the first active structure; forming a first metal interconnection layer on the front stacked transistor; forming a reverse stacked transistor based on the second active structure; forming a second metal interconnection layer on the reverse stacked transistor; wherein a front dielectric layer and a plurality of front metal interconnection structures formed based on the front dielectric layer are formed between the front stacked transistor and the first metal interconnection layer; the front metal interconnection structure is used for communicating the source drain metal of the front transistor with the first metal interconnection layer; and / or, a reverse dielectric layer and a plurality of reverse metal interconnection structures formed based on the reverse dielectric layer are formed between the reverse stacked transistor and the second metal interconnection layer; and the reverse metal interconnection structure is used for communicating the source drain metal of the reverse transistor with the second metal interconnection.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and particularly to an interconnection method for stacked transistors and a stacked transistor. Background Art

[0002] At present, with the continuous deepening of Moore's Law, further promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can achieve further improvement in transistor integration density, and become one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for manufacturing stacked transistors, the active regions of the upper and lower layers of homogeneous transistors are formed by etching, and the stacked transistors are fabricated on the front and back sides of the wafer through wafer flipping. This can also be called the "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, if the front transistor or the back transistor is a stacked transistor, there are problems such as difficult routing for the front transistor or the back transistor, and it is difficult to adapt to complex logic circuits. Summary of the Invention

[0004] This application provides an interconnection method for stacked transistors and a stacked transistor to meet the requirements of connecting all transistors to the metal interconnection layer, and further optimize and improve the interconnection performance of the stacked transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for interconnecting stacked transistors, including: forming an active structure on a semiconductor substrate, where the active structure includes a first active structure and a second active structure stacked along a first direction, and the first active structure is farther from the semiconductor substrate than the second active structure; forming a front stacked transistor based on the first active structure, where the front stacked transistor includes at least two front transistors stacked along the first direction; forming a first metal interconnect layer above the front stacked transistor, and the first metal interconnect layer is used to connect the front stacked transistor to an external circuit; flipping the wafer and removing the semiconductor substrate; forming a back stacked transistor based on the second active structure, where the back stacked transistor includes at least two back transistors stacked along the first direction; forming a second metal interconnect layer above the back stacked transistor, and the second metal interconnect layer is used to connect the back stacked transistor to an external circuit; where a front dielectric layer is formed between the front stacked transistor and the first metal interconnect layer, and a plurality of front metal interconnect structures are formed based on the front dielectric layer; the front metal interconnect structures are used to connect the source / drain metals of the front transistors to the first metal interconnect layer, and one front metal interconnect structure corresponds to one front transistor; and / or, a back dielectric layer is formed between the back stacked transistor and the second metal interconnect layer, and a plurality of back metal interconnect structures are formed based on the back dielectric layer; the back metal interconnect structures are used to connect the source / drain metals of the back transistors to the second metal interconnect layer, and one back metal interconnect structure corresponds to one back transistor.

[0006] In some embodiments, forming a first metal interconnect layer above the front stacked transistor includes: depositing a dielectric material above the front stacked transistor to form a first dielectric layer; etching the first dielectric layer until the source / drain metals of a plurality of front transistors among at least two front transistors are exposed to form a plurality of first interconnect vias, and depositing a metal material in the plurality of first interconnect vias to form a plurality of first metal interconnect structures; where one first interconnect via connects the source / drain metal of one front transistor, and one first interconnect via correspondingly forms one first metal interconnect structure; depositing a dielectric material above the first dielectric layer to form a second dielectric layer, and forming a second metal interconnect structure in the second dielectric layer, where the second metal interconnect structure has a preset width in a second direction so that a first end of the second metal interconnect structure is connected to the first interconnect via, and a second end of the second metal interconnect structure is connected to the first metal interconnect layer; the first dielectric layer and the second dielectric layer are included in the front dielectric layer, and one first metal interconnect structure and one second metal interconnect structure correspondingly form one front metal interconnect structure; forming the first metal interconnect layer above the second dielectric layer.

[0007] In some embodiments, on top of the second dielectric layer, a first metal interconnect layer is formed, including: depositing a dielectric material on top of the second dielectric layer to form a third dielectric layer; etching the third dielectric layer to form a second via hole, and depositing a metal material in the second via hole to form a first metal hole structure 34; depositing a dielectric material on top of the third dielectric layer to form a fourth dielectric layer, and forming a first metal wire structure in the fourth dielectric layer, wherein the first metal hole structure 34 is used to connect the second metal interconnect structure and the first metal wire structure, and the first metal wire structure is used to connect to an external circuit.

[0008] In some embodiments, a front stacked transistor includes: a first transistor and a second transistor, the first transistor being closer to the back stacked transistor than the second transistor; forming a front stacked transistor based on a first active structure, including: forming a first dummy gate structure based on the first active structure, wherein the first dummy gate structure is a dummy gate structure shared by the first transistor and the second transistor; forming a first source / drain structure based on the first active structure; forming a first source / drain metal on top of the first source / drain structure; forming a front isolation structure on top of the first source / drain metal, the front isolation structure being used to electrically isolate the first transistor and the second transistor; forming a second source / drain structure on top of the front isolation structure based on the first active structure; removing the first dummy gate structure to form a first gate structure and a second gate structure; forming a second source / drain metal on top of the second source / drain structure.

[0009] In some embodiments, multiple front metal interconnect structures include: a first front metal interconnect structure and a second front metal interconnect structure; the first front metal interconnect structure connects the first source / drain metal and the first metal interconnect layer, and the second front metal interconnect structure connects the second source / drain metal and the first metal interconnect layer.

[0010] In some embodiments, a second metal interconnect layer is formed over the back-side stacked transistors, comprising: depositing a dielectric material over the back-side stacked transistors to form a fifth dielectric layer; etching the fifth dielectric layer until the source / drain metals of multiple back-side transistors among at least two back-side transistors are exposed to form a plurality of third interconnect vias, and depositing a metal material in the plurality of third interconnect vias to form a plurality of third metal interconnect structures; wherein one third interconnect via communicates with the source / drain metal of one back-side transistor, and one third interconnect via correspondingly forms one third metal interconnect structure; depositing a dielectric material over the fifth dielectric layer to form a sixth dielectric layer, and forming a fourth metal interconnect structure in the sixth dielectric layer, wherein the fourth metal interconnect structure has a preset width in a second direction, such that a first end of the fourth metal interconnect structure is connected to the third interconnect via, and a second end of the fourth metal interconnect structure is connected to the second metal interconnect layer; the fifth dielectric layer and the sixth dielectric layer are included in the back-side dielectric layer, and one third metal interconnect structure and one fourth metal interconnect structure correspondingly form one back-side metal interconnect structure; a second metal interconnect layer is formed over the sixth dielectric layer.

[0011] In some embodiments, a second metal interconnect layer is formed over the sixth dielectric layer, comprising: depositing a dielectric material over the sixth dielectric layer to form a seventh dielectric layer; etching the seventh dielectric layer to form a fourth interconnect via, and depositing a metal material in the fourth interconnect via to form a second metal via structure; depositing a dielectric material over the seventh dielectric layer to form an eighth dielectric layer, and forming a second metal wire structure in the eighth dielectric layer, wherein the second metal via structure is used to communicate the fourth metal interconnect structure and the second metal wire structure, and the second metal wire structure is used to communicate with an external circuit.

[0012] In some embodiments, the back-side stacked transistors include: a third transistor and a fourth transistor, the third transistor being closer to the front-side stacked transistors than the fourth transistor; forming the back-side stacked transistors based on a second active structure, comprising: forming a second pseudo-gate structure based on the second active structure, wherein the second pseudo-gate structure is a shared pseudo-gate structure for the third transistor and the fourth transistor; forming a third source / drain structure based on the second active structure; forming a third source / drain metal over the third source / drain structure; forming a back-side isolation structure over the third source / drain metal, the back-side isolation structure being used to electrically isolate the third transistor and the fourth transistor; forming a fourth source / drain structure based on the second active structure over the back-side isolation structure; removing the second pseudo-gate structure to form a third gate structure and a fourth gate structure; forming a fourth source / drain metal over the fourth source / drain structure.

[0013] In some embodiments, the multiple backside metal interconnect structures include: a first backside metal interconnect structure and a second backside metal interconnect structure; the first backside metal interconnect structure is connected to the third source / drain metal and the second metal interconnect layer, and the second backside metal interconnect structure is connected to the fourth source / drain metal and the second metal interconnect layer.

[0014] In a second aspect, an embodiment of the present application provides a stacked transistor. The stacked transistor includes: a front-side stacked transistor and a first metal interconnect layer located above the front-side stacked transistor; the front-side stacked transistor includes: at least two front-side transistors stacked along a first direction; the first metal interconnect layer is used to connect the front-side stacked transistor to an external circuit; a back-side stacked transistor and a second metal interconnect layer located above the back-side stacked transistor; the back-side stacked transistor includes: at least two back-side transistors stacked along the first direction; the second metal interconnect layer is used to connect the back-side stacked transistor to the external circuit; the front-side stacked transistor and the back-side stacked transistor are stacked along the first direction, and a first active structure in the front-side stacked transistor and a second active structure in the back-side stacked transistor form an active structure; wherein, a front-side dielectric layer is formed between the front-side stacked transistor and the first metal interconnect layer, and multiple front-side metal interconnect structures are formed based on the front-side dielectric layer; the front-side metal interconnect structures are used to connect the source / drain metals of the front-side transistors to the first metal interconnect layer, and one front-side metal interconnect structure corresponds to one front-side transistor; and / or, a back-side dielectric layer is formed between the back-side stacked transistor and the second metal interconnect layer, and multiple back-side metal interconnect structures are formed based on the back-side dielectric layer; the back-side metal interconnect structures are used to connect the source / drain metals of the back-side transistors to the second metal interconnect layer, and one back-side metal interconnect structure corresponds to one back-side transistor.

[0015] In some embodiments, the front-side stacked transistor includes: a first metal interconnect structure and a second metal interconnect structure; one end of the first metal interconnect structure is connected to the source / drain structure in the front-side transistor, one end of the first metal interconnect structure is connected to one end of the second metal interconnect structure, and the other end of the second metal interconnect structure is connected to the first metal interconnect layer; the back-side stacked transistor includes: a third metal interconnect structure and a fourth metal interconnect structure; one end of the third metal interconnect structure is connected to the source / drain structure in the back-side transistor, one end of the third metal interconnect structure is connected to one end of the fourth metal interconnect structure, and the other end of the fourth metal interconnect structure is connected to the second metal interconnect layer.

[0016] In the embodiments of the present disclosure, by etching an active structure on a semiconductor substrate at one time, it is possible to achieve self-alignment of the active regions of the upper and lower transistors in the stacked transistors. Subsequently, based on the first active structure and the second active structure in the active structure, a front stacked transistor and a back stacked transistor can be respectively fabricated. Among them, a plurality of front metal interconnect structures are formed on the front stacked transistor, and the plurality of front metal interconnect structures are used to connect the source / drain metals of different front transistors in the front stacked transistor to the first metal interconnect layer; alternatively, a plurality of back metal interconnect structures are formed on the back stacked transistor, and the plurality of back metal interconnect structures are used to connect the source / drain metals of different back transistors in the back stacked transistor to the second metal interconnect layer. In this way, it is possible to connect the source / drain metal of any transistor to the metal interconnect layer formed in the subsequent process, thereby meeting the connection requirements of all transistors to the metal interconnect layer and further optimizing and improving the interconnect performance of the stacked transistors.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with this application and used together with the specification to explain the principles of this application.

[0019] Figure 1 FIG. is a top view of a stacked transistor shown according to an embodiment of this application;

[0020] Figure 2 FIG. is a schematic flowchart of an implementation process of a preparation method of a stacked transistor shown according to an embodiment of this application;

[0021] Figures 3 to 36 FIG. is a schematic diagram of a preparation process of a stacked transistor shown according to an embodiment of this application;

[0022] Figure 37 FIG. is a schematic diagram of a structure of a stacked transistor shown according to an embodiment of this application.

[0023] In the above figures: 10, stacked transistors; 101, front stacked transistors; 102, back stacked transistors; 11, first transistor; 12, second transistor; 13, third transistor; 14, fourth transistor; 111, first dummy gate sidewall; 112, first source / drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source / drain metal; 116, first metal interconnect layer; 121, second dummy gate sidewall; 122, second source / drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source / drain metal; 126, second metal interconnect layer; 127, front dielectric structure; 131, third dummy gate sidewall; 132, third source / drain structure; 133, third interlayer dielectric layer; 134, third gate structure; 135, third source / drain metal; 141, fourth dummy gate sidewall; 142, fourth source / drain structure; 143, fourth interlayer dielectric layer; 144, fourth gate structure; 145, fourth source / drain metal; 147, back dielectric structure;

[0024] 20, semiconductor substrate; 21, first active structure; 211, first sacrificial layer; 212, first part; 213, second part; 214, second sacrificial layer; 22, second active structure; 221, third sacrificial layer; 222, third part; 223, fourth part; 224, fourth sacrificial layer; 23, stacked structure; 24, isolation layer; 25, shallow trench isolation structure; 26, first dummy gate structure; 27, first trench; 28, front isolation structure; 29, initial first trench; 30, first barrier layer; 31, cell isolation structure; 32, first interconnect via; 33, front metal groove; 34, first metal via structure; 35, first metal wire structure; 36, second dummy gate structure; 37, back isolation structure; 38, third interconnect via; 39, back metal groove; 40, second metal via structure; 41, second metal wire structure; 42, source / drain metal interconnect structure; 43, carrier wafer;

[0025] 51, first dielectric layer; 52, second dielectric layer; 53, third dielectric layer; 54, fourth dielectric layer; 55, fifth dielectric layer; 56, sixth dielectric layer; 57, seventh dielectric layer; 58, eighth dielectric layer; 61, first metal interconnect structure; 62, second metal interconnect structure; 63, third metal interconnect structure; 64, fourth metal interconnect structure. Detailed Description of the Embodiments

[0026] Here, the exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0027] In the current context of the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in the vertical space through three-dimensional transistor stacking, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0028] In one embodiment, there are two schemes for the manufacturing process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0029] For the first scheme, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, that is, NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it must rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0030] For the second scheme, it is based on wafer bonding and processed layer by layer. Specifically, the upper layer transistors are fabricated by bonding a wafer on top of the previously fabricated lower layer transistors, stacking two transistors vertically. However, during the thermal process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and interconnects. The advantage of this scheme is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matched device performance.

[0031] To solve the technical problems existing in the above two schemes, a flip-chip scheme for realizing self-aligned stacked transistors is proposed. This flip-chip scheme forms the active regions of the upper and lower layer homologous transistors through etching, and realizes the fabrication of stacked transistors on the front and back sides of the wafer by flipping the wafer, so as to overcome the disadvantages of the above two schemes. This can also be called the "self-aligned flip-chip transistor" scheme.

[0032] However, in the "self-aligned flip-chip transistor" solution, if the front-side transistor or the back-side transistor is a stacked transistor stacked along the first direction, although the transistor integration density can be greatly increased, which is beneficial to the continuous advancement of Moore's Law. However, as the number of transistors in the first direction increases, new challenges are posed to the implementation of different logic circuit designs. For example, if the connection between the source or drain of each transistor in the first direction and the first metal layer (metal layer M0) cannot be achieved within a limited area overhead, it will pose a severe challenge to the large-scale application of flip-chip complementary transistors.

[0033] In the related art, via vias are formed on both sides of the active region to solve the mid-channel vertical interconnection problem between stacked transistors of each layer. However, in the related art, the source-drain metal of the front-side transistor or the back-side transistor is not directly below the metal layer M0, so it is impossible to ensure that the source-drain metal of each transistor is directly connected to the metal layer M0 through a vertical via. It can be seen that in the related art, there are problems that the routing of the front-side transistor or the back-side transistor is difficult and it is difficult to adapt to complex logic circuits.

[0034] In a first aspect, an embodiment of the present application provides a stacked transistor. Figure 1 FIG. is a top view of a stacked transistor shown according to an embodiment of the present application. Refer to Figure 1 As shown, only the fin structure, gate structure, and source-drain structure of the stacked transistor 10 are shown in the top view. It can be understood that based on the different types of stacked transistors, the structure of the fin structure can be different.

[0035] Exemplarily, when the stacked transistor 10 is a fin field-effect transistor, the fin structure can be formed by depositing a single semiconductor material. When the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet) field-effect transistor, the fin structure can be formed by alternately depositing a semiconductor material and a sacrificial layer material; for example, it can be formed by alternately depositing a silicon layer and a silicon-germanium layer. The embodiments of the present application do not limit this.

[0036] Figure 2 FIG. is a schematic flowchart of an implementation process of a method for manufacturing a stacked transistor shown according to an embodiment of the present application. Refer to Figure 2 As shown, the method for manufacturing a stacked transistor may include:

[0037] Step S201: Form an active structure on a semiconductor substrate, where the active structure includes: a first active structure and a second active structure stacked along a first direction, and the first active structure is farther from the semiconductor substrate than the second active structure.

[0038] Step S202: Based on the first active structure, form a front stacked transistor, where the front stacked transistor includes at least two front transistors stacked along a first direction;

[0039] Step S203: Above the front stacked transistor, form a first metal interconnect layer for connecting the front stacked transistor to an external circuit;

[0040] Step S204: Flip the wafer and remove the semiconductor substrate;

[0041] Step S205: Based on the second active structure, form a back stacked transistor, where the back stacked transistor includes at least two back transistors stacked along the first direction;

[0042] Step S206: Above the back stacked transistor, form a second metal interconnect layer for connecting the back stacked transistor to the external circuit;

[0043] Wherein, a front dielectric layer and a plurality of front metal interconnect structures formed based on the front dielectric layer are formed between the front stacked transistor and the first metal interconnect layer; the front metal interconnect structures are used to connect the source / drain metals of the front transistors to the first metal interconnect layer, and one front metal interconnect structure corresponds to one front transistor; and / or, a back dielectric layer and a plurality of back metal interconnect structures formed based on the back dielectric layer are formed between the back stacked transistor and the second metal interconnect layer; the back metal interconnect structures are used to connect the source / drain metals of the back transistors to the second metal interconnect layer, and one back metal interconnect structure corresponds to one back transistor.

[0044] In some embodiments, the first metal interconnect layer includes a first layer of metal (metal layer M0) and a second layer of metal (metal layer M1). In one embodiment, the metal layer M0 can be used to generate the power supply and ground rails of the standard cell, that is, the metal layer M0 is used for the wiring of the power supply and ground wires. The M1 metal layer is used to connect to the metal layer M0 and other metal layers (such as the M2 metal layer, M3 metal layer, etc.) through vias to form a complete circuit. In some embodiments, the second metal interconnect layer has the same structure as the first metal interconnect layer.

[0045] In some embodiments, the external circuit can be a circuit connecting the transistors. For example, the external circuit can be a power supply circuit, a protection circuit, etc. In one embodiment, the transistors and the external circuit can jointly form a logic circuit. For example, the logic circuit can be a logic gate circuit, a switch circuit, etc.

[0046] In some embodiments, step S201 may include: forming an active structure by performing a single etching on a semiconductor substrate. It can be understood that by performing processes such as material layer deposition and epitaxial growth on the semiconductor substrate, a stacked structure is formed on the semiconductor substrate. Subsequently, a single etching process can be used to etch the stacked structure to form an active structure on the semiconductor substrate.

[0047] In some embodiments, the material for forming each layer in the stacked structure can be selected according to the type of transistor to be fabricated, and the embodiments of the present application do not limit this.

[0048] In some embodiments, the active structure includes a first active structure and a second active structure, and the first active structure and the second active structure are stacked along a first direction (a direction perpendicular to the semiconductor substrate), and the second active structure is closer to the semiconductor substrate than the first active structure.

[0049] It can be understood that the first active structure is used to form the active regions of multiple front transistors in the front stacked transistors in subsequent steps; the second active structure is used to form the active regions of multiple back transistors in the back stacked transistors.

[0050] It should be noted that the front stacked transistors are fabricated based on the front side of the semiconductor substrate, and after the stacked transistors are fabricated, the front stacked transistors are located at the bottom layer of the stacked transistors. The back stacked transistors are opposite to the front stacked transistors.

[0051] In some embodiments, step S201 may include: forming an isolation layer between the first active structure and the second active structure, thereby electrically isolating the first active structure and the second active structure to avoid current interference between the circuits of the front stacked transistors and the circuits of the back stacked transistors. In one embodiment, the isolation layer may be a buried oxide layer or a dielectric layer. Here, the process for forming the buried oxide layer or the dielectric layer can be set according to actual requirements, and the embodiments of the present application do not limit this. In one embodiment, the isolation layer may be an ion implantation layer. Here, the process for forming the ion implantation layer can be set according to actual requirements, and the embodiments of the present application do not limit this.

[0052] In some embodiments, step S202 may include: successively forming at least two front transistors stacked along the first direction based on the standard process for semiconductor fabrication. It can be understood that the front stacked transistors can be formed by multiple front transistors stacked along the first direction. These multiple front transistors can be self-aligned in the first direction. The fabrication method of the multiple front transistors can refer to the related art, and the embodiments of the present application do not limit this.

[0053] In one embodiment, each front transistor includes a source-drain structure and a gate structure. The manufacturing method of each front transistor can be a sequential scheme or a monolithic scheme. In one embodiment, in the monolithic scheme, the top source-drain metal can be formed before the metal gate is formed or after the metal gate is formed. In one embodiment, multiple front transistors can be a common-gate scheme or a split-gate scheme. In one embodiment, the source-drain structures of multiple front transistors can have the same or different polarities.

[0054] In some embodiments, the front stacked transistor includes: a first transistor and a second transistor, and the first transistor is closer to the back stacked transistor than the second transistor; step S202 may include: forming a first dummy gate structure based on the first active structure, where the first dummy gate structure is a dummy gate structure shared by the first transistor and the second transistor; forming a first source-drain structure based on the first active structure; forming a first source-drain metal on the first source-drain structure; forming a front isolation structure on the first source-drain metal, and the front isolation structure is used to electrically isolate the first transistor and the second transistor; forming a second source-drain structure on the front isolation structure based on the first active structure; removing the first dummy gate structure to form a first gate structure and a second gate structure; forming a second source-drain metal on the second source-drain structure.

[0055] It can be understood that when the front stacked transistor only includes the first transistor and the second transistor, the first transistor and the second transistor can be formed by using a common-gate process. And, a front isolation structure can be formed between the first transistor and the second transistor to electrically isolate the first transistor and the second transistor.

[0056] In some embodiments, the polarities of the first transistor and the second transistor are opposite, so that the front stacked transistor can be a complementary stacked transistor.

[0057] In some embodiments, step S203 may include: depositing a dielectric material on the front stacked transistor to form a first dielectric layer; etching the first dielectric layer until the source-drain metals of multiple front transistors among at least two front transistors are exposed to form multiple first interconnect vias, and depositing a metal material in the multiple first interconnect vias to form multiple first metal interconnect structures; depositing a dielectric material on the first dielectric layer to form a second dielectric layer, and forming a second metal interconnect structure in the second dielectric layer; forming a first metal interconnect layer on the second dielectric layer.

[0058] It can be understood that after fabricating the front-side stacked transistors, a first metal interconnect layer can be formed on the front-side stacked transistors. Before forming the first metal interconnect layer, a front-side dielectric layer between the front-side stacked transistors and the first metal interconnect layer, and multiple front-side metal interconnect structures formed based on the front-side dielectric layer can also be formed. Each metal interconnect structure among the multiple front-side metal interconnect structures is used to connect the source / drain structure in the first metal interconnect layer and one front-side transistor. The multiple front-side metal interconnect structures can meet the connection requirements of the source / drain structures of all front-side transistors and the first metal interconnect layer.

[0059] It can be understood that the fabrication process for fabricating the front-side metal interconnect structures can be the Dual-Damascene process. The Dual-Damascene process can include: first fabricating and forming a first metal interconnect structure, and then fabricating and forming a second metal interconnect structure. Among them, the second metal interconnect structure has a preset width in the second direction, so that the first end of the second metal interconnect structure is connected to the first metal interconnect structure, and the second end of the second metal interconnect structure is connected to the first metal interconnect layer. It can be understood that by using the Dual-Damascene process, a metal interconnect structure in the VHV (vertical-horizontal-vertical) form can be formed. Among them, the vertical metal in the VHV-form metal interconnect structure is the first metal interconnect structure, and the horizontal metal in the VHV-form metal interconnect structure is the second metal interconnect structure. The second direction is a direction perpendicular to the first direction.

[0060] It can be understood that whether the VHV-form metal interconnect structure can connect the source / drain metal and the metal interconnect layer depends on the length of the horizontal metal in the VHV-form metal interconnect structure in the second direction. When one end of the second metal interconnect structure is connected to the first metal interconnect structure and the other end is connected to the metal interconnect layer, the source / drain electrodes of the transistor can be connected to the metal layer M0.

[0061] It can be understood that by forming a first dielectric layer, then etching the first dielectric layer and the dielectric layer wrapping the source / drain structure based on the positions of the source / drain structures of the front-side transistors, a first interconnect via can be formed, and then depositing a metal material in the first interconnect via, a first metal interconnect structure can be formed. Among them, one first interconnect via connects the source / drain metal of one front-side transistor, and one first interconnect via correspondingly forms one first metal interconnect structure.

[0062] It can be understood that by forming a second dielectric layer on top of the first dielectric layer and then etching the second dielectric layer based on the positions of the first metal interconnect structure and the first metal interconnect layer, a front metal groove can be formed. Here, the length of the front metal groove in the second direction is related to the positions of the first metal interconnect structure and the first metal interconnect layer in the second direction. By depositing a metal material in the front metal groove, a second metal interconnect structure can be formed. Among them, one first metal interconnect structure and one second metal interconnect structure can correspondingly form a front metal interconnect structure; the first dielectric layer and the second dielectric layer are included in the front dielectric layer.

[0063] In some embodiments, on top of the second dielectric layer, a first metal interconnect layer of the front stacked transistors can be formed by using standard back-end processes in semiconductor manufacturing (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.).

[0064] In some embodiments, forming the first metal interconnect layer of the front stacked transistors may include: depositing a dielectric material on top of the second dielectric layer to form a third dielectric layer; etching the third dielectric layer to form a second via hole, and depositing a metal material in the second via hole to form a first metal via structure 34; depositing a dielectric material on top of the third dielectric layer to form a fourth dielectric layer, and forming a first metal line structure in the fourth dielectric layer.

[0065] It can be understood that the manufacturing process for forming the first metal interconnect layer can also be a dual damascene process. The dual damascene process may include: first preparing and forming the first metal via structure 34, and then preparing and forming the first metal line structure.

[0066] In some embodiments, the dielectric layer where the first metal line structure is located can be the front metal layer M0. The first metal via structure 34 can connect the interconnect structures of the transistor and the front metal layer M0. Here, the first metal via structure 34 is used to connect the second metal interconnect structure and the first metal line structure, and the first metal line structure is used to connect to an external circuit.

[0067] In some embodiments, when the front stacked transistors include a first transistor and a second transistor, the multiple front metal interconnect structures include: a first front metal interconnect structure and a second front metal interconnect structure. Among them, the first front metal interconnect structure connects the first source / drain metal and the first metal interconnect layer, and the second front metal interconnect structure connects the second source / drain metal and the first metal interconnect layer.

[0068] It can be understood that both the first front metal interconnect structure and the second front metal interconnect structure are composed of the first metal interconnect structure and the second metal interconnect structure.

[0069] It can be understood that the source-drain structure in the first transistor (i.e., the first source-drain structure) is connected to the metal layer M0 through the first front-side metal interconnect structure, and the source-drain structure in the second transistor (i.e., the second source-drain structure) is connected to the metal layer M0 through the second front-side metal interconnect structure, so that all the transistors in the front-side stacked transistors are connected to the metal layer M0.

[0070] It should be noted that, for ease of description, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, and the "source-drain" therein is an abbreviation for "source and / or drain".

[0071] In some embodiments, step S204 may include: bonding the front-side stacked transistors to a carrier wafer, and then flipping the bonded front-side stacked transistors.

[0072] It can be understood that an insulating material (such as silicon oxide) is deposited on the front-side stacked transistors to form an insulating layer, and the insulating layer is bonded to the carrier wafer. Then, the wafer is flipped so that the front-side stacked transistors are located at the bottom and the second active structure is located at the top after flipping, which is convenient for subsequent preparation of the back-side stacked transistors. It can be understood that the bonded carrier wafer can provide physical support for the flipped front-side stacked transistors after flipping, effectively preventing the front-side stacked transistors from being broken by external forces during the preparation of the back-side stacked transistors.

[0073] In some embodiments, step S205 may include: based on the standard process of semiconductor manufacturing, at least two back-side transistors stacked along the first direction are sequentially formed. It can be understood that the back-side stacked transistors can be formed by multiple back-side transistors stacked along the first direction. The multiple back-side transistors can be self-aligned in the first direction. The preparation methods of the multiple back-side transistors can refer to the related technologies, and the embodiments of the present application do not limit this.

[0074] In one embodiment, each back-side transistor includes a source-drain structure and a gate structure. The preparation method of each back-side transistor can be a sequential scheme or a single-chip scheme. In one embodiment, in the single-chip scheme, the top source-drain metal can be formed before the metal gate is formed or after the metal gate is formed. In one embodiment, the multiple back-side transistors can be a common-gate scheme or a split-gate scheme. In one embodiment, the source-drain structures of the multiple back-side transistors can have the same or different polarities.

[0075] In some embodiments, the type of the back transistor may be different from that of the front transistor; alternatively, the type of the back transistor may be the same as that of the front transistor. Exemplarily, the back transistor may be a fin field-effect transistor, and the front transistor may be a gate-all-around field-effect transistor.

[0076] In some embodiments, the back stacked transistor includes: a third transistor and a fourth transistor, and the third transistor is closer to the front stacked transistor than the fourth transistor. Step S205 may include: forming a second dummy gate structure based on the second active structure, where the second dummy gate structure is a dummy gate structure shared by the third transistor and the fourth transistor; forming a third source / drain structure based on the second active structure; forming a third source / drain metal on the third source / drain structure; forming a back isolation structure on the third source / drain metal, where the back isolation structure is used to electrically isolate the third transistor and the fourth transistor; forming a fourth source / drain structure on the back isolation structure based on the second active structure; removing the second dummy gate structure to form a third gate structure and a fourth gate structure; forming a fourth source / drain metal on the fourth source / drain structure.

[0077] It can be understood that when the back stacked transistor only includes the third transistor and the fourth transistor, the third transistor and the fourth transistor can be fabricated using a common-gate process. And, a back isolation structure may be formed between the third transistor and the fourth transistor to electrically isolate the third transistor and the fourth transistor.

[0078] In some embodiments, the polarities of the third transistor and the fourth transistor are opposite, so that the back stacked transistor can be a complementary stacked transistor.

[0079] In some embodiments, step S206 may include: depositing a dielectric material on the back stacked transistor to form a fifth dielectric layer; etching the fifth dielectric layer until the source / drain metals of multiple back transistors among at least two back transistors are exposed to form a plurality of third interconnect vias, and depositing a metal material in the plurality of third interconnect vias to form a plurality of third metal interconnect structures; depositing a dielectric material on the fifth dielectric layer to form a sixth dielectric layer, and forming a fourth metal interconnect structure in the sixth dielectric layer; forming a second metal interconnect layer on the sixth dielectric layer.

[0080] It can be understood that after forming the backside stacked transistors, a second metal interconnect layer can be formed on the backside stacked transistors. Before forming the second metal interconnect layer, a backside dielectric layer between the backside stacked transistors and the second metal interconnect layer, and a plurality of backside metal interconnect structures formed based on the backside dielectric layer can also be formed. Each metal interconnect structure in the plurality of backside metal interconnect structures is used to connect the second metal interconnect layer and the source / drain structure in one backside transistor. The plurality of backside metal interconnect structures can meet the connection requirements of the source / drain structures of all backside transistors with the second metal interconnect layer.

[0081] It can be understood that the manufacturing process for forming the backside metal interconnect structures can be a dual damascene process. The dual damascene process can include: first manufacturing and forming a third metal interconnect structure, and then manufacturing and forming a fourth metal interconnect structure. Among them, the fourth metal interconnect structure has a preset width in the second direction, so that the first end of the fourth metal interconnect structure is connected to the third metal interconnect structure, and the second end of the fourth metal interconnect structure is connected to the second metal interconnect layer.

[0082] It can be understood that by forming a fifth dielectric layer, and then etching the fifth dielectric layer and the dielectric layer wrapping the source / drain structure based on the positions of the source / drain structures of the backside transistors, a third via interconnect can be formed, and then depositing a metal material in the third via interconnect, a third metal interconnect structure can be formed. Among them, one fourth via interconnect connects the source / drain metal of one backside transistor, and one third via interconnect correspondingly forms one third metal interconnect structure.

[0083] It can be understood that by forming a sixth dielectric layer on the fifth dielectric layer, and then etching the sixth dielectric layer based on the positions of the third metal interconnect structure and the second metal interconnect layer, a backside metal groove can be formed. Here, the length of the backside metal groove in the second direction is related to the positions of the third metal interconnect structure and the second metal interconnect layer in the second direction. By depositing a metal material in the backside metal groove, a fourth metal interconnect structure can be formed. Among them, one third metal interconnect structure and one fourth metal interconnect structure can correspondingly form one backside metal interconnect structure; the fifth dielectric layer and the sixth dielectric layer are included in the backside dielectric layer.

[0084] In some embodiments, on the sixth dielectric layer, a second metal interconnect layer of the backside stacked transistors can be formed by using standard back-end processes in semiconductor manufacturing (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.).

[0085] In some embodiments, the second metal interconnect layer for forming the backside stacked transistor may include: depositing a dielectric material over the sixth dielectric layer to form a seventh dielectric layer; etching the seventh dielectric layer to form a fourth interconnect via hole, and depositing a metal material in the fourth interconnect via hole to form a second metal via structure; depositing a dielectric material over the seventh dielectric layer to form an eighth dielectric layer, and forming a second metal wire structure in the eighth dielectric layer.

[0086] It can be understood that the manufacturing process for forming the second metal interconnect layer may also be a dual damascene process. The dual damascene process may include: first manufacturing and forming the second metal via structure, and then manufacturing and forming the second metal wire structure.

[0087] In some embodiments, the dielectric layer where the first metal wire structure is located may be the backside metal layer M0. The second metal via structure may connect the transistor and the interconnect structure of the backside metal layer M0. Here, the second metal via structure is used to connect the fourth metal interconnect structure and the second metal wire structure, and the second metal wire structure is used to connect to an external circuit.

[0088] In some embodiments, when the backside stacked transistor includes a third transistor and a fourth transistor, the multiple backside metal interconnect structures include: a first backside metal interconnect structure and a second backside metal interconnect structure. Among them, the first backside metal interconnect structure connects the third source / drain metal and the second metal interconnect layer, and the second backside metal interconnect structure connects the fourth source / drain metal and the second metal interconnect layer.

[0089] It can be understood that both the first backside metal interconnect structure and the second backside metal interconnect structure are composed of the first metal interconnect structure and the second metal interconnect structure.

[0090] It can be understood that the source / drain structure in the third transistor (i.e., the third source / drain structure) is connected to the metal layer M0 through the first backside metal interconnect structure, and the source / drain structure in the fourth transistor (i.e., the fourth source / drain structure) is connected to the metal layer M0 through the second backside metal interconnect structure, so that all the transistors in the backside stacked transistor are connected to the metal layer M0.

[0091] It should be noted that Figure 2 the steps shown in [[ ]] are not exclusive, and other steps may also be executed before, after, or between any of the shown operations; Figure 2 the steps shown in [[ ]] can be adjusted in order according to actual requirements.

[0092] It can be understood that by etching to form an active structure on a semiconductor substrate at one time, the active regions of the upper and lower transistors in the stacked transistors can be self-aligned. Subsequently, based on the first active structure and the second active structure in the active structure, a front stacked transistor and a back stacked transistor can be respectively fabricated. Among them, a plurality of front metal interconnect structures are formed above the front stacked transistor, and the plurality of front metal interconnect structures are used to connect the source / drain metals of different front transistors in the front stacked transistor to the first metal interconnect layer; alternatively, a plurality of back metal interconnect structures are formed above the back stacked transistor, and the plurality of back metal interconnect structures are used to connect the source / drain metals of different back transistors in the back stacked transistor to the second metal interconnect layer. In this way, the source / drain metal of any transistor can be connected to the metal interconnect layer formed in the subsequent process, so as to meet the connection requirements of all transistors and the metal interconnect layer, and further optimize and improve the interconnect performance of the stacked transistors.

[0093] Next, a specific example will be used to illustrate the interconnect method of the stacked transistors in the embodiments of the present application. Figures 3 to 36 FIG. is a schematic diagram of a manufacturing process of a stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 36 (a) in FIG. shows a cross-sectional view along the Figure 1 dashed line A-A' direction in FIG., Figures 3 to 36 (b) in FIG. shows a cross-sectional view along the Figure 1 dashed line B-B' direction in FIG., Figures 3 to 36 (c) in FIG. shows a cross-sectional view along the Figure 1 dashed line C-C' direction in FIG. Next, the interconnect method of the stacked transistors provided in the embodiments of the present application will be exemplarily described with reference to Figures 1 to 36 FIG.

[0094] The first step is to refer to Figure 3 FIG., and epitaxially grow silicon germanium material and silicon material on a semiconductor substrate 20 (formed of silicon material) to form a stacked structure 23 on the semiconductor substrate 20.

[0095] Here, the stacked structure 23 may include a sacrificial layer (such as the first sacrificial layer 211) and a support layer (such as the first part 212) that are alternately stacked in sequence. The sacrificial layer is formed of the above-mentioned silicon germanium material, and the support layer is formed of the above-mentioned silicon material. In one embodiment, the materials used for the sacrificial layer and the support layer can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0096] The second step is to refer to Figure 4 FIG., and use a single etching process to etch the stacked structure 23 to form an active structure on the semiconductor substrate 20.

[0097] It can be understood that the active structure includes a first active structure 21 and a second active structure 22. The first active structure 21 is farther from the semiconductor substrate 20 than the second active structure 22. Here, the first active structure 21 is used to form the active regions of the first transistor 11 and the second transistor 12 in the front stacked transistor 101 in subsequent steps; the second active structure 22 is used to form the active regions of the third transistor 13 and the fourth transistor 14 in the back stacked transistor 102 in subsequent steps.

[0098] It can be understood that an isolation layer 24 formed of a silicon material is formed between the first active structure 21 and the second active structure 22. In some embodiments, an insulating material or a dielectric material can also be used to form the isolation layer 24. For example, the isolation layer 24 can be a buried oxide layer, a dielectric layer, etc.

[0099] In some embodiments, the isolation layer 24 is used to electrically isolate the first active structure 21 and the second active structure 22, to avoid current interference between the circuits of the front stacked transistor 101 and the back stacked transistor 102. In one embodiment, ions can be implanted into the isolation layer 24 formed by preparing a silicon material, so that the isolation layer 24 can electrically isolate the front stacked transistor 101 and the back stacked transistor 102.

[0100] It can be understood that when lithographically forming the first active structure 21 and the second active structure 22, a relatively large etching depth can be used. For example, the sum of the heights of the first active structure 21 and the second active structure 22 obtained by etching can be such that at least four transistors can be formed in the first direction. Of course, the height of the active structure can also be set according to the actual situation, and the embodiments of the present application do not limit this.

[0101] It should be noted that the steps of the lithography process can include: depositing a photoresist material, exposing and developing the photoresist material, removing a part of the photoresist material, etching to remove the material layer corresponding to the part of the photoresist material, etc.

[0102] The third step, referring to Figure 5 As shown, an insulating material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 25 covering the active structure, and the shallow trench isolation structure 25 is subjected to chemical-mechanical planarization (CMP) treatment to ensure that the shallow trench isolation structure 25 has the same height in any region. Subsequently, an etching process is used to etch the shallow trench isolation structure 25 until the first active structure 21 is exposed. Here, the etched shallow trench isolation structure 25 can cover the first active structure 21, wrap the isolation layer 24 and the second active structure 22.

[0103] It is understandable that the height of the shallow trench isolation structure 25 after chemical mechanical planarization is slightly higher than that of the active structure in the first direction.

[0104] In some embodiments, the oxide material for forming the shallow trench isolation structure 25 may be: silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2), etc.

[0105] The fourth step, referring to Figure 6 As shown, a pseudo-gate material such as polysilicon or single-crystalline silicon is deposited in the gate region to form a first pseudo-gate structure 26. Subsequently, a pseudo-gate sidewall can be formed on the sidewalls of the first pseudo-gate structure 26.

[0106] Here, a first sacrificial layer 211 is formed in the middle part of the first active structure 21. Taking the first sacrificial layer 211 as the demarcation point, the part of the first active structure 21 closer to the semiconductor substrate 20 than the first sacrificial layer 211 (i.e., the first part 212) is used to form the first transistor 11, and the part of the first active structure 21 farther from the semiconductor substrate 20 than the first sacrificial layer 211 (i.e., the second part 213) is used to form the second transistor 12.

[0107] In the embodiment of the present application, the pseudo-gate sidewall formed on the sidewalls of the first pseudo-gate structure 26 can constitute the second pseudo-gate sidewall 121 of the second transistor 12.

[0108] The fifth step, referring to Figure 7 As shown, using the first pseudo-gate structure 26 as a hard mask, the first sacrificial layer 211 and the second part 213 in the source-drain region are removed to expose the first part 212 in the source-drain region and the first sacrificial layer 211 and the second part 213 in the gate region, obtaining an initial first trench 29. Subsequently, the first sacrificial layer 211 in the gate region is etched laterally, and silicon nitride is filled at the position where the first sacrificial layer 211 is removed to form the first pseudo-gate sidewall 111 of the first transistor 11.

[0109] The sixth step, referring to Figure 8 As shown, an insulating material is deposited on the sidewalls of the initial first trench 29 using an isotropic deposition process to form an initial first barrier layer. Subsequently, the initial first barrier layer on the top of the first pseudo-gate structure 26 and the shallow trench isolation structure 25 is etched away to form a first barrier layer 30.

[0110] Here, the first barrier layer 30 can cover the second part 213 to ensure that while epitaxially growing the first source-drain structure 112, the active structure for preparing the second transistor 12 is not affected. The bottom of the initial first trench 29 can be formed by the first part 212 in the source-drain region, and the sidewalls of the initial first trench 29 can be formed by the second part 213 and the first sacrificial layer 211 in the gate region.

[0111] In one embodiment, the material forming the first blocking layer 30 may have a high etch selectivity with respect to the material forming the first portion 212.

[0112] Step 7, referring to Figure 9 As shown, using the first pseudo-gate structure 26 as a hard mask, the first portion 212 and the second sacrificial layer 214 located below the initial first trench 29 within the source / drain regions are removed to expose the isolation layer 24 within the source / drain regions and the first portion 212 and the second sacrificial layer 214 within the gate region, thereby obtaining the first trench 27. Subsequently, using an etching process, the second sacrificial layer 214 within the gate region is etched laterally, and silicon nitride is filled at the position where the second sacrificial layer 214 is removed to form the first pseudo-gate sidewall 111 of the first transistor.

[0113] It can be understood that, compared with the solution without the second sacrificial layer 214, the solution with the second sacrificial layer 214 can completely expose the first portion 212 within the gate region in the subsequent step of forming the gate structure, thereby facilitating the formation of the surrounding-gate structure.

[0114] In some embodiments, the material forming the first pseudo-gate sidewall 111 may also be an insulating material.

[0115] Step 8, referring to Figure 10 As shown, based on the first portion 212 within the gate region, a first source / drain structure 112 is epitaxially grown inside and outside the first trench 27 by an epitaxial growth process.

[0116] Here, when forming the first trench 27, it is possible to effectively prevent the second portion 213 from also epitaxially growing an active structure, thereby ensuring the orderly preparation of the front-side stacked transistor 101.

[0117] Step 9, referring to Figure 11 As shown, the first blocking layer 30 is removed to expose the second portion 213 within the gate region.

[0118] Step 10, referring to Figure 12 As shown, a dielectric material is deposited on the first source / drain structure 112 to form the first interlayer dielectric layer 113. Subsequently, the first interlayer dielectric layer 113 is etched to expose the first source / drain structure 112, and a metal material is deposited on the first source / drain structure 112 to form the first source / drain metal 115 of the first transistor 11.

[0119] Step 11, referring to Figure 13As shown, an insulating material is deposited on the first source / drain metal 115 to form a front isolation structure 28. The front isolation structure 28 is located between the first source / drain structure 112 and the second source / drain structure 122. In one embodiment, the front isolation structure 28 may be opposite to the position of the first sacrificial layer 211.

[0120] Step 12, refer to Figure 14 As shown, based on the second part 213 within the gate region, a second source / drain structure 122 is epitaxially grown inside and outside the first trench 27.

[0121] Step 13, refer to Figure 15 As shown, a dielectric material is deposited on the second source / drain structure 122 to form a second interlayer dielectric layer 123. Subsequently, the first dummy gate structure 26 is removed to expose the first part 212, the first sacrificial layer 211, the second part 213, and the second sacrificial layer 214 within the gate region. Subsequently, the first sacrificial layer 211 and the second sacrificial layer 214 are removed to completely expose the first part 212 and the second part 213 within the gate region. A first gate structure 114 of the first transistor 11 is formed based on the first part 212, and a second gate structure 124 of the second transistor 12 is formed based on the second part 213.

[0122] Here, the junction of the first gate structure 114 and the second gate structure 124 is located at the position where the first sacrificial layer 211 is removed. It can be understood that the first sacrificial layer 211 separates the first active structure 21 within the gate region into two parts for forming the first gate structure 114 and the second gate structure 124 respectively. The junction of the first gate structure 114 and the second gate structure 124 may be located at the position where the first active structure 21 is separated, that is, the position of the first sacrificial layer 211.

[0123] Step 14, refer to Figure 16 As shown, a resection process is used to remove the structures within the first isolation region, and silicon nitride is deposited within the first isolation region to form an initial cell isolation structure. The silicon nitride deposited on the top and a part of the second gate structure 124 are removed by a chemical mechanical planarization process to expose the second interlayer dielectric layer 123 within the source / drain region, and a cell isolation structure 31 is obtained.

[0124] Here, the first isolation region refers to the regions on both sides of the stacked transistors in the second direction. The cell isolation structure 31 is used to electrically isolate adjacent stacked transistor cells.

[0125] Step 15, refer to Figure 17 As shown, a resection process is used to remove the structures within the second isolation region, and silicon nitride is deposited within the second isolation region to form a cell isolation structure 31.

[0126] Here, the second isolation region refers to the regions located on both sides of the stacked transistors in the third direction. The third direction is perpendicular to the second direction and the first direction.

[0127] The sixteenth step, refer to Figure 18 As shown, deposit a dielectric material on top of the second transistor 12 to form a front dielectric structure 127. Subsequently, etch the front dielectric structure 127 and the second interlayer dielectric layer 123 in sequence to expose the second source / drain structure 122, and deposit a metal material on top of the second source / drain structure 122 to form the second source / drain metal 125 of the second transistor 12.

[0128] Here, in order to facilitate the connection between the first source / drain metal 115 and the metal layer M0, the projection of the second source / drain metal 125 in the first direction may not coincide with the projection of the first source / drain metal 115 in the first direction.

[0129] The seventeenth step, refer to Figure 19 As shown, deposit a dielectric material on top of the front dielectric structure 127 to form a first dielectric layer 51. Here, the first dielectric layer 51 serves to electrically isolate the adjacent upper and lower structures.

[0130] The eighteenth step, refer to Figure 20 As shown, according to the positions of the source / drain metals of the first transistor 11 and the second transistor 12 in the front stacked transistor 101, etch to form the first interconnect via 32. Here, by etching the first dielectric layer 51, the front dielectric structure 127, the second interlayer dielectric layer 123, and the front isolation structure 28, the first source / drain metal 115 can be exposed, and the first interconnect via 32 corresponding to the first transistor 11 can be formed. By etching the first dielectric layer 51, the second source / drain metal 125 can be exposed, and the first interconnect via 32 corresponding to the second transistor 12 can be formed.

[0131] It should be noted that the first interconnect via 32 corresponding to the first transistor 11 and the first interconnect via 32 corresponding to the second transistor 12 may not be connected.

[0132] The nineteenth step, refer to Figure 21 As shown, deposit a metal material in the first interconnect via 32 to form a first metal interconnect structure 61. Subsequently, deposit a dielectric material on top of the first dielectric layer 51 to form a second dielectric layer 52, and etch the second dielectric layer 52 based on the positions of the first metal interconnect structure 61 and the first metal interconnect layer 116 to form a front metal groove 33.

[0133] Here, the length of the front metal groove 33 in the second direction is related to the positions of the first metal interconnect structure 61 and the first metal interconnect layer 116 in the second direction.

[0134] The twentieth step, refer to Figure 22As shown, a second metal interconnect structure 62 is formed by depositing a metal material in the front metal groove 33. Herein, a first metal interconnect structure 61 and a second metal interconnect structure 62 can correspondingly form a front metal interconnect structure. The front metal interconnect structure may include: a first front metal interconnect structure and a second front metal interconnect structure. Among them, the first front metal interconnect structure can connect the first source / drain metal 115 and the first metal interconnect layer 116, and the second front metal interconnect structure can connect the second source / drain metal 125 and the first metal interconnect layer 116.

[0135] The twenty-first step, refer to Figure 23 As shown, a dielectric material is deposited on the second dielectric layer 52 to form a third dielectric layer 53; the third dielectric layer 53 is etched to form a second through-hole, and a metal material is deposited in the second through-hole to form a first metal via structure 34.

[0136] The twenty-second step, refer to Figure 24 As shown, a dielectric material is deposited on the third dielectric layer 53 to form a fourth dielectric layer 54, and a first metal wire structure 35 (i.e., metal layer M0) is formed in the fourth dielectric layer 54. And a metal layer M1 is formed on the first metal wire structure 35 by using the same preparation process. Thus, the preparation of the front stacked transistor 101 and the first metal interconnect layer 116 is completed.

[0137] The twenty-third step, refer to Figure 25 As shown, the front stacked transistor 101 is bonded to the carrier wafer 43, and the bonded front stacked transistor 101 is flipped.

[0138] The twenty-fourth step, refer to Figure 26 As shown, an etching process is used to remove the semiconductor substrate 20 until the shallow trench isolation structure 25 is exposed.

[0139] The twenty-fifth step, refer to Figure 27 As shown, a chemical mechanical planarization process is used to expose the second active structure 22.

[0140] Here, a third sacrificial layer 221 is formed in the middle part of the second active structure 22. Taking the third sacrificial layer 221 as the boundary, the part of the second active structure 22 closer to the front stacked transistor 101 than the third sacrificial layer 221 (i.e., the third part 222) is used to form the third transistor 13, and the part of the second active structure 22 farther from the front stacked transistor 101 than the third sacrificial layer 221 (i.e., the fourth part 223) is used to form the fourth transistor 14. The second active structure 22 further includes a fourth sacrificial layer 224.

[0141] Here, exposing the second active structure 22 can expose the fourth transistor 14 in the second active structure 22.

[0142] Step 26, refer to Figure 28 As shown, use an etching process to thin the shallow trench isolation structure 25 so that the second active structure 22 is exposed outside the thinned shallow trench isolation structure 25. The thinned shallow trench isolation structure 25 can wrap the isolation layer 24. The thinned shallow trench isolation structure 25 has a certain thickness in the first direction and can be used for electrically isolating the first transistor 11 and the third transistor 13.

[0143] Step 27, refer to Figure 29 As shown, use the same processes as in Steps 4 to 10 to sequentially form a second dummy gate structure 36, a dummy gate sidewall covering the sidewalls of the second dummy gate structure 36, a third dummy gate sidewall 131 of the third transistor 13, a third source / drain structure 132 of the third transistor 13, a third interlayer dielectric layer 133 of the third transistor 13, and a third source / drain metal 135 of the third transistor 13.

[0144] In the embodiment of the present application, the dummy gate sidewall formed on the sidewalls of the second dummy gate structure 36 can form a fourth dummy gate sidewall 141 of the fourth transistor 14.

[0145] Step 28, refer to Figure 30 As shown, use the same processes as in Steps 11 to 15 to sequentially form a backside isolation structure 37, a fourth source / drain structure 142 of the fourth transistor 14, a fourth interlayer dielectric layer 143 of the fourth transistor 14, a third gate structure 134 of the third transistor 13, a fourth gate structure 144 of the fourth transistor 14, and a cell isolation structure 31.

[0146] Step 29, refer to Figure 31 As shown, deposit a dielectric material on the fourth transistor 14 to form a backside dielectric structure 147, etch the backside dielectric structure 147 and the fourth interlayer dielectric layer 143 in sequence to expose the fourth source / drain structure 142, and deposit a metal material on the fourth source / drain structure 142 to form a fourth source / drain metal 145 of the fourth transistor 14. Deposit a dielectric material on the backside dielectric structure 147 to form a fifth dielectric layer 55. Here, the fifth dielectric layer 55 serves to electrically isolate the adjacent upper and lower structures.

[0147] Step 30, refer to Figure 32 As shown, according to the positions of the source / drain metals of the third transistor 13 and the fourth transistor 14 in the backside stacked transistor 102, etch to form a third interconnection via 38. Here, by etching the fifth dielectric layer 55, the backside dielectric structure 147, the fourth interlayer dielectric layer 143, and the backside isolation structure 37, the third source / drain metal 135 can be exposed, and the third interconnection via 38 corresponding to the third transistor 13 can be formed.

[0148] The thirty - first step, refer to Figure 33 As shown, deposit a metal material in the third mutually - connected via 38 to form a third metal interconnection structure 63. Subsequently, deposit a dielectric material on the fifth dielectric layer 55 to form a sixth dielectric layer 56, and etch the sixth dielectric layer 56 based on the positions of the third metal interconnection structure 63 and the second metal interconnection layer 126 to form a back - side metal groove 39.

[0149] The thirty - second step, refer to Figure 34 As shown, form a fourth metal interconnection structure 64 by depositing a metal material in the back - side metal groove 39. Among them, one third metal interconnection structure 63 and one fourth metal interconnection structure 64 can correspondingly form a back - side metal interconnection structure.

[0150] It should be noted that the back - side metal interconnection structure in the figure only includes: the first back - side metal interconnection structure, and the first back - side metal interconnection structure can connect the third source - drain metal 135 and the second metal interconnection layer 126.

[0151] In some embodiments, the back - side metal interconnection structure may further include: the second back - side metal interconnection structure, and the second back - side metal interconnection structure can connect the fourth source - drain metal 145 and the second metal interconnection layer 126.

[0152] The thirty - third step, refer to Figure 35 As shown, deposit a dielectric material on the sixth dielectric layer 56 to form a seventh dielectric layer 57; etch the seventh dielectric layer 57 to form a fourth mutually - connected via, and deposit a metal material in the fourth mutually - connected via to form a second metal via structure 40.

[0153] Here, by etching the seventh dielectric layer 57, the sixth dielectric layer 56, and the fifth dielectric layer 55, the fourth source - drain metal 145 can be exposed, thereby forming a fourth mutually - connected via corresponding to the fourth transistor 14. Based on this fourth mutually - connected via, a second metal via structure 40 that connects the fourth source - drain metal 145 and the second metal wire structure 41 (i.e., metal layer M0) can be formed.

[0154] The thirty - fourth step, refer to Figure 36 As shown, deposit a dielectric material on the seventh dielectric layer 57 to form an eighth dielectric layer 58, and form a second metal wire structure 41 in the eighth dielectric layer 58. And form a metal layer M1 on the second metal wire structure 41 using the same preparation process. Thus, the preparation of the back - side stacked transistor 102 and the second metal interconnection layer 126 is completed.

[0155] In the embodiments of the present application, after the silicon substrate and the superlattice stack are formed, the active structures of the front and back transistors are formed simultaneously, and the front stacked transistors are formed according to the standard process flow. Bonding, flipping the wafer, exposing the active structure of the back transistor, and then forming the back stacked transistors according to the standard process flow. Among them, the connection between the transistor and the metal interconnect layer is through the metal interconnect structure in the VHV form. The key advantage of the metal interconnect structure in the VHV form is that the source and drain electrodes of each layer of transistors are connected to the horizontal metal in the metal interconnect structure in the VHV form through the vertical metal in the metal interconnect structure in the VHV form. The horizontal metal in the metal interconnect structure in the VHV form extends in the second direction until the horizontal metal is located below the metal layer M0, so as to be connected to the metal layer M0 through the horizontal metal, realizing the connection between the source and drain electrodes of each layer of transistors and the metal layer M0.

[0156] Through this design, the problem that the source and drain electrodes of the transistor cannot be connected to the metal layer M0 through the vertical vias or can only be connected to the metal layer M0 at a fixed position can be solved. The metal interconnect structure in the VHV form is cited in the stacked transistors, which not only improves the interconnect flexibility of the transistors, but also provides a solid foundation for realizing complex logic designs and large-scale integrations based on flip-chip complementary stacked transistors. This innovative interconnect scheme opens up new possibilities for the development of future high-performance integrated circuits, ensuring that while continuously pursuing smaller sizes and higher integration levels, the performance and reliability of the circuit can be maintained.

[0157] In a second aspect, in the embodiments of the present disclosure, a stacked transistor 10 is provided. The stacked transistor 10 can be fabricated by using the method in Figures 3 to 36 one or more corresponding embodiments. Referring to Figure 36 as shown, the stacked transistor 10 includes: a front stacked transistor and a first metal interconnect layer 116 located above the front stacked transistor; the front stacked transistor includes: at least two front transistors stacked along a first direction; the first metal interconnect layer 116 is used to connect the front stacked transistor to an external circuit;

[0158] a back stacked transistor and a second metal interconnect layer 126 located above the back stacked transistor; the back stacked transistor includes: at least two back transistors stacked along the first direction; the second metal interconnect layer 126 is used to connect the back stacked transistor to an external circuit; the front stacked transistor and the back stacked transistor are stacked along the first direction, and the first active structure in the front stacked transistor and the second active structure in the back stacked transistor form an active structure;

[0159] Among them, a front dielectric layer is formed between the front stacked transistors and the first metal interconnect layer 116, and a plurality of front metal interconnect structures are formed based on the front dielectric layer; the front metal interconnect structures are used to connect the source / drain metals of the front transistors to the first metal interconnect layer 116, and one front metal interconnect structure corresponds to one front transistor; and / or, a back dielectric layer is formed between the back stacked transistors and the second metal interconnect layer 126, and a plurality of back metal interconnect structures are formed based on the back dielectric layer; the back metal interconnect structures are used to connect the source / drain metals of the back transistors to the second metal interconnect layer 126, and one back metal interconnect structure corresponds to one back transistor.

[0160] It can be understood that the stacked transistors in the embodiments of the present application can be prepared by using Figures 3 to 26 the preparation methods in one or more corresponding embodiments. In the embodiments of the present application, front stacked transistors are formed on the front side of the wafer. The front stacked transistors include two stacked transistors. Back stacked transistors are formed on the back side of the wafer. The back stacked transistors include two stacked transistors, so that the integration performance of the stacked transistors is further enhanced.

[0161] It can be understood that any layer of front transistors in the front stacked transistors can be connected to the first metal interconnect layer 116 through the front metal interconnect structures, and any layer of back transistors in the back stacked transistors can be connected to the first metal interconnect layer 116 through the back metal interconnect structures, so as to meet the connection requirements of all transistors in the stacked transistors with the metal interconnect layer, and further optimize and improve the interconnect performance of the stacked transistors.

[0162] In some embodiments, the front metal interconnect structure includes a first metal interconnect structure 61 and a second metal interconnect structure 62. There is a VHV morphology between the first metal interconnect structure 61 and the second metal interconnect structure 62. Among them, the first metal interconnect structure 61 connects any layer of source / drain metal and the second metal interconnect structure 62, and the second metal interconnect structure 62 adjusts the length in the second direction to connect the first metal interconnect structure 61 and the first metal interconnect layer 116, so as to meet the connection requirement of the source / drain metal and the metal M0 layer. Similarly, the back metal interconnect structure includes a third metal interconnect structure 63 and a fourth metal interconnect structure 64. There is a VHV morphology between the third metal interconnect structure 63 and the fourth metal interconnect structure 64. The connection requirement of the source / drain metal and the metal M0 layer is realized through the length of the fourth metal interconnect structure 64 in the second direction.

[0163] In some embodiments, the type of the first transistor 11 or the second transistor 12 is any one of the following: planar transistor, fin field effect transistor, fully surrounded gate transistor.

[0164] In some embodiments, Figure 37Schematic diagram of a stacked transistor structure shown according to an embodiment of the present application. Figure 37 (a) in Figure 1 shows a cross-sectional view along the dashed line A-A' direction in Figure 37 (b) in Figure 1 shows a cross-sectional view along the dashed line B-B' direction in Figure 37 (c) in Figure 1 shows a cross-sectional view along the dashed line C-C' direction in Figure 37 As shown in

[0165] It should be noted that the solution of realizing the upper and lower transistors by flipping the wafer in the embodiments of the present application is an organic integration of the current sequential and monolithic stacked transistor solutions, taking into account issues such as the consistency of the active regions of the upper and lower layer transistors, defect density, alignment, and thermal budget. This solution solves the long-term problems existing in the existing mainstream technical solutions of stacked transistors, such as complex processes \ fixed polarity (monolithic solution) and difficult alignment \ high defect density of the upper layer semiconductor material (sequential solution), thereby promoting the industrialization of transistor stacking technology.

[0166] Moreover, the mature technology reuse degree of the flip-chip stacked transistor solution of the present scheme is high, which can avoid a large amount of high-cost process development to save costs and has high feasibility. At the same time, the flip-chip transistor adopts a self-aligned "back-to-back" active region design, and the front and back transistors have independent signal and power supply networks, which are connected through local interconnections, greatly releasing the metal wiring resources (more than 60% improvement compared to the current solution), and there is a huge space in the direction of process design co-optimization.

[0167] Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) without special process development for specific device architectures, with strong flexibility and strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and broad development prospects. In the embodiments of the present application, the flip-chip transistor solution can also be the flip-chip stacking of complementary stacked transistors of types such as planar transistors, FinFETs, GAA Nanosheets, and vertical transistors, thereby further increasing the integration density of transistors and improving the integration performance of transistors.

[0168] An embodiment of the present application provides a semiconductor device, including: a stacked transistor as in the above embodiment. The specific definition of the stacked transistor can at least refer to the stacked transistor shown above Figure 36 and will not be elaborated here.

[0169] An embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned stacked transistor. The specific definition of the stacked transistor can at least refer to the structure shown above Figure 36 and will not be elaborated here.

[0170] In the description of the present application, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expression of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any number of embodiments or examples. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0171] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for interconnecting stacked transistors, characterized in that The method includes: Forming an active structure on a semiconductor substrate, wherein the active structure includes a first active structure and a second active structure stacked in a first direction, and the first active structure is farther from the semiconductor substrate than the second active structure; Forming a front stacked transistor based on the first active structure, wherein the front stacked transistor includes at least two front transistors stacked in a first direction; Forming a first metal interconnect layer on the front stacked transistor, and the first metal interconnect layer is used to connect the front stacked transistor to an external circuit; Flipping the wafer and removing the semiconductor substrate; Forming a back stacked transistor based on the second active structure, wherein the back stacked transistor includes at least two back transistors stacked in a first direction; Forming a second metal interconnect layer on the back stacked transistor, and the second metal interconnect layer is used to connect the back stacked transistor to an external circuit; Wherein, a front dielectric layer is formed between the front stacked transistor and the first metal interconnect layer, and a plurality of front metal interconnect structures are formed based on the front dielectric layer; the front metal interconnect structures are used to connect the source-drain metals of the front transistors to the first metal interconnect layer, and one front metal interconnect structure corresponds to one front transistor; and / or, a back dielectric layer is formed between the back stacked transistor and the second metal interconnect layer, and a plurality of back metal interconnect structures are formed based on the back dielectric layer; the back metal interconnect structures are used to connect the source-drain metals of the back transistors to the second metal interconnect layer, and one back metal interconnect structure corresponds to one back transistor.

2. The method according to claim 1, characterized in that, The forming a first metal interconnect layer on the front stacked transistor includes: Depositing a dielectric material on the front stacked transistor to form a first dielectric layer; Etching the first dielectric layer until the source-drain metals of a plurality of the front transistors among the at least two front transistors are exposed, to form a plurality of first interconnect vias, and depositing a metal material in the plurality of first interconnect vias to form a plurality of first metal interconnect structures; wherein one first interconnect via connects the source-drain metal of one front transistor, and one first interconnect via correspondingly forms one first metal interconnect structure; Depositing a dielectric material on the first dielectric layer to form a second dielectric layer, and forming a second metal interconnect structure in the second dielectric layer, wherein the second metal interconnect structure has a preset width in a second direction, so that a first end of the second metal interconnect structure connects the first interconnect via, and a second end of the second metal interconnect structure connects the first metal interconnect layer; the first dielectric layer and the second dielectric layer are included in the front dielectric layer, and one first metal interconnect structure and one second metal interconnect structure correspondingly form one front metal interconnect structure; Forming the first metal interconnect layer on the second dielectric layer.

3. The method according to claim 2, wherein The forming the first metal interconnect layer on the second dielectric layer includes: Deposit a dielectric material over the second dielectric layer to form a third dielectric layer; Etch the third dielectric layer to form second through-holes, and deposit a metal material in the second through-holes to form a first metal via structure; Deposit a dielectric material over the third dielectric layer to form a fourth dielectric layer, and form a first metal line structure in the fourth dielectric layer, wherein the first metal via structure is used to connect the second metal interconnect structure and the first metal line structure, and the first metal line structure is used to connect to an external circuit.

4. The method according to any one of claims 1 to 3, characterized in that, The front stacked transistors include: a first transistor and a second transistor, and the first transistor is closer to the back stacked transistor than the second transistor; Forming front stacked transistors based on the first active structure includes: Based on the first active structure, form a first dummy gate structure, wherein the first dummy gate structure is a dummy gate structure shared by the first transistor and the second transistor; Based on the first active structure, form a first source / drain structure; Form a first source / drain metal over the first source / drain structure; Form a front isolation structure over the first source / drain metal, and the front isolation structure is used to electrically isolate the first transistor and the second transistor; Based on the first active structure, form a second source / drain structure over the front isolation structure; Remove the first dummy gate structure to form a first gate structure and a second gate structure; Form a second source / drain metal over the second source / drain structure.

5. The method according to claim 4, wherein The plurality of front metal interconnect structures include: a first front metal interconnect structure and a second front metal interconnect structure; the first front metal interconnect structure connects the first source / drain metal and the first metal interconnect layer, and the second front metal interconnect structure connects the second source / drain metal and the first metal interconnect layer.

6. The method according to claim 1, wherein Forming a second metal interconnect layer over the back stacked transistor includes: Deposit a dielectric material over the back stacked transistor to form a fifth dielectric layer; Etch the fifth dielectric layer until the source / drain metals of a plurality of the back transistors among the at least two back transistors are exposed to form a plurality of third through-holes, and deposit a metal material in the plurality of third through-holes to form a plurality of third metal interconnect structures; wherein one of the third through-holes connects the source / drain metal of one of the back transistors, and one of the third through-holes correspondingly forms one of the third metal interconnect structures; Deposit a dielectric material over the fifth dielectric layer to form a sixth dielectric layer, and form a fourth metal interconnect structure in the sixth dielectric layer, wherein the fourth metal interconnect structure has a preset width in a second direction such that a first end of the fourth metal interconnect structure connects to the third through-hole, and a second end of the fourth metal interconnect structure connects to the second metal interconnect layer; the fifth dielectric layer and the sixth dielectric layer are included in the back dielectric layer, and one of the third metal interconnect structures and one of the fourth metal interconnect structures correspondingly form one of the back metal interconnect structures; Form the second metal interconnect layer over the sixth dielectric layer.

7. The method according to claim 6, characterized in that, Above the sixth dielectric layer, forming the second metal interconnect layer, includes: Depositing a dielectric material above the sixth dielectric layer to form a seventh dielectric layer; Etching the seventh dielectric layer to form a fourth via hole, and depositing a metal material in the fourth via hole to form a second metal via structure; Depositing a dielectric material above the seventh dielectric layer to form an eighth dielectric layer, and forming a second metal line structure in the eighth dielectric layer, wherein the second metal via structure is used to connect the fourth metal interconnect structure and the second metal line structure, and the second metal line structure is used to connect to an external circuit.

8. The method according to any one of claims 1, 6, and 7, characterized in that, The back stacked transistors include: a third transistor and a fourth transistor, and the third transistor is closer to the front stacked transistor than the fourth transistor; Forming the back stacked transistors based on the second active structure, includes: Based on the second active structure, forming a second dummy gate structure, wherein the second dummy gate structure is a shared dummy gate structure for the third transistor and the fourth transistor; Based on the second active structure, forming a third source / drain structure; Forming a third source / drain metal above the third source / drain structure; Forming a back isolation structure above the third source / drain metal, and the back isolation structure is used to electrically isolate the third transistor and the fourth transistor; Above the back isolation structure, based on the second active structure, forming a fourth source / drain structure; Removing the second dummy gate structure to form a third gate structure and a fourth gate structure; Forming a fourth source / drain metal above the fourth source / drain structure.

9. The method according to claim 8, wherein The multiple back metal interconnect structures include: a first back metal interconnect structure and a second back metal interconnect structure; the first back metal interconnect structure connects the third source / drain metal and the second metal interconnect layer, and the second back metal interconnect structure connects the fourth source / drain metal and the second metal interconnect layer.

10. A stacked transistor prepared by using the method according to any one of claims 1 to 9, characterized in that, Includes: A front stacked transistor and a first metal interconnect layer located above the front stacked transistor; The front stacked transistor includes: at least two front transistors stacked along a first direction; the first metal interconnect layer is used to connect the front stacked transistor to an external circuit; A back stacked transistor and a second metal interconnect layer located above the back stacked transistor; the back stacked transistor includes: at least two back transistors stacked along a first direction; the second metal interconnect layer is used to connect the back stacked transistor to an external circuit; the front stacked transistor and the back stacked transistor are stacked along the first direction, and a first active structure in the front stacked transistor and a second active structure in the back stacked transistor form an active structure; Wherein, a front dielectric layer is formed between the front stacked transistors and the first metal interconnect layer, and a plurality of front metal interconnect structures are formed based on the front dielectric layer; the front metal interconnect structures are used to connect the source-drain metals of the front transistors to the first metal interconnect layer, and one front metal interconnect structure corresponds to one front transistor; and / or, a back dielectric layer is formed between the back stacked transistors and the second metal interconnect layer, and a plurality of back metal interconnect structures are formed based on the back dielectric layer; the back metal interconnect structures are used to connect the source-drain metals of the back transistors to the second metal interconnect layer, and one back metal interconnect structure corresponds to one back transistor.

11. The stacked transistor according to claim 10, wherein The front stacked transistors include: a first metal interconnect structure and a second metal interconnect structure; one end of the first metal interconnect structure is connected to the source-drain structure in the front transistor, one end of the first metal interconnect structure is connected to one end of the second metal interconnect structure, and the other end of the second metal interconnect structure is connected to the first metal interconnect layer; The back stacked transistors include: a third metal interconnect structure and a fourth metal interconnect structure; one end of the third metal interconnect structure is connected to the source-drain structure in the back transistor, one end of the third metal interconnect structure is connected to one end of the fourth metal interconnect structure, and the other end of the fourth metal interconnect structure is connected to the second metal interconnect layer.

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