Three-dimensional memory device including split support pillar structure and method of manufacturing same

Abstract

A memory device includes a pair of alternating stacks of insulating layers and conductive layers; a memory opening extending vertically through a respective one of the pair of alternating stacks; a memory opening filling structure in the memory opening; a lateral isolation trench filling structure located in the lateral isolation trench between the pair of alternating stacks; and a support pillar structure extending vertically through a respective one of the pair of alternating stacks. The support pillar structures include first type support pillar structures each having a respective circular or elliptical horizontal cross-sectional shape and auxiliary support pillar structures each having a horizontal cross-sectional shape of a circular or elliptical sector and having a planar vertically extending surface.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority of U.S. Non - Provisional Application No. 18 / 477,907, filed on September 29, 2023, U.S. Continuation - in - Part Application No. 18 / 508,638, filed on November 14, 2023, and U.S. Continuation - in - Part Application No. 18 / 421,417, filed on January 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including a split support pillar structure and methods of manufacturing the same. Background Art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., titled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor(S - SGT)Structured Cell", Proceedings of the IEDM (2001), pages 33 - 36. Summary of the Invention

[0005] According to one aspect of the present disclosure, a memory device includes: a pair of alternating stacks of insulating and conductive layers, wherein the pair of alternating stacks are laterally spaced apart from each other by lateral isolation trenches extending laterally along a first horizontal direction; memory openings extending vertically through a respective one of the pair of alternating stacks; memory opening fill structures located in the memory openings, wherein each memory opening fill structure in the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel; lateral isolation trench fill structures located in the lateral isolation trenches; and support pillar structures extending vertically through a respective one of the pair of alternating stacks, wherein the support pillar structures include a first type of support pillar structure and a second type of support pillar structure, the first type of support pillar structure each having a respective circular or oval horizontal cross - sectional shape, and the second type of support pillar structure each having a horizontal cross - sectional shape of a sector of a circle or an oval and having a planar vertically extending surface.

[0006] According to another aspect of the present disclosure, a method of forming a device structure includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a stepped surface by patterning the alternating stack; forming an inverse-stepped dielectric material portion over the stepped surface; forming a support opening fill structure through the inverse-stepped dielectric material portion and a underlying portion of the alternating stack; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a respective vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench through the inverse-stepped dielectric material portion, through the alternating stack, and through a first row of a first support pillar structure of the support pillar structure to cut each first support pillar structure in the first support pillar structure into a respective pair of auxiliary support pillar structures, each auxiliary support pillar structure in the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertical extension surface in opposite sidewalls of the lateral isolation trench; and replacing the sacrificial material layer with a conductive layer.

[0007] In an alternative embodiment, the lateral isolation trench is formed through the inverse-stepped dielectric material portion, through the alternating stack, and through a first row and a second row of a first support pillar structure and a second support pillar structure of the support pillar structure to cut each of the first support pillar structure and the second support pillar structure into a respective pair of auxiliary support pillar structures, each auxiliary support pillar structure in the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertical extension surface in opposite sidewalls of the lateral isolation trench.

[0008] According to one aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device including: a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks includes an insulating layer and a conductive layer that are interleaved along a vertical direction, and wherein the pair of alternating stacks are laterally spaced apart from each other by a lateral isolation trench that extends laterally along a first horizontal direction; a memory opening that extends vertically through a corresponding one of the pair of alternating stacks; a memory opening filling structure that is located in a corresponding one of the memory openings and includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; a row of support pillar structures, wherein each row of the support pillar structures extends laterally along the first horizontal direction and vertically through a corresponding one of the pair of alternating stacks; and a lateral isolation trench filling structure that has a variable width along a second horizontal direction and is located in the lateral isolation trench, the lateral isolation trench filling structure including: a plurality of neck portions that have a pair of straight sidewalls extending along the first horizontal direction and have a first width along the second horizontal direction that is perpendicular to the first horizontal direction; and a plurality of lateral protruding portions that have a second width greater than the first width along the second horizontal direction, wherein the plurality of lateral protruding portions are interleaved with the plurality of neck portions along the first horizontal direction.

[0009] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method includes: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer over a substrate; forming a memory opening through the vertical alternating sequence; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; forming a row of support pillar structures, wherein each row of the support pillar structures is periodically arranged at a uniform pitch along a first horizontal direction and extends vertically through the vertical alternating sequence; forming a lateral isolation trench that extends generally along the first horizontal direction through the vertical alternating sequence, wherein the lateral isolation trench has a variable width along a second horizontal direction, the variable width having a periodic undulation along the first horizontal direction, the periodic undulation having the same periodicity as the uniform pitch; and replacing a remaining portion of the continuous sacrificial material layer with a conductive layer to form a pair of alternating stacks of an insulating layer and a conductive layer that are separated by the lateral isolation trench along the second horizontal direction.

[0010] According to one aspect of the present disclosure, a three-dimensional memory device includes: a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks includes insulating layers and conductive layers that are staggered along a vertical direction, and wherein the pair of alternating stacks are laterally spaced apart from each other by a lateral isolation trench that extends laterally along a first horizontal direction; a memory opening that extends vertically through a corresponding one of the pair of alternating stacks; a memory opening fill structure that is located in a corresponding one of the memory openings and includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; and a lateral isolation trench fill structure that is located in the lateral isolation trench and includes a plurality of neck portions that have a pair of straight sidewalls extending along the first horizontal direction and have a first width along a second horizontal direction that is perpendicular to the first horizontal direction; and a plurality of lateral protruding portions that have a second width that is greater than the first width along the second horizontal direction, wherein the plurality of lateral protruding portions are staggered with the plurality of neck portions along the first horizontal direction.

[0011] According to one aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers; a memory opening that extends vertically through the alternating stack within a memory array region; a memory opening fill structure that is located in a corresponding one of the memory openings and includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; a layer contact via structure that contacts a corresponding one of the conductive layers and is located in a contact region that is laterally offset from the memory array region along the first horizontal direction; a lateral isolation trench fill structure that is positioned adjacent to the alternating stack, the lateral isolation trench fill structure including a plurality of narrower neck portions and wider lateral protruding portions that alternate with the neck portions along the first horizontal direction and are positioned in a transition region between the memory array region and the contact region along the first horizontal direction; a first type of support pillar structure that each extends vertically through the alternating stack in the contact region and is substantially composed of at least one dielectric material; and a second type of support pillar structure that each extends vertically through the alternating stack in the transition region and includes a corresponding set of dielectric material layers and a corresponding semiconductor material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure for forming a memory die after forming a barrier insulating layer, a source level material layer, and an alternating stack of an insulating layer and a sacrificial material layer over a carrier substrate according to an embodiment of the present disclosure.

[0013] Figure 2 is a schematic vertical cross - sectional view of a first exemplary structure after forming a stepped surface and a stepped dielectric material portion in accordance with an embodiment of the present disclosure.

[0014] Figure 3A is a schematic vertical cross - sectional view of a first exemplary structure after forming a memory opening and a support opening in accordance with an embodiment of the present disclosure. Figure 3B is Figure 3A a top - view of a first exemplary structure of Figure 3A The vertical plane A - A’ is the cutting plane of the vertical cross - sectional view of

[0015] Figure 4 is a vertical cross - sectional view of a first exemplary structure after forming a sacrificial opening filling structure in accordance with an embodiment of the present disclosure.

[0016] Figure 5 is a vertical cross - sectional view of a first exemplary structure after removing a first - type sacrificial support opening filling structure in accordance with an embodiment of the present disclosure.

[0017] Figure 6 is a vertical cross - sectional view of a first exemplary structure after forming a dielectric support pillar structure in accordance with an embodiment of the present disclosure.

[0018] Figure 7 is a vertical cross - sectional view of a first exemplary structure after removing a memory opening filling structure and a second - type sacrificial support opening filling structure in accordance with an embodiment of the present disclosure.

[0019] Figures 8A to 8D is a series of vertical cross - sectional views of a memory opening during the formation of a memory opening filling structure in accordance with an embodiment of the present disclosure.

[0020] Figure 9A is a vertical cross - sectional view of a first exemplary structure after forming a memory opening filling structure and a composite support pillar structure in accordance with an embodiment of the present disclosure. Figure 9B is Figure 9A a top - view of a first exemplary structure of Figure 9A The vertical plane A - A’ is the cutting plane of the vertical cross - sectional view of

[0021] Figure 10A is a vertical cross - sectional view of a first exemplary structure after forming a lateral isolation trench in accordance with an embodiment of the present disclosure. Figure 10B is Figure 10A a top - view of a first exemplary structure of Figure 10A The vertical plane A - A’ is the cutting plane of the vertical cross - sectional view of

[0022] Figures 11A to 11Fis a top view of an alternative configuration of a first exemplary structure at a processing step of Figure 10A and Figure 10B in accordance with an embodiment of the present disclosure.

[0023] Figure 12 is a vertical cross-sectional view of a first exemplary structure after forming a source electrode cavity in accordance with an embodiment of the present disclosure.

[0024] Figure 13 is a vertical cross-sectional view of a first exemplary structure after forming a source contact layer in accordance with an embodiment of the present disclosure.

[0025] Figure 14 is a vertical cross-sectional view of a first exemplary structure after forming a laterally extending cavity in accordance with an embodiment of the present disclosure.

[0026] Figures 15A to 15D is a sequential vertical cross-sectional view of a region of a first exemplary structure during formation of a conductive layer in accordance with an embodiment of the present disclosure.

[0027] Figure 16 is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer in accordance with an embodiment of the present disclosure.

[0028] Figure 17A is a vertical cross-sectional view of a first exemplary structure after forming an insulating spacer in accordance with an embodiment of the present disclosure. Figure 17B is Figure 17A a top view of a first exemplary structure. The vertical plane A-A’ is Figure 17A the cutting plane of a vertical cross-sectional view of Figure 17C is a vertical cross-sectional view of a first exemplary structure along the vertical plane C-C’. Figure 17D is a vertical cross-sectional view of a first exemplary structure along the vertical plane D-D’. Figure 17E is a vertical cross-sectional view of a first exemplary structure along the vertical plane E-E'.

[0029] Figures 18A to 18C is a vertical cross-sectional view of a first exemplary structure after forming a first metal barrier liner in accordance with an embodiment of the present disclosure. Figure 18A The cutting plane of Figure 17B corresponds to the vertical plane C-C′ of Figure 18B The cutting plane of Figure 17B corresponds to the vertical plane D-D′ of Figure 18C The cutting plane of Figure 17B corresponds to the vertical plane E-E′ of

[0030] Figures 19A to 19C is a vertical cross-sectional view of a first exemplary structure after forming a first metal layer in accordance with an embodiment of the present disclosure.Figure 19A The cutting plane of Figure 17B corresponds to the vertical plane C-C' of Figure 19B The cutting plane of Figure 17B corresponds to the vertical plane D-D' of Figure 19C The cutting plane of Figure 17B corresponds to the vertical plane E-E' of

[0031] Figures 20A to 20C is a vertical cross-sectional view of a first exemplary structure after forming a second metal barrier liner according to an embodiment of the present disclosure. Figure 20A The cutting plane of Figure 17B corresponds to the vertical plane C-C' of Figure 20B The cutting plane of Figure 17B corresponds to the vertical plane D-D' of Figure 20C The cutting plane of Figure 17B corresponds to the vertical plane E-E' of

[0032] Figures 21A to 21C is a vertical cross-sectional view of a first exemplary structure after forming a metal portion according to an embodiment of the present disclosure. Figure 21A The cutting plane of Figure 17B corresponds to the vertical plane C-C' of Figure 21B The cutting plane of Figure 17B corresponds to the vertical plane D-D' of Figure 21C The cutting plane of Figure 17B corresponds to the vertical plane E-E' of

[0033] Figures 22A to 22C is a vertical cross-sectional view of a first exemplary structure after forming a second metal layer according to an embodiment of the present disclosure. Figure 22A The cutting plane of Figure 17B corresponds to the vertical plane C-C' of Figure 22B The cutting plane of Figure 17B corresponds to the vertical plane D-D' of Figure 22C The cutting plane of Figure 17B corresponds to the vertical plane E-E' of

[0034] Figure 23A is a vertical cross-sectional view of a first exemplary structure after forming an isolation trench filling structure according to an embodiment of the present disclosure. Figure 23B is Figure 23A a top view of a first exemplary structure. The vertical plane A-A' is Figure 23A the cutting plane of the vertical cross-sectional view of Figure 23C a vertical cross-sectional view of a first exemplary structure along the vertical plane C-C'. Figure 23D is a vertical cross-sectional view of a first exemplary structure along the vertical plane D-D'. Figure 23EIt is a vertical cross-sectional view of a first exemplary structure along the vertical plane E-E'.

[0035] Figures 24A to 24F It is according to an embodiment of the present disclosure at Figure 23A and Figure 23B A top view of an alternative configuration of the first exemplary structure at the processing steps of

[0036] Figure 25A It is a vertical cross-sectional view of the first exemplary structure according to an embodiment of the present disclosure after forming a contact via structure. Figure 25B It is Figure 25A A top view of the first exemplary structure of Figure 25A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0037] Figure 26A It is a vertical cross-sectional view of the first exemplary structure according to an embodiment of the present disclosure after forming bit lines and bit line-level metal lines. Figure 26B It is Figure 26A A top view of the first exemplary structure of Figure 26A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of

[0038] Figure 27 It is a vertical cross-sectional view of the first exemplary structure according to an embodiment of the present disclosure after forming a memory die.

[0039] Figure 28 It is a vertical cross-sectional view of a logic die according to an embodiment of the present disclosure.

[0040] Figure 29 It is a vertical cross-sectional view of the first exemplary structure according to an embodiment of the present disclosure after forming a bonded assembly of a memory die and a logic die.

[0041] Figure 30 It is a vertical cross-sectional view of the first exemplary structure according to an embodiment of the present disclosure after removing a carrier substrate from the memory die.

[0042] Figure 31 It is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to an embodiment of the present disclosure after forming an alternating stack of an insulating layer and a sacrificial material layer.

[0043] Figure 32 It is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to an embodiment of the present disclosure after forming a memory-side metal interconnect structure and memory-side bonding pads.

[0044] Figure 33AA vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure. Figure 33B is Figure 33A a top view of the second exemplary structure. The vertical plane A-A’ is Figure 33A the cutting plane of the vertical cross-sectional view.

[0045] Figure 34A A vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer and a lateral isolation trench according to an embodiment of the present disclosure. Figure 34B is Figure 34A a top view of the second exemplary structure. The vertical plane A-A’ is Figure 34A the cutting plane of the vertical cross-sectional view.

[0046] Figure 35 A vertical cross-sectional view of a second exemplary structure after forming a source layer according to an embodiment of the present disclosure.

[0047] Figure 36 A vertical cross-sectional view of a second exemplary structure after replacing a sacrificial material layer with a conductive layer according to an embodiment of the present disclosure.

[0048] Figure 37A A vertical cross-sectional view of a second exemplary structure after forming insulating spacers according to an embodiment of the present disclosure. Figure 37B is Figure 37A a top view of the second exemplary structure. The vertical plane A-A’ is Figure 37A the cutting plane of the vertical cross-sectional view.

[0049] Figure 38A A vertical cross-sectional view of a second exemplary structure after forming a conductive filling structure in a lateral isolation trench according to an embodiment of the present disclosure. Figure 38B is Figure 38A a top view of the second exemplary structure. The vertical plane A-A’ is Figure 38A the cutting plane of the vertical cross-sectional view.

[0050] Figure 39A A vertical cross-sectional view of a second exemplary structure after forming various contact via structures according to an embodiment of the present disclosure. Figure 39B is Figure 39A a top view of the second exemplary structure. The vertical plane A-A’ is Figure 39A the cutting plane of the vertical cross-sectional view.

[0051] Figure 40A A vertical cross-sectional view of a third exemplary structure after forming a memory opening and a support opening according to an embodiment of the present disclosure. Figure 40B is Figure 40ATop view of the third exemplary structure. The vertical plane A-A’ is Figure 40A the cutting plane of the vertical sectional view of

[0052] Figure 41A Vertical sectional view of the third exemplary structure after forming the sacrificial opening fill structure according to an embodiment of the present disclosure. Figure 41B is Figure 41A Top view of the third exemplary structure. The vertical plane A-A’ is Figure 41A the cutting plane of the vertical sectional view of

[0053] Figure 42 Vertical sectional view of the third exemplary structure after removing the sacrificial support opening fill structure according to an embodiment of the present disclosure.

[0054] Figure 43A Vertical sectional view of the third exemplary structure after forming the support pillar structure according to an embodiment of the present disclosure. Figure 43B is Figure 43A Top view of the third exemplary structure. The vertical plane A-A’ is Figure 43A the cutting plane of the vertical sectional view of

[0055] Figure 44A Vertical sectional view of the third exemplary structure after removing the sacrificial memory opening fill structure according to an embodiment of the present disclosure. Figure 44B is Figure 44A Top view of the third exemplary structure. The vertical plane A-A’ is Figure 44A the cutting plane of the vertical sectional view of

[0056] Figure 45A Vertical sectional view of the third exemplary structure after forming the memory opening fill structure according to an embodiment of the present disclosure. Figure 45B is Figure 45A Top view of the third exemplary structure. The vertical plane A-A’ is Figure 45A the cutting plane of the vertical sectional view of Figure 45C and Figure 45D is Figure 45A Top view of an alternative configuration of the third exemplary structure of

[0057] Figure 46A Vertical sectional view of the third exemplary structure after forming the contact-level dielectric layer and the lateral isolation trenches according to an embodiment of the present disclosure. Figure 46B is Figure 46A Top view of the third exemplary structure. The vertical plane A-A’ is Figure 46A the cutting plane of the vertical sectional view of Figure 46C Perspective view of a region of the third exemplary structure.

[0058] Figure 47 is a vertical cross-sectional view of a third exemplary structure after forming a source electrode level cavity according to an embodiment of the present disclosure.

[0059] Figure 48 is a vertical cross-sectional view of a third exemplary structure after forming a source electrode contact layer according to an embodiment of the present disclosure.

[0060] Figure 49A is a vertical cross-sectional view of a third exemplary structure after forming a laterally extending cavity according to an embodiment of the present disclosure. Figure 49B is a perspective view of a region of a third exemplary structure.

[0061] Figure 50 is a vertical cross-sectional view of a third exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0062] Figure 51A is a vertical cross-sectional view of a third exemplary structure after forming a laterally isolated trench filling structure according to an embodiment of the present disclosure. Figure 51B is Figure 51A a top view of a third exemplary structure.

[0063] Figure 52A is a vertical cross-sectional view of a third exemplary structure after forming a contact via structure according to an embodiment of the present disclosure. Figure 52B is Figure 52A a top view of a third exemplary structure. The vertical plane A - A’ is Figure 52A the cutting plane of the vertical cross-sectional view.

[0064] Figure 53A is a vertical cross-sectional view of a third exemplary structure after forming a bit line and a bit line level metal line according to an embodiment of the present disclosure. Figure 53B is Figure 53A a top view of a third exemplary structure. The vertical plane A - A’ is Figure 53A the cutting plane of the vertical cross-sectional view.

[0065] Figure 54 is a vertical cross-sectional view of a third exemplary structure after forming a memory die according to an embodiment of the present disclosure.

[0066] Figure 55 is a vertical cross-sectional view of a third exemplary structure after forming a bonded assembly of a memory die and a logic die according to an embodiment of the present disclosure.

[0067] Figure 56 is a vertical cross-sectional view of a third exemplary structure after removing a carrier substrate from a memory die and forming a source electrode contact structure according to an embodiment of the present disclosure.

[0068] Figure 57A and Figure 57B is an alternative configuration vertical cross-sectional view of a third exemplary structure along corresponding vertical planes A-A' and B-B' in Figure 49B after forming an external barrier dielectric layer.

[0069] Figure 58A and Figure 58B is an alternative configuration vertical cross-sectional view of a third exemplary structure along corresponding vertical planes A-A' and B-B' in Figure 49B after depositing a conductive layer.

[0070] Figure 59A and Figure 59B is an alternative configuration vertical cross-sectional view of a third exemplary structure along corresponding vertical planes A-A' and B-B' in Figure 49B after removing the conductive layer from the lateral isolation trench.

[0071] Figure 60A and Figure 60B is an alternative configuration vertical cross-sectional view of a third exemplary structure along corresponding vertical planes A-A' and B-B' in Figure 49B after forming insulating spacers in the lateral isolation trench. DETAILED DESCRIPTION

[0072] As discussed above, the present disclosure relates to a three-dimensional memory device including a split support pillar structure and a method of manufacturing the same, aspects of which are described below.

[0073] The drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of illustrating a single instance of the element, unless otherwise explicitly described or clearly indicated as not existing. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0074] Like reference numerals denote like or similar elements. Unless otherwise specified, elements with the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "work-in-progress" structure refers to a transient structure that is subsequently modified in shape or composition of at least one of its components.

[0075] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers on, above, and / or below it.

[0076] Generally, a semiconductor die or a semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). Despite some limitations, the same, concurrent operations can be performed on each plane. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest programmable units, i.e., the smallest units on which a read operation can be performed.

[0077] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5Materials in the range of 1.0 S / m to 1.0 S / m, and which can generate a doped material with a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" is a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulating material" or "dielectric material" is a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" is a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0×10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material, or can be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant), the concentration of these electrical dopants providing a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" is a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semiconductor or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" is a conductive material containing at least one metallic element. All conductivity measurements are made under standard conditions.

[0078] Reference Figure 1 , illustrates a first exemplary structure according to an embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can be selectively removed relative to the material of the insulating layer 32 and the dielectric material portion to be formed subsequently.

[0079] An insulating material layer may be formed on the top surface of the carrier substrate 9. The insulating material layer may then be used as an etch stop material layer in the process of removing the carrier substrate 9, and is referred to herein as the etch stop insulating layer 106, or the backside pad dielectric layer. If a polishing process such as a chemical mechanical polishing process is used to subsequently remove the carrier substrate 9, the etch stop insulating layer 106 may then be used as a polishing stop material layer. If an etching process such as a wet etching process is used to subsequently remove the carrier substrate 9, the etch stop insulating layer 106 may then be used as an etch stop material layer. In one embodiment, the etch stop insulating layer 106 includes a dielectric material such as undoped silicate glass, doped silicate glass, or silicon nitride. The thickness of the etch stop insulating layer 106 may be in the range of 50 nm to 600 nm, such as 100 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0080] During the process, a source level material layer 110' may be formed above the etch stop insulating layer 106. The source level material layer 110' may include various layers that are subsequently modified to form the source level material layer. When formed, the source level material layer includes a source contact layer that serves as a common source region for the vertical field effect transistors of the three-dimensional memory device. In one embodiment, the source level material layer 110' may include, from bottom to top, a lower source level semiconductor layer 112, an optional lower sacrificial liner (not shown), a source level sacrificial layer 104, an optional upper sacrificial liner (not shown), and an upper source level semiconductor layer 116.

[0081] The lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conduction type of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conduction type, the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 have a doping of a second conduction type opposite to the first conduction type. The thickness of each of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0082] The source-level sacrificial layer 104 comprises a sacrificial material that can be selectively removed relative to the lower sacrificial liner (or relative to the lower source-level semiconductor layer 112) and the upper sacrificial liner (or relative to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 may comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with a germanium atom concentration greater than 20%. The thickness of the source-level sacrificial layer 104 may range from 30 nm to 400 nm, such as 60 nm to 200 nm, although smaller and larger thicknesses may also be used. The lower sacrificial liner (if present) and the upper sacrificial liner (if present) comprise materials that can be used as an etch-stop material during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner and the upper sacrificial liner may comprise silicon oxide, silicon nitride, and / or dielectric metal oxides. In one embodiment, each of the lower sacrificial liner and the upper sacrificial liner may comprise a silicon oxide layer having a thickness in the range of 2 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0083] An alternating stack of the first material layer and the second material layer may be formed over the in-process source-level material layer 110′. The alternating sequence includes a vertical alternating stack in which the first material layer and the second material layer are staggered along the vertical direction. In an alternative embodiment, the in-process source-level material layer 110′ and the blocking insulating layer 106 may be omitted, and the alternating stack is formed directly on the surface of the carrier substrate 9. In another alternative embodiment described below with respect to Figure 31 and Figure 32 , prior to forming the alternating stack, the peripheral circuit is formed on the same substrate as the alternating stack. For example, the peripheral circuit may include a word line driver region, a bit line driver region, a sense amplifier region, an input / output buffer, etc. In this alternative embodiment, a separate logic die comprising the peripheral circuit may be omitted. In this alternative embodiment, the alternating stack may be deposited on the in-process source-level material layer 110′, or the in-process source-level material layer 110′ may be omitted, and the alternating stack may be deposited on the blocking insulating layer 106.

[0084] In the alternating stack, the first material layer may be an insulating layer and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed over a carrier substrate 9 (e.g., over the source level material layer 110' during the process if present). The insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer and the sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer. The alternating stack (32, 42) may include multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, although smaller and larger numbers of repetitions may also be employed. Hereinafter, the topmost one of the insulating layers 32 is referred to as the topmost insulating layer 32T. The bottommost one of the insulating layers 32 is the insulating layer 32 closest to the carrier substrate 9, which is referred to herein as the bottommost insulating layer 32B. Each of the insulating layers 32 other than the topmost insulating layer 32 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, although smaller and larger thicknesses may also be employed. Each of the sacrificial material layers 42 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, although smaller and larger thicknesses may also be employed. In one embodiment, the topmost insulating layer 32 may have a thickness of approximately half of the thickness of the other insulating layers 32.

[0085] The first exemplary structure includes a memory array region 100 in which a three-dimensional array of memory elements will be subsequently formed and a contact region 300 in which a layer contact via structure for contacting word lines will be subsequently formed. The first exemplary structure also includes a transition region 200 in which support openings and a composite support pillar structure including multiple materials will be subsequently formed. The insulating layer 32 extends continuously across the memory array region 100 and the contact region 300 without being patterned and may be referred to as the continuous insulating layer 32. The sacrificial material layer 42 extends continuously across the memory array region 100 and the contact region 300 without being patterned and may be referred to as the continuous sacrificial material layer 42. Thus, a vertical alternating sequence of the continuous insulating layer 32 and the continuous sacrificial material layer 42 may be formed.

[0086] Reference Figure 2, a stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface that extends upward from a first edge of the horizontal surface and is adjacent to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and portions of the alternating stacks (32, 42) are removed from the stepped cavity by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0087] The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the source-level material layer 110' in the process. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example, a first type of etching process and a second type of etching process. The first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the area that is vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including multiple alternating ones is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0088] Each sacrificial material layer 42 within the alternating stacks (32, 42) other than the topmost sacrificial material layer 42 extends further laterally than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mesa region. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0089] A stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed, for example, by chemical mechanical planarization (CMP) from above the top surface of the topmost insulating layer 32T. The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the stepped dielectric material portion 65, which can be an inverse-stepped dielectric material portion. As used herein, an "inverse-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 can or can not be doped with dopants such as B, P, and / or F.

[0090] Optionally, a drain select level isolation structure (not shown) may be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 located at the drain select level. For example, the drain select level isolation structure may be formed by forming a drain select level lateral isolation trench and filling the drain select level lateral isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material may be removed from above the top surface of the topmost insulating layer 32T.

[0091] Reference Figure 3A and Figure 3B , an etch mask layer (not shown) may be formed over the alternating stack (32, 42) and may be lithographically patterned to form openings therein. An anisotropic etching process may be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42) to form memory openings 49 and support openings 19. The memory openings 49 may be formed through the alternating stack (32, 42) in the memory array region 100. Each of the memory openings 49 in the memory openings may vertically extend through the alternating stack (32, 42) and into the in-process source level material layer 110'. In one embodiment, the bottom surface of the memory openings 49 may be formed within the lower source level semiconductor layer 112 or at the interface between the lower source level semiconductor layer and the blocking insulating layer 106. The support openings 19 may be formed through the alternating stack (32, 42) and the stepped dielectric material portion 65 in the contact region 300 and the transition region 200. In one embodiment, the support openings 19 may have the same depth as the memory openings 49. The support openings 19 may include a first type of support opening 19A formed in the contact region 300 and a second type of support opening 19B formed in the transition region 200.

[0092] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1 by a transition region 200. Memory openings 49 may include rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. A plurality of clusters of memory openings 49 may be formed in the memory array region 100, each cluster of memory openings comprising a respective two-dimensional periodic array of memory openings 49. The clusters of memory openings 49 may be laterally spaced along the second horizontal direction hd2 by strip regions that do not contain any openings (49, 19). Similarly, a plurality of clusters of first type support openings 19A may be formed in the contact region 300 such that the clusters of first type support openings 19A may be laterally spaced along the second horizontal direction hd2 by strip regions that do not contain any openings (49, 19). Additionally, a plurality of clusters of second type support openings 19B may be formed in the transition region such that the clusters of second type support openings 19B may be laterally spaced along the second horizontal direction hd2 by strip regions that do not contain any openings (49, 19).

[0093] Reference Figure 4 , a sacrificial fill material, such as amorphous carbon or diamond-like carbon, may be deposited in the memory openings 49 and the support openings 19 by a conformal deposition process. The excess of the sacrificial fill material may be removed from above a horizontal plane of the top surface including the topmost insulating layer 32T by a planarization process such as a recess etching process or a chemical mechanical polishing process. The remaining portion of the sacrificial fill material that fills the memory openings 49 constitutes a sacrificial memory opening fill structure 47. The remaining portion of the sacrificial fill material that fills the first type support openings 19A constitutes a first type sacrificial support opening fill structure 17A. The remaining portion of the sacrificial fill material that fills the second type support openings 19B constitutes a second type sacrificial support opening fill structure 17B.

[0094] Reference Figure 5 , a hard mask layer 21 may be applied over the first exemplary structure and may be lithographically patterned to cover the memory array region 100 and the transition region 200 without covering the contact region 300. The hard mask layer 21 may include a dielectric material such as silicon oxide or silicon nitride and may have a thickness in the range of 10 nm to 50 nm, although smaller and larger thicknesses may also be employed. The first type sacrificial support opening fill structure 17A may be selectively removed relative to the hard mask layer 21, the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), and the in-process source electrode layer 110' by performing a selective removal process such as an ashing process. A cavity is formed in the volume of the reopened first type support openings 19A.

[0095] Reference Figure 6, a dielectric fill material, such as silicon oxide, can be deposited in the first type of support opening 19A. The excess portions of the dielectric fill material and the hard mask layer that overlie the horizontal plane including the top surface of the stepped dielectric material portion 65 can be removed by a planarization process such as a recess etching process or a chemical mechanical polishing process. The remaining portion of the dielectric fill material that fills the first type of support opening 19A constitutes the first type of support pillar structure 20A. The first type of support pillar structure 20A extends vertically through the vertical alternating sequence (32, 42) in the contact region 300. In one embodiment, the first type of support pillar structure 20A is substantially composed of at least one dielectric material (such as silicon oxide).

[0096] Reference Figure 7 , the sacrificial memory opening fill structure 47 and the second type of sacrificial support opening fill structure 17B can be selectively removed relative to the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), the first type of support pillar structure 20A, and the material of the in-process source level material layer 110' by performing a selective removal process such as an ashing process. Cavities are formed in the volumes of the memory opening 49 and the second type of support opening 19B to re-open the memory opening 49 and the second type of support opening 19B.

[0097] Figures 8A to 8D is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening fill structure 58 in each memory opening 49 and the formation of the second type of support pillar structure 20B (e.g., dummy memory opening fill structure) in each second type of support opening 19B according to an embodiment of the present disclosure. The memory opening fill structure 58 can include vertical NAND strings.

[0098] Reference Figure 8A , illustrates the memory opening 49 after the processing steps of Figure 7 .

[0099] Reference Figure 8B , a layer stack including a memory material layer 54 can be conformally deposited. In an illustrative example, the layer stack can include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 can include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 can include a tunneling dielectric layer.

[0100] The semiconductor channel material layer 60L can be deposited over the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L can have a doping of a first conductivity type, which can be p-type or n-type. In one embodiment, the first semiconductor material includes a first doped silicon material having a doping of a first conductivity type. In an illustrative example, the atomic concentration of the dopant of the first conductivity type in the semiconductor channel material layer 60L can be in the range of 1.0×10 13 / cm 3 to 3.0×10 17 / cm 3 , such as 1.0×10 14 / cm 3 to 3.0×10 16 / cm 3 , but smaller and larger atomic concentrations can also be employed. A dielectric core layer 62L including a dielectric fill material can be deposited in the remaining volume of the memory opening 49 and over the alternating stack (32, 42).

[0101] Referring Figure 8C , the dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane of the bottom surface including the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0102] Referring Figure 8D , a doped semiconductor material having a doping of a second conductivity type can be deposited in each recessed area over the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0103] The excess portion of the deposited doped semiconductor material having a second conductivity type and the horizontal portion of the semiconductor channel material layer 60L can be removed from above a horizontal plane of the top surface including the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or recess etching processes. Each remaining portion of the doped semiconductor material having a second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has a doping of a first conductivity type) constitutes a vertical semiconductor channel 60.

[0104] Each portion of the layer stack including the memory material layer 54 retained in the corresponding memory opening 49 constitutes the memory membrane 50. In one embodiment, the memory membrane 50 may include an optional barrier dielectric layer 52, the memory material layer 54, and an optional dielectric liner 56. Each adjacent combination of the memory membrane 50 and the vertical semiconductor channel 60 constitutes the memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes the memory opening fill structure 58. Each memory opening fill structure 58 includes a corresponding vertical stack of memory elements, and the corresponding vertical stack may include a portion of the memory material layer 54 at the level of the sacrificial material layer 42, or generally at the level of a spacer material layer that can subsequently be at least partially replaced by a conductive layer.

[0105] Reference Figure 9A and Figure 9B illustrates a first exemplary structure after forming the memory opening fill structure 58 within the memory opening 49 in the memory array region 100. Each memory opening fill structure within the memory opening fill structure 58 may include the memory membrane 50 and the vertical semiconductor channel 60. Each memory opening fill structure within the memory opening fill structure 58 includes a corresponding vertical stack of memory elements, and the vertical stack may include a portion of the corresponding memory material layer 54 at the level of the sacrificial material layer 42. The second type of support pillar structure 20B is formed within the second type of support opening 19B located within the transition region 200. Each second type of support pillar structure 20B may have the same set of material portions as the memory opening fill structure 58.

[0106] Each second type of support pillar structure within the second type of support pillar structure 20B includes a corresponding set of dielectric material layers and a corresponding semiconductor material layer. Each set of dielectric material layers may have the same set of material layers as the memory membrane 50. In other words, each memory membrane 50 has the same set of materials as a set of dielectric material layers within the second type of support pillar structure 20B and has the same thickness as that set of dielectric material layers. Additionally, each memory opening fill structure within the memory opening fill structure 58 includes a vertical semiconductor channel 60 having the same material composition and the same thickness as the semiconductor material layer within the second type of support pillar structure 20B. Each semiconductor material layer may have the same material composition and the same thickness as the vertical semiconductor channel 60. Thus, the second type of support pillar structure 20B includes a dummy memory opening structure having the same structure and composition as the memory opening fill structure 58, but it is not electrically connected to the bit line and is not used for storing data during the operation of the memory device.

[0107] Reference Figure 10A andFigure 10B A dielectric material, such as undoped silicate glass or doped silicate glass, may be deposited over the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 may be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, although smaller and larger thicknesses may also be employed.

[0108] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form various openings therein. The openings in the photoresist layer include elongated laterally undulating openings that extend generally along a first horizontal direction hd1 in a strip region between clusters proximate to the memory opening fill structure 58 (e.g., between adjacent memory block regions).

[0109] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), and the stepped dielectric material portion 65 and into the in-process source-level material layer 110' (if present). Lateral isolation trenches 79 may be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the in-process source-level material layer 110' (if present). The lateral isolation trenches 79 extend vertically through each layer within the alternating stack (32, 42) and into an upper portion of the semiconductor material layer, which may be located within the in-process source-level material layer 110' or, if the in-process source-level material layer 110' is omitted, may comprise the top portion of the carrier substrate 9. The lateral isolation trenches 79 extend laterally along the first horizontal direction hd1 (e.g., the word line direction). Each of the lateral isolation trenches 79 may include a respective pair of laterally undulating longitudinal sidewalls that extend generally along the first horizontal direction hd1, have a respective width modulation along a second horizontal direction hd2, and extend from the blocking insulating layer 106 vertically to the top surface of the contact-level dielectric layer 80. In one embodiment, the lower source-level semiconductor layer 112 may be physically exposed under each of the lateral isolation trenches 79.

[0110] In one embodiment, the lateral isolation trench 79 may have a corresponding vertical cross-sectional profile including a transition line 79I at which a tapered surface section of a continuously extending sidewall abuts a frustoconical surface section of the continuously extending sidewall. As used herein, a tapered surface section refers to a surface section where the lateral dimension of the volume of an element increases with the vertical distance from the underlying substrate, and a frustoconical surface section refers to a surface section where the lateral dimension of the volume of an element decreases with the vertical distance from the underlying substrate. Thus, in one embodiment, the sidewalls of the lateral isolation trench 79 may optionally have a gradually changing slope and may optionally have a curved vertical cross-sectional profile with the maximum width located at the transition line 79I. The lateral isolation trench 79 may have a maximum lateral width along the second horizontal direction hd2 at the transition line 79I. Each transition line may extend generally laterally along the first horizontal direction hd1 and may have a corresponding periodic lateral undulation along the second horizontal direction hd2.

[0111] Generally speaking, the lateral isolation trench 79 may be formed through a vertically alternating sequence (32, 42). Each lateral isolation trench 79 may include a pair of longitudinal sidewalls extending generally along the first horizontal direction hd1. The vertical cross-sectional profile of the lateral isolation trench 79 in a vertical plane perpendicular to the first horizontal direction hd1 has a variable width that increases with the vertical distance from a horizontal plane including the bottommost surface of the vertically alternating sequence (32, 42) in the lower portion of the vertically alternating sequence (32, 42) to a horizontal plane including the transition line 79I, and decreases with the vertical distance from the horizontal plane including the transition line 79I in the upper portion of the vertically alternating sequence (32, 42), as Figure 10A shown. In one embodiment, each lateral isolation trench 79 has a width modulation along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 that varies with the lateral distance along the first horizontal direction hd1, as Figure 10B shown.

[0112] In Figure 10B one embodiment shown, each lateral isolation trench 79 includes a periodic lateral alternating sequence of a neck portion (e.g., region) 79N having a minimum width along the second horizontal direction hd2 and a protruding portion (e.g., region) 79B having a maximum width along the second horizontal direction hd2. In Figure 10BIn the illustrated embodiment, the neck portion 79N includes horizontally linear (i.e., straight) sidewalls, and the protruding portion 79B includes horizontally convex sidewalls that protrude outward from the center of the lateral isolation trench 79. In this embodiment, each lateral isolation trench 79 includes a pair of laterally undulating longitudinal sidewalls that have lateral undulations at the protruding portion 79B; and each of the pair of laterally undulating longitudinal sidewalls includes a set of horizontally convex and vertically tapering surface segments in the protruding portion 79B that abut, at the edges, horizontally linear and vertically tapering surface segments in the neck portion 79N.

[0113] In Figure 10B In the illustrated embodiment, each lateral isolation trench 79 extends generally along a first horizontal direction hd1 through a vertically alternating sequence (32, 42). Each lateral isolation trench 79 includes a plurality of neck portions 79N that have a first width w1 along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 between a corresponding pair of straight surface segments that extend along the first horizontal direction hd1. Each lateral isolation trench 79 also includes a plurality of laterally protruding portions 79B that have a variable width that is greater than the first width w1 along the second horizontal direction. The plurality of laterally protruding portions 79B are staggered with the plurality of neck portions 79N along the first horizontal direction hd1. In one embodiment, the maximum value of the variable width can be a second width w2 at the middle of the laterally protruding portion 79B.

[0114] In Figure 10B In one illustrated embodiment, the memory opening fill structures 58 can be arranged in rows that extend laterally along the first horizontal direction hd1. The memory opening fill structures 58 located within each row of the memory opening fill structures 58 can be arranged at a uniform pitch along the first horizontal direction hd1, which is referred to herein as a first pitch p1. In one embodiment, the plurality of laterally protruding portions 79B have a uniform pitch along the first horizontal direction hd1, which is referred to herein as a second pitch p2. The second pitch p2 can be the same as the first pitch p1, or can be greater than the first pitch p1. Each of the plurality of laterally protruding portions 79B can be laterally bounded along the second horizontal direction hd2 by a pair of laterally convex surface segments that are laterally spaced apart from each other. As used herein, a laterally convex surface has a convex profile in a horizontal cross-sectional view. A laterally concave surface has a concave profile in a horizontal cross-sectional view.

[0115] In one embodiment, each of the laterally convex surface sections of the laterally convex portion 79B may be laterally bounded in a horizontal cross-sectional view by alternately stacked concave surfaces of the insulating layer 32 and the sacrificial material layer 42. A plurality of laterally convex portions 79B are formed at least in the transition region 200, and may be formed in the memory array region 100 and / or in the contact region 300. In one embodiment, a first subset of the laterally convex portions 79B may be located in the transition region 200, a second subset of the laterally convex portions 79B may be located in the memory array region 100, and a third subset of the laterally convex portions 79B may be located in the contact region 300.

[0116] Figures 11A to 11F According to the embodiments of the present disclosure Figure 10A and Figure 10B A top view of an alternative configuration of the first exemplary structure at a processing step of . Figures 11A to 11F In the illustrated alternative configuration, the lateral protruding portion 79B of the lateral isolation trench 79 may be formed completely within the transition region 200. In this case, the portion of each lateral isolation trench 79 having the lateral width fluctuation is referred to as a width fluctuation region WUR.

[0117] refer to Figure 11A , exemplified in reference Figure 10A and Figure 10B A first alternative configuration of the first exemplary structure after the described processing steps. Each lateral isolation trench 79 includes a plurality of neck portions 79N and a plurality of lateral protrusions 79B, the plurality of neck portions having a first width w1 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and the plurality of lateral protrusions having a variable width greater than the first width w1 along the second horizontal direction. The plurality of lateral protrusions 79B are staggered with the plurality of neck portions 79N along the first horizontal direction hd1. The plurality of lateral protrusions 79B and the neck portions 79N may be formed entirely within a transition region 200 located between a corresponding pair of straight surface sections 79S extending along the first horizontal direction hd1 in the memory array region 100 and the contact region 300. In this embodiment, the neck portion 79N may not contain straight sidewalls and may be located where the edges of adjacent protrusions 79B meet each other.

[0118] In one embodiment, the maximum value of the variable width is the second width w2. In a first alternative configuration, the entire portion of each lateral isolation trench 79 located in the memory array region 100 may have a uniform array region width wa that is less than the second width w2, and the entire portion of each lateral isolation trench 79 located in the contact region 300 may have a uniform contact region width wc that is less than the second width w2. In one embodiment, the uniform array region width wa is not less than the first width w1; and the uniform contact region width wc is not less than the first width w1. In one embodiment, the uniform array region width wa and the uniform contact region width wc may be the same as the first width w1 of the neck portion 79N. In one embodiment, the plurality of lateral protrusions 79B in each lateral isolation trench 79 have a uniform pitch along the first horizontal direction hd1, and the uniform pitch may be the same as the first pitch p1.

[0119] Reference Figure 11B , the second alternative configuration of the first exemplary structure can be obtained from the first alternative configuration of the first exemplary structure by selecting the value of the uniform array region width wa to be greater than the first width w1, and / or by selecting the value of the uniform contact region width wc to be greater than the first width w1.

[0120] Reference Figure 11C , the third alternative configuration of the first exemplary structure can be obtained from the first alternative configuration of the first exemplary structure by providing straight surface segments in each lateral protrusion of the lateral protrusions 79B of the lateral isolation trench 79 and each neck portion of the neck portion 79N. In this case, each lateral protrusion of the plurality of lateral protrusions 79B includes a corresponding uniform width portion having the second width w2. Each lateral protrusion of the plurality of lateral protrusions 79B may be laterally defined by four lateral concave surface segments that are laterally spaced apart from each other and do not directly contact each other.

[0121] Reference Figure 11D , the fourth alternative configuration of the first exemplary structure can be obtained from the third alternative configuration of the first exemplary structure by providing a plurality of stepped increases in the variable width of the lateral protrusions 79B of the lateral isolation trench 79. In this case, each lateral protrusion of the plurality of lateral protrusions 79B may be laterally defined by four sets of lateral concave surface segments, each set including two lateral concave surface segments that are laterally spaced apart from each other and do not directly contact each other.

[0122] Reference Figure 11E, a fifth alternative configuration of the first exemplary structure can be derived from a second alternative configuration of the first exemplary structure by providing a straight surface section in each of the lateral protruding portions 79B of the lateral isolation trench 79 and in each of the neck portions 79N. In this case, each of the plurality of lateral protruding portions 79B includes a corresponding uniform-width portion having a second width w2. Each of the plurality of lateral protruding portions 79B can be laterally defined by four laterally concave surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0123] Reference Figure 11F , a sixth alternative configuration of the first exemplary structure can be obtained from the fifth alternative configuration of the first exemplary structure by providing a plurality of stepped increases in the variable width of the lateral protruding portions 79B of the lateral isolation trench 79. In this case, each of the plurality of lateral protruding portions 79B can be laterally defined by four sets of laterally concave surface sections, each set including two laterally concave surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0124] As Figures 11A to 11F shown, each of the lateral protruding portions 79B can be positioned adjacent to a corresponding second type of support pillar structure 20B along a second horizontal direction hd2. Without wishing to be bound by a particular theory, the ions used to etch the lateral isolation trench 79 during a reactive ion etching process are concentrated in the lateral protruding portions 79B adjacent to the corresponding second type of support pillar structure 20B. The second type of support pillar structure 20B provides support for the device structure and minimizes the bending of the lateral isolation trench 79 along the second horizontal direction hd2 due to ion attack on the sidewalls of the lateral isolation trench 79. In addition, by concentrating the ions in the lateral protruding portions 79B adjacent to the corresponding second type of support pillar structure 20B, the ion attack on the first type of support pillar structure 20A is reduced, which can be entirely composed of the same material as the insulating layer 32 (e.g., silicon oxide), and this material is etched by the reactive ion etching process. This also reduces the bending of the lateral isolation trench 79 along the second horizontal direction hd2.

[0125] Reference Figure 12, if the source electrode layer 110' is used during the use process, the source electrode sacrificial layer 104 is selectively removed through the lateral isolation trench 79. The etchant can be introduced into the lateral isolation trench 79 by performing an isotropic etching process, and the etchant selectively etches the material of the source electrode sacrificial layer 104 with respect to the materials of the alternating stack (32, 42), the contact electrode dielectric layer 80, the stepped dielectric material portion 65, the lower source electrode semiconductor layer 112, the upper source electrode semiconductor layer 116, the upper sacrificial liner 105 (if present), and the lower sacrificial liner 103 (if present). For example, if the source electrode sacrificial layer 104 comprises undoped amorphous silicon or a silicon-germanium alloy, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide ("hot TMY") or tetramethyl ammonium hydroxide (TMAH) can be used to selectively remove the source electrode sacrificial layer 104 with respect to the alternating stack (32, 42), the contact electrode dielectric layer 80, the stepped dielectric material portion 65, the lower source electrode semiconductor layer 112, and the upper source electrode semiconductor layer 116. The source cavity 109 is formed in the volume from which the source electrode sacrificial layer 104 is removed.

[0126] Wet etching chemicals such as hot TMY and TMAH are selective for doped semiconductor materials such as p-doped semiconductor materials and / or n-doped semiconductor materials of the upper source electrode semiconductor layer 116 and the lower source electrode semiconductor layer 112. Therefore, using selective wet etching chemicals (such as hot TMY and TMAH) for the wet etching process of forming the source cavity 109 provides a large process window for resisting etching depth variations during the formation of the lateral isolation trench 79. Specifically, even if the sidewalls of the upper source electrode semiconductor layer 116 are physically exposed or even if the surface of the lower source electrode semiconductor layer 112 is physically exposed when forming the source cavity 109, the collateral etching of the upper source electrode semiconductor layer 116 and / or the lower source electrode semiconductor layer 112 is minimal, and the structural changes to the first exemplary structure caused by the accidental physical exposure of the surface of the upper source electrode semiconductor layer 116 and / or the lower source electrode semiconductor layer 112 during the manufacturing steps do not result in device failure. Each memory opening filling structure in the memory opening filling structure 58 is physically exposed to the source cavity 109. Specifically, each memory opening filling structure in the memory opening filling structure 58 includes sidewalls and is physically exposed to the source cavity 109.

[0127] A series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portion of the memory film 50 to sequentially etch various groups of layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper sacrificial liner 105 (if present) and the lower sacrificial liner 103 (if present) can be incidentally etched during the removal of the portion of the memory film 50 located at the level of the source cavity 109. The volume of the source cavity 109 can be enlarged by removing the portions of the memory film 50 at the levels of the source cavity 109 and the upper and lower sacrificial liners. The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each memory film in the memory film 50 relative to at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0128] Reference Figure 13 , a doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surfaces of at least one source-level semiconductor layer (such as the bottom surface of the upper source-level semiconductor layer 116 and / or the top surface of the lower source-level semiconductor layer 112). For example, the physically exposed semiconductor surface can include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the upper source-level semiconductor layer 116.

[0129] In one embodiment, the doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant gas can flow into the process chamber including the first exemplary structure simultaneously. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the dopant gas can include hydrides of dopant atoms such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material of the second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms the source contact layer 114, which can contact the sidewall of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be in the range of 1.0×10 20 / cm 3 to 2.0×1021 / cm 3 within the range of, such as 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may be substantially composed of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0130] The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material having the second conductivity type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source-level sacrificial layer 104 may be replaced with the source contact layer 114. The layer stack including the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116 constitutes the source-level material layer 110, and the source-level material layer 110 replaces the source-level material layer 110' during the replacement process. The source-level material layer 110 contacts the end portions of each vertical semiconductor channel in the vertical semiconductor channel 60. Optionally, a dielectric surface conversion process (such as an oxidation process or a nitridation process) may be performed to convert the surface portions of the source-level material layer 110 physically exposed from under each lateral isolation trench 79 to form the trench bottom dielectric liner 129. The source-level material layer 110 includes a stack of semiconductor material layers, such as the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116.

[0131] Reference Figure 14 and Figure 15A and, an isotropic etching process may be performed to selectively remove the sacrificial material layer 42 with respect to the insulating layer 32, the blocking insulating layer 106, the memory opening filling structure 58, and the source-level material layer 110. A laterally extending cavity 43 may be formed in the volume where the sacrificial material layer 42 is removed. The sidewall surface section of the memory opening filling structure 58 may be physically exposed to the laterally extending cavity 43. In an illustrative example, if the sacrificial material layer 42 contains silicon oxide, the isotropic etching process may include a wet etching process using hot phosphoric acid, which is a process in which the first exemplary structure is immersed in phosphoric acid at or near the boiling point of phosphoric acid. A suitable cleaning process may be performed as needed.

[0132] Reference Figure 15B, an external blocking dielectric layer 44 can optionally be formed in the laterally extending cavity 43 through a conformal deposition process.

[0133] Reference Figure 15C , a metal barrier material can be conformally deposited in the laterally extending cavity 43. The metal barrier material can include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof.

[0134] Reference Figure 15D and Figure 16 , a metal fill material can be conformally deposited in the remaining volume of the laterally extending cavity 43. The metal fill material can include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or their alloys or layer stacks. The excess portion of at least one conductive material deposited in the laterally isolated trench 79 or above the contact-level dielectric layer 80 can be removed by performing an etch-back process, which can include an isotropic etching process and / or an anisotropic etching process. Each remaining portion of at least one conductive material filling a corresponding one of the laterally extending cavities in the laterally extending cavity 43 constitutes a conductive layer 46. An alternating stack of the insulating layer 32 and the conductive layer 46 can be formed between each pair of adjacent laterally isolated trenches 79 above the carrier substrate 9. A plurality of alternating stacks of the insulating layer 32 and the conductive layer 46 can be laterally spaced apart from each other by the laterally isolated trenches 79. The conductive layer 46 includes word lines and select gate electrodes.

[0135] A plurality of alternating stacks (32, 46) of the insulating layer 32 and the conductive layer 46 can be formed, and the plurality of alternating stacks can be laterally spaced apart from each other by the laterally isolated trenches 79. Each pair of laterally adjacent alternating stacks (32, 46) can be laterally spaced apart from each other by the laterally isolated trench 79 extending laterally along the first horizontal direction hd1. A memory opening 49 extends vertically through a corresponding one of the alternating stacks (32, 46). A memory opening filling structure 58 can be located in a corresponding one of the memory openings 49. Each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50) at the level of the conductive layer 46.

[0136] Reference Figures 17A to 17E , an insulating material can be conformally deposited in the laterally isolated trench 79 and can be anisotropically etched to form insulating spacers 74 in the peripheral portion of the laterally isolated trench 79. The portion of the trench bottom dielectric liner 129 not covered by the insulating spacers 74 can be removed such that the surface of the source-level material layer 110 is exposed under each laterally isolated trench 79.

[0137] The insulating spacer 74 includes a dielectric material such as undoped silicate glass or doped silicate glass. Each insulating spacer in the insulating spacer 74 may include a pair of laterally undulating outer sidewalls and a pair of laterally undulating inner sidewalls. A lateral isolation cavity 79' may be present within each lateral isolation trench 79.

[0138] Reference Figures 18A to 18C , the first metal barrier liner 762 may be conformally deposited on the physically exposed surfaces of the insulating spacer 74, the source-level material layer 110, and the contact-level dielectric layer 80. For example, a chemical vapor deposition process may be used to deposit the first metal barrier liner 762. The first metal barrier liner 762 may include a conductive metal nitride material such as TiN, TaN, WN, MoN, etc., and may have a thickness in the range of 5 nm to 100 nm, although smaller and larger thicknesses may also be employed. Alternatively, a refractory metal layer such as Ti, Ta, W, or Mo may be conformally deposited on the physically exposed surfaces of the insulating spacer 74, the source-level material layer 110, and the contact-level dielectric layer 80, and then exposed to a nitrogen-containing environment (e.g., an ammonia-containing environment) at an elevated temperature to convert the refractory metal layer into a conductive metal nitride material such as TiN, TaN, WN, MoN, etc. of the first metal barrier liner 762.

[0139] Reference Figures 19A to 19C , the first metal layer 763 may be conformally deposited on the physically exposed surface of the first metal barrier liner 762. For example, chemical vapor deposition may be used to deposit the first metal layer 763. The first metal layer 763 includes a first metal, which may be an elemental metal or an intermetallic compound. For example, the first metal layer 763 may include W, Ti, Ta, Mo, etc., and / or may consist essentially of W, Ti, Ta, Mo, etc. The thickness of the first metal layer 763 may be in the range of 20 nm to 100 nm, although smaller and larger thicknesses may also be employed.

[0140] Reference Figures 20A to 20C , the second metal barrier liner 764 may be non-conformally deposited on the horizontally extending portion of the first metal layer 763 that overlies the contact-level dielectric layer 80 and in the upper portion of the first metal layer 763 adjacent to the contact-level dielectric layer 80. For example, the second metal barrier liner 764 may be deposited by physical vapor deposition. The second metal barrier liner 764 may include a conductive metal nitride material such as TiN, TaN, WN, MoN, etc. The horizontally extending portion of the second metal barrier liner 764 that overlies the contact-level dielectric layer 80 may have a thickness in the range of 5 nm to 30 nm, although smaller and larger thicknesses may also be employed.

[0141] Reference Figures 21A to 21C, a selective metal deposition process can be performed to grow a second metal from the physically exposed surface of the first metal layer 763 while suppressing the growth of the second metal from the physically exposed surface of the second metal barrier liner 764. For example, a metal such as W, Ti, Ta, or Mo can be grown from the physically exposed surface of the first metal layer 763 by a chemical vapor deposition process. In an illustrative example, the chemical vapor deposition process can employ a fluorine-containing metal precursor gas (such as tungsten hexafluoride) or a chlorine-containing metal precursor gas that decomposes on a metal surface (such as a tungsten surface) and does not decompose on a metal nitride surface (such as a titanium nitride surface). The deposited portion of the second metal is referred to herein as the metal portion 765. The thickness of each metal portion 765 can be in the range of 30 nm to 150 nm, although smaller and larger thicknesses can also be employed. The metal portion 765 reduces the volume of the unfilled cavity in the lateral isolation trench 79.

[0142] Reference Figures 22A to 22C , a second metal layer 766 can be conformally deposited by a conformal deposition process such as a chemical vapor deposition process to fill the remaining portion of the lateral isolation trench 79. The lateral protrusion 79B in the lateral isolation trench 79 serves as an entry path for the precursor reactants for depositing the second metal. The second metal can include elemental metals or intermetallic alloys. The second metal can include W, Ti, Ta, Co, Ru, Mo, Cu, or alloys thereof. An encapsulation cavity (i.e., air gap) 767 that does not contain any solid-phase material can be formed in the central portion of the lateral protrusion of the lateral isolation trench 79.

[0143] Reference Figures 23A to 23E , a planarization process such as a chemical mechanical polishing process can be performed to remove the portions of the metal materials of the first metal barrier liner 762, the first metal layer 763, the second metal barrier liner 764, and the second metal layer 766 that overlie a horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the metal material retained in the respective lateral isolation trench 79 constitutes a conductive fill structure 76. Each adjacent combination of the insulating spacer 74 and the conductive fill structure 76 constitutes a lateral isolation trench fill structure (74, 76).

[0144] Each lateral isolation trench fill structure (74, 76) includes an insulating spacer 74 and a conductive fill structure 76 laterally surrounded by the insulating spacer 74. In one embodiment, each insulating spacer 74 includes a pair of outer longitudinal sidewalls, each of which includes a plurality of laterally convex surface segments interleaved with a plurality of first laterally straight surface segments; and a pair of inner longitudinal sidewalls, each of which includes a plurality of laterally concave surface segments interleaved with a plurality of second laterally straight surface segments.

[0145] Each lateral isolation trench fill structure (74, 76) may include a pair of longitudinal sidewalls extending generally along a first horizontal direction hd1. The vertical cross-sectional profile of the lateral isolation trench fill structure (74, 76) in a vertical plane perpendicular to the first horizontal direction hd1 has a variable width that increases with the vertical distance from the horizontal plane including the bottommost surface of the vertical alternating sequence (32, 42) in the lower portion of the vertical alternating sequence (32, 42) to the transition line 79I described above, and decreases with the vertical distance from the horizontal plane including the transition line 79I in the upper portion of the vertical alternating sequence (32, 42). In one embodiment, each lateral isolation trench fill structure (74, 76) has a width modulation along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and the width modulation varies with the lateral distance along the first horizontal direction hd1.

[0146] In one embodiment, each lateral isolation trench fill structure (74, 76) includes a periodic lateral alternating sequence of a neck portion (e.g., region) 78N having a minimum width along the second horizontal direction hd2 and a protruding portion (e.g., region) 78B having a maximum width along the second horizontal direction hd2. In Figure 20B the illustrated embodiment, the neck portion 78N includes horizontally linear (i.e., straight) sidewalls, and the protruding portion 78B includes horizontally convex sidewalls that protrude outward from the center of the lateral isolation trench fill structure (74, 76). In this embodiment, each lateral isolation trench fill structure (74, 76) includes a pair of laterally undulating longitudinal sidewalls that have lateral undulations at the protruding portion 78B; and each laterally undulating longitudinal sidewall in the protruding portion 78B includes a set of horizontally convex and vertically tapered surface segments that abut, at the edges, the horizontally linear and vertically tapered surface segments in the neck portion 78N. In one embodiment, each of the plurality of lateral protruding portions 78B has a pair of laterally convex surface segments that are laterally spaced apart from each other.

[0147] Each lateral isolation trench fill structure (74, 76) extends generally along a first horizontal direction hd1 through the vertical alternating sequence (32, 42). Each lateral isolation trench fill structure (74, 76) includes a plurality of neck portions 78N having a first width w1 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 between a respective pair of straight surface segments extending along the first horizontal direction hd1. Each lateral isolation trench fill structure (74, 76) further includes a plurality of lateral protrusions 78B having a variable width greater than the first width w1 along the second horizontal direction. The plurality of lateral protrusions 78B are staggered with the plurality of neck portions 78N along the first horizontal direction hd1. In one embodiment, the maximum value of the variable width may be a second width w2 at the middle of the lateral protrusion 78B.

[0148] In Figure 23B In one embodiment shown, the memory opening fill structures 58 may be arranged in rows extending laterally along the first horizontal direction hd1. The memory opening fill structures 58 within each row of the memory opening fill structures 58 may be arranged with a uniform pitch, which is referred to herein as a first pitch p1 along the first horizontal direction hd1. In one embodiment, the plurality of lateral protrusions 78B have a uniform pitch along the first horizontal direction hd1, which is referred to herein as a second pitch p2. The second pitch p2 may be the same as the first pitch p1 or may be greater than the first pitch p1. Each of the plurality of lateral protrusions 78B may be laterally defined along the second horizontal direction hd2 by a pair of laterally convex surface segments spaced laterally from each other.

[0149] In one embodiment, each of the laterally convex surface segments of the lateral protrusion 78B may have a respective pair of convex surfaces in a horizontal cross-sectional view. The plurality of lateral protrusions 78B are formed at least in the transition region 200 and may be formed in the memory array region 100 and / or the contact region 300. In one embodiment, a first subset of the lateral protrusions 78B may be located in the transition region 200, a second subset of the lateral protrusions 78B may be located in the memory array region 100, and a third subset of the lateral protrusions 78B may be located in the contact region 300.

[0150] The air gap 767 is formed due to the necking down of the second metal layer 766 at the top of the lateral isolation trench 79, which may have a narrowed width above the turning line 79I. If the air gap 767 is continuous along the entire length of the lateral isolation trench filling structure (74, 76) in the first horizontal direction hd1, such a continuous air gap 767 would structurally weaken the lateral isolation trench filling structure (74, 76). However, by forming the lateral isolation trench filling structure (74, 76) with lateral undulations (e.g., having alternating protruding portions and neck portions), the air gap is sealed at the interfaces between the lateral undulations.

[0151] As Figures 23C to 23E shown, discrete air gaps 767 may exist in the middle of the protruding portion 78B and the neck portion 78N. However, as Figure 23D shown, due to the lateral undulations in the lateral isolation trench filling structure (74, 76), the air gap 767 is sealed and does not continue through the interface region between the protruding portion 78B and the neck portion 78N. Thus, by making the air gap 767 discontinuous rather than continuous along the entire length of the lateral isolation trench filling structure (74, 76), the mechanical strength of the lateral isolation trench filling structure (74, 76) is improved.

[0152] Figures 24A to 24F is a top view of an alternative configuration of a first exemplary structure at the processing steps of Figure 23A and Figure 23E in accordance with an embodiment of the present disclosure. In the alternative configuration shown in Figures 24A to 24F , the lateral protruding portion 78B may be fully formed within the transition region 200. In this case, the portion of each lateral isolation trench filling structure (74, 76) having lateral width undulations is referred to as the width undulation region WUR.

[0153] Referring to Figure 24A , an illustration is provided in reference Figure 23A and Figure 23BA first alternative configuration of the first exemplary structure after the described processing steps. Each lateral isolation trench fill structure (74, 76) includes a plurality of neck portions 78N and a plurality of lateral protrusion portions 78B. The plurality of neck portions have a first width w1 along a second horizontal direction perpendicular to the first horizontal direction hd1, and the plurality of lateral protrusion portions have a variable width greater than the first width w1 along the second horizontal direction. The plurality of lateral protrusion portions 78B are staggered with the plurality of neck portions 78N along the first horizontal direction hd1. The plurality of lateral protrusion portions 78B and the neck portions 78N may be entirely formed within a transition region 200 located between a corresponding pair of straight surface segments 78S extending along the first horizontal direction hd1 in the memory array region 100 and the contact region 300. In this embodiment, the neck portions 78N may not include straight sidewalls and may be located at positions where the edges of adjacent protrusion portions 78B meet each other.

[0154] In one embodiment, the maximum value of the variable width is a second width w2. In the first alternative configuration, the entire portion of each lateral isolation trench fill structure (74, 76) located in the memory array region 100 may have a uniform array region width w_a less than the second width w2, and the entire portion of each lateral isolation trench fill structure (74, 76) located in the contact region 300 may have a uniform contact region width w_c less than the second width w2. In one embodiment, the uniform array region width w_a is not less than the first width w1; and the uniform contact region width w_c is not less than the first width w1. In one embodiment, the uniform array region width w_a and the uniform contact region width w_c may be the same as the first width w1 of the neck portions 78N. In one embodiment, the plurality of lateral protrusion portions in each lateral isolation trench fill structure (74, 76) have a uniform pitch along the first horizontal direction hd1, and the uniform pitch may be the same as the first pitch p1.

[0155] Reference Figure 24B , a second alternative configuration of the first exemplary structure can be obtained from the first alternative configuration of the first exemplary structure by selecting a value of the uniform array region width w_a greater than the first width w1, and / or by selecting a value of the uniform contact region width w_c greater than the first width w1.

[0156] Reference Figure 24C, a third alternative configuration of the first exemplary structure can be obtained from the first alternative configuration of the first exemplary structure by providing straight surface sections in each of the lateral protrusions 78B and each of the neck portions 78N. In this case, each of the plurality of lateral protrusions 78B includes a corresponding uniformly wide portion having a second width w2. Each of the plurality of lateral protrusions 78B includes four laterally convex surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0157] Reference Figure 24D , a fourth alternative configuration of the first exemplary structure can be obtained from the third alternative configuration of the first exemplary structure by providing a plurality of stepped increases in the variable width of the lateral protrusions 78B. In this case, each of the plurality of lateral protrusions 78B may include four sets of laterally convex surface sections, each set including two laterally convex surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0158] Reference Figure 24E , a fifth alternative configuration of the first exemplary structure can be obtained from the second alternative configuration of the first exemplary structure by providing straight surface sections in each of the lateral protrusions 78B and each of the neck portions 78N. In this case, each of the plurality of lateral protrusions 78B includes a corresponding uniformly wide portion having a second width w2. Each of the plurality of lateral protrusions includes four laterally convex surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0159] Reference Figure 24F , a sixth alternative configuration of the first exemplary structure can be obtained from the fifth alternative configuration of the first exemplary structure by providing a plurality of stepped increases in the variable width of the lateral protrusions 78B. In this case, each of the plurality of lateral protrusions 78B may include four sets of laterally convex surface sections, each set including two laterally convex surface sections that are laterally spaced apart from each other and do not directly contact each other.

[0160] Reference Figure 25A and Figure 25B, A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form openings over each of the memory opening fill structures in the memory opening fill structure 58 and over the horizontal extension surfaces of the stepped surfaces in the contact regions. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the stepped dielectric material portion 65. The drain contact via cavity can be formed through the contact-level dielectric layer 80 over the memory opening fill structure 58. The layer contact via cavity can be formed through the contact-level dielectric layer 80 and the stepped dielectric material portion 65 on the top surface of a corresponding one of the conductive layers in the conductive layer 46. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0161] At least one conductive material (such as a combination of a metal barrier material and a metal fill material) can be deposited in the drain contact via cavity and the layer contact via cavity. The excess portion of the at least one conductive material can be removed from a horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which can employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material filling the drain contact via cavity constitutes the drain contact via structure 88 on the top surface of a corresponding one of the drain regions in the contact drain region 63. The remaining portion of the at least one conductive material filling the layer contact via cavity constitutes the layer contact via structure 86 on the top surface of a corresponding one of the conductive layers contacting the conductive layer 46.

[0162] Reference Figure 26A and Figure 26B , The connection-level dielectric layer 90 can be formed over the contact-level dielectric layer 80. Connection via cavities can be formed through the connection-level dielectric layer 90 and can be filled with at least one conductive material (which can include at least one metal material) to form connection-level via structures (98, 96). The connection-level via structures (98, 96) include drain connection via structures 98 of corresponding ones of the drain contact via structures in the contact drain contact via structure 88, and layer connection via structures 96 of corresponding ones of the layer contact via structures in the layer contact via structure 86.

[0163] The bit-line-level dielectric layer 120 can be formed over the connection-level dielectric layer 90. Bit-line-level line cavities can be formed through the bit-line-level dielectric layer 120 and can be filled with at least one conductive material (which can include at least one metal material) to form bit-line-level metal lines (128, 126). The bit-line-level metal lines can include bit lines 128 extending laterally along a second horizontal direction hd2, and bit-line-level interconnect metal lines 126 (not shown separately) that can be used to provide electrical connection to the layer connection via structure 96.

[0164] Reference Figure 27, an additional dielectric material layer and an additional metal interconnect structure may be formed over the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structure may include a metal via structure, a metal line structure, and / or an integrated metal line and via structure. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as the memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer embedding bit lines 128, which are a subset of the memory-side metal interconnect structure 980.

[0165] A metal bonding pad (referred to herein as the memory-side bonding pad 988) may be formed at the topmost level of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, which includes an alternating stack of insulating layers 32 and conductive layers 46 and memory opening fill structures 58. Thus, a memory die 900 may be provided.

[0166] The memory-side dielectric material layer 960 is formed over the alternating stack (32, 46). The memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be embedded within the memory-side dielectric material layer 960, and specifically within the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0167] In one embodiment, the memory die 900 may include: a three-dimensional memory array including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a two-dimensional array of memory openings 49 that vertically extend through the alternating stack (32, 46); and a two-dimensional array of memory opening fill structures 58 located within the two-dimensional array of memory openings 49 and including corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two-dimensional array of drain contact via structures 88 electrically connected to a corresponding one of the vertical semiconductor channels in the vertical semiconductor channels 60; and a two-dimensional array of layer contact via structures 86 electrically connected to a corresponding one of the conductive layers in the conductive layers 46, a subset of the conductive layers serving as word lines of the three-dimensional memory array.

[0168] Typically, a memory die 900 is provided, which includes a memory array, a memory - side metal interconnect structure 980, and memory - side bond pads 988 embedded within a memory - side dielectric material layer 960. The memory die 900 includes a memory device, which may include a three - dimensional memory array comprising an alternating stack of an insulating layer 32 and a conductive layer 46, and further includes a two - dimensional array of NAND strings (e.g., memory opening fill structures 58) that vertically extend through the alternating stack (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two - dimensional array of NAND strings. In one embodiment, the memory - side metal interconnect structure 980 includes bit lines 128 of the two - dimensional array of NAND strings.

[0169] Reference Figure 28 Reference, a logic die 700 is provided. The logic die 700 includes peripheral circuits 720 formed on a logic - side substrate 709. According to one aspect of the present disclosure, the peripheral circuits 720 may be configured to control the operation of the memory array within the memory die 900. For example, the peripheral circuits 720 may include a word line driver region, a bit line driver region, a sense amplifier region, an input / output buffer, etc. A logic - side metal interconnect structure 780 embedded within a logic - side dielectric material layer 760 may be formed above the peripheral circuits 720. The logic die 700 includes logic - side bond pads 788 embedded within the logic - side dielectric material layer 760.

[0170] Reference Figure 29 Reference, a bonded component may be formed by bonding the logic die 700 to the memory die 900. The logic die 700 may be attached to the memory die 900, for example, by bonding the logic - side bond pads 788 to the memory - side bond pads 988. The bonding between the memory die 900 and the logic die 700 may be performed using a wafer - to - wafer bonding process (in which a two - dimensional array of the memory die 900 is bonded to a two - dimensional array of the logic die 700), by a die - to - bond process, or by a die - to - die bonding process. Each logic - side bond pad 788 within the logic die 700 may be bonded to a corresponding memory - side bond pad 988 within the memory die 900.

[0171] The logic die 700 may be attached to the memory die 900, for example, by bonding the logic - side bond pads 788 to the memory - side bond pads 988. The bonding between the memory die 900 and the logic die 700 may be performed using a wafer - to - wafer bonding process (in which a two - dimensional array of the memory die 900 is bonded to a two - dimensional array of the logic die 700), by a die - to - bond process, or by a die - to - die bonding process. Each logic - side bond pad 788 within the logic die 700 may be bonded to a corresponding memory - side bond pad 988 within the memory die 900.

[0172] Reference Figure 30 , the carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, isotropic etching processes, and / or anisotropic etching processes. If a polishing process such as chemical mechanical polishing is used to remove the carrier substrate 9. In this case, the stop insulation layer 106 can be used as a polishing stop material layer. If an etching process such as a wet etching process is used to remove the carrier substrate 9, then the stop insulation layer 106 can be subsequently used as an etching stop material layer.

[0173] Reference Figure 31 illustrates an alternative configuration of the first exemplary structure. The alternative configuration of the first exemplary structure can be provided by: forming a semiconductor device 620 on a semiconductor substrate 609, the semiconductor device including a peripheral circuit for controlling the operation of a three-dimensional memory device; forming a metal interconnect structure 680 embedded in a dielectric material layer 660 above the semiconductor device 620. In other words, a combination of the semiconductor substrate 609, the semiconductor device 620, the dielectric material layer 660, and the metal interconnect structure 680 can be used instead of the carrier substrate 9. The source electrode layer material 110' and the vertical alternating sequence (32, 42) can be formed above the dielectric material layer 660 during the process.

[0174] Reference Figure 32 , the processing steps described in Reference Figures 2 to 27 can be performed to provide a memory die, which can optionally be bonded to a logic die 700. In this case, memory-side bonding pads 988 can be present in the memory die. The semiconductor device 620 can include a first subset of the peripheral circuits for controlling the operation of the three-dimensional memory device, and the logic die 700 can include a second subset of the peripheral circuits for controlling the operation of the three-dimensional memory device. If the memory die 900 is not bonded to the logic die 700, then the memory-side bonding pads 988 can be omitted.

[0175] Referring to all of the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided that includes: a pair of alternating stacks (32, 46), where each alternating stack (32, 46) within the pair of alternating stacks (32, 46) includes an insulating layer 32 and a conductive layer 46 that are staggered along a vertical direction, and where the pair of alternating stacks (32, 46) are laterally spaced apart from each other by a lateral isolation trench 79 that extends laterally along a first horizontal direction hd1; a memory opening 49 that extends vertically through a corresponding one of the pair of alternating stacks (32, 46); a memory opening fill structure 58 that is located in a corresponding one of the memory openings 49 and includes: a corresponding vertical stack of memory elements (e.g., portions of a memory film 50) and a corresponding vertical semiconductor channel 60; and a lateral isolation trench fill structure (74, 76) that is located in the lateral isolation trench 79. The lateral isolation trench fill structure (74, 76) includes a plurality of neck portions 78N that have a pair of straight sidewalls extending along the first horizontal direction hd1 and have a first width w1 along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1; and a plurality of lateral protruding portions 78B that have a second width w2 that is greater than the first width w1 along the second horizontal direction hd2, where the plurality of lateral protruding portions 78B are staggered from the plurality of neck portions 78N along the first horizontal direction hd1.

[0176] In one embodiment, the memory opening fill structure 58 is located in a memory array region 100; a layer contact via structure 86 contacts a corresponding one of the conductive layers 46 and is located in a contact region 300 that is laterally offset from the memory array region 100 along the first horizontal direction hd1; and the plurality of lateral protruding portions are at least located in a transition region 200 that is located between the memory array region 100 and the contact region 300. In one embodiment, each memory opening fill structure in the memory opening fill structure 58 further includes a corresponding drain region 63 that is contacted by a corresponding drain contact via structure 88; and the transition region 200 and the contact region 300 do not have any drain contact via structures 88.

[0177] In one embodiment, a three-dimensional memory device includes: first type support pillar structures 20A, each of which extends vertically through a respective one of the pair of alternating stacks (32, 46), is located in the contact region 300, and is substantially composed of at least one dielectric material; and second type support pillar structures 20B, each of which extends vertically through a respective one of the pair of alternating stacks (32, 46), is located in the transition region 200, and includes a respective set of dielectric material layers and a respective semiconductor material layer. In one embodiment, each of the plurality of lateral protrusions 78B is positioned adjacent to a respective one of the second type support pillar structures 20B along the second horizontal direction hd2; a respective vertical stack of memory elements includes a portion of a respective memory film 50 at the level of the conductive layer 46; and the respective memory film 50 has the same set of materials as the respective set of dielectric material layers and has the same thickness as the respective set of dielectric material layers. In one embodiment, the vertical semiconductor channel 60 has the same material composition and the same thickness as the respective semiconductor material layer.

[0178] In one embodiment, the plurality of lateral protrusions 78B are located only in the transition region 200 and are not located in the memory array region 100 or the contact region 300. In this embodiment, the plurality of staggered lateral protrusions 78B and neck portions 78N are located between a respective pair of straight surface segments 78S that extend along the first horizontal direction hd1 in the memory array region 100 and the contact region 300. In another embodiment, the plurality of lateral protrusions are also located within the memory array region 100.

[0179] In one embodiment, the plurality of lateral protrusions 78B have a uniform pitch along the first horizontal direction hd1, and each of the plurality of lateral protrusions has a second width w2 that varies along the second horizontal direction hd2 and a pair of laterally convex surface segments that are laterally spaced apart from each other along the second horizontal direction hd2.

[0180] In one embodiment, each of the plurality of lateral protrusions 78B includes four laterally convex surface segments that are laterally spaced apart from each other and do not directly contact each other. In one embodiment, each of the plurality of lateral protrusions includes a respective uniform width portion having the second width w2.

[0181] In one embodiment, the lateral isolation trench fill structure (74, 76) includes an insulating spacer 74 and a conductive fill structure 76 laterally surrounded by the insulating spacer 74. In one embodiment, the conductive fill structure 76 includes a discrete air gap 767 located intermediate the lateral protrusion 78B and the neck portion 78N; and the discrete air gap 767 is enclosed and does not continue along a first horizontal direction hd1 through the interface region between the lateral protrusion 78B and the neck portion 78N.

[0182] In one embodiment, the insulating spacer 74 includes: a pair of outer longitudinal sidewalls each including a plurality of laterally convex surface segments interleaved with a plurality of first laterally straight surface segments; and a pair of inner longitudinal sidewalls each including a plurality of laterally concave surface segments interleaved with a plurality of second laterally straight surface segments.

[0183] Various embodiments of the present disclosure can be used to provide enhanced structural support by forming a lateral isolation trench 79 having a lateral protrusion 79B and by forming a conductive fill structure 76 having a portion without voids (i.e., air gaps) at the interface between the protrusion 78B and the neck portion 78N.

[0184] Reference Figure 33A and Figure 33B , a second exemplary structure according to a second embodiment of the present disclosure can be obtained from Figure 9A and Figure 9B by varying the pattern of the first type of support pillar structure 20A and optionally varying the size of each first type of support pillar structure 20A. In the second exemplary structure, the first type of support pillar structure 20A is formed in rows arranged along a first horizontal direction hd1. Accordingly, each row of the first type of support pillar structure 20A extends along the first horizontal direction hd1, and the rows of the first type of support pillar structure 20A are spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction. In one embodiment, the first type of support pillar structure 20A in each row can be periodically arranged along the first horizontal direction hd1 with a uniform pitch, which is referred to herein as the pillar-to-pillar pitch p_pp. The first type of support pillar structure 20A extends vertically through a vertical alternating sequence of a continuous insulating layer 32 and a continuous sacrificial material layer 42.

[0185] Typically, the region in which the first type of support pillar structure 20A is formed may be the same or substantially the same across the second exemplary structure and the first exemplary structure. In one embodiment, a row of the first type of support pillar structures 20A may be located between two strip-shaped regions in which a pair of adjacent lateral isolation trenches are subsequently formed. Such a row of the first type of support pillar structures 20A may be arranged as a rectangular array of the first type of support pillar structures 20A. In this case, the geometric center of the first type of support pillar structures 20A may be arranged as a rectangular array in a plan view.

[0186] Within a Cartesian coordinate system that employs a first axis parallel to the first horizontal direction hd1 and a second axis parallel to the second horizontal direction hd2 and represents each coordinate as a combination of a first component and a second component, the center of gravity of a two-dimensional array of the first type of support pillar structures 20A may be included within a set of first Euclidean planes EP1 that are laterally spaced from each other by an integer multiple of the pillar-to-pillar pitch p_pp. In this case, the first Euclidean plane EP1 that contains the position of the geometric center of the first type of support pillar structures 20A is represented by a first set of fixed values of the first component in the Cartesian coordinate system. In an illustrative example, if the (x, y, z) coordinate system employs an x-axis parallel to the first horizontal direction hd1 and a y-axis parallel to the second horizontal direction hd2, then the first Euclidean plane EP1 that contains the position of the geometric center of the first type of support pillar structures 20A is represented by a first set of fixed x values in the (x, y, z) coordinate system. In other words, each first Euclidean plane EP1 may be a set of all points having a corresponding fixed x coordinate value and thus is perpendicular to the first horizontal direction hd1. In this case, each fixed value within the first set of fixed values may be offset from each other by an integer multiple of the uniform pitch within each row of the first type of support pillar structures (i.e., the pillar-to-pillar pitch p_pp). The geometric centers of the first type of support pillar structures 20A within a row of the first type of support pillar structures 20A may be entirely located within the first Euclidean plane EP1.

[0187] In one embodiment, a row of the first type of support pillar structures 20A may consist of only one or more dielectric materials such as silicon oxide. The vertical alternating sequence (32, 42) includes a stepped region in which the lateral extent of the continuous sacrificial material layer 42 varies (e.g., decreases) along a first horizontal direction hd1 as a function of the vertical distance from a horizontal plane including the bottommost surface of the vertical alternating sequence (32, 42). The row of the first type of support pillar structures 20A is located in the stepped region of the vertical alternating sequence (32, 42). The maximum lateral dimension (such as diameter) of each of the first type of support pillar structures 20A may be in the range of 100 nm to 600 nm, although smaller and larger lateral dimensions may also be employed. In contrast, the maximum lateral dimension (such as diameter) of each of the memory opening fill structures 58 described in the first embodiment may be in the range of 100 nm to 300 nm, although smaller and larger lateral dimensions may also be employed. Thus, the maximum lateral dimension of the first type of support pillar structures 20A may be the same as or greater than the maximum lateral dimension of the memory opening fill structures 58.

[0188] Reference Figure 34A and Figure 34B , reference may be made to Figure 10A and Figure 10B for the processing steps described to form the contact-level dielectric layer 80 and to form the lateral isolation trenches 79. The lateral isolation trenches 79 are formed through the vertical alternating sequence of the continuous insulating layer 32 and the continuous sacrificial material layer 42 and divide the vertical alternating sequence into a plurality of alternating stacks of the insulating layer 32 and the sacrificial material layer 42 that are laterally spaced apart from each other along a second horizontal direction hd2. According to a second embodiment of the present disclosure, the pattern of the lateral isolation trenches 79 in the second exemplary structure is modified such that each lateral isolation trench 79 has a variable width along the second horizontal direction hd2 in a region between each pair of neighboring two-dimensional arrays of the first type of support pillar structures 20A. In this case, each lateral isolation trench 79 extends generally laterally along the first horizontal direction hd1 and has a variable width along the second horizontal direction hd2 in the contact region 300. According to one aspect of the second embodiment of the present disclosure, the variable width has a periodic undulation along the first horizontal direction hd1 that has the same periodicity as the uniform pitch (i.e., pillar-to-pillar pitch p_pp) of the first type of support pillar structures 20A.

[0189] In a second embodiment, at least one of the lateral isolation trenches 79 includes a respective plurality of lateral protruding portions 79B that are staggered along a first horizontal direction hd1 with the neck portions 79N and with the rows of the first type of support pillar structures 20A. Each of the neck portions 79N in the neck portion 79N abuts a respective pair of the lateral protruding portions 79B of the lateral isolation trench 79. Thus, at least one of the lateral isolation trenches 79 includes a respective plurality of lateral protruding portions 79B that are staggered along the first horizontal direction hd1 with the respective nearest side row in the rows of the first type of support pillar structures 20A. The plurality of lateral protruding portions 79B are laterally spaced apart along a second horizontal direction hd2 from the rows of the first type of support pillar structures 20A (such as the nearest side row of the first type of support pillar structures 20A). In other words, each of the neck portions 79N of the lateral isolation trench 79 is positioned along the second horizontal direction hd2 adjacent to a respective one of the first type of support pillar structures 20A in the nearest side row of the first type of support pillar structures 20A. In contrast, each of the lateral protruding portions 79B is positioned along the second horizontal direction hd2 adjacent to a space between a respective two of the first type of support pillar structures 20A in the nearest side row of the first type of support pillar structures 20A.

[0190] In a Cartesian coordinate system that employs a first axis parallel to the first horizontal direction hd1 and a second axis parallel to the second horizontal direction hd2 and represents each coordinate by a combination of a first component and a second component, a first Euclidean plane EP1 that contains the position of the geometric center of the nearest side row of the first type of support pillar structures 20A is represented by a first set of fixed values of the first component in the Cartesian coordinate system, a second Euclidean plane EP2 that contains the position of the maximum value of the variable width (i.e., the maximum value of the lateral protruding portions 79B) is represented by a second set of fixed values of the first component in the Cartesian coordinate system, and each fixed value within the second set of fixed values is offset from a fixed value within the first set of fixed values by a product of an odd number (e.g., one) and half of a uniform pitch, which uniform pitch is the pillar-to-pillar pitch p_pp. Thus, the first Euclidean plane EP1 may be located in the middle between a pair of neighboring second Euclidean planes EP2, and the second Euclidean plane EP2 may be located in the middle between a pair of neighboring first Euclidean planes EP1.

[0191] In the second embodiment, the rows of the first type of support pillar structures 20A may be arranged as a rectangular array of the first type of support pillar structures 20A that is aligned along the first horizontal direction hd1 and thus is laterally offset by the same lateral offset distance from the memory array region 100.

[0192] In a second embodiment, each of the plurality of neck portions 79N may have a uniform width, which is a first width w1, and each of the laterally protruding portions 79B may have a maximum width, which is a second width w2. The second width w2 may be greater than the first width w1. For example, the second width w2 may be greater than the first width w1 by a difference in the range of 50% to 150% (such as 75% to 125%) of the maximum lateral dimension (such as diameter) of at least one of the first type of support pillar structures 20A in the first type of support pillar structure 20A. In one embodiment, the second width w2 is greater than the first width w1 by more than the maximum lateral dimension (such as diameter) of at least one of the first type of support pillar structures 20A in the first type of support pillar structure 20A.

[0193] In one embodiment, for at least one of the lateral isolation trenches 79, each pair of adjacent first type of support pillar structures 20A in the nearest row of the first type of support pillar structures 20A may be laterally spaced from each other along a first horizontal direction hd1 by a pillar-to-pillar pitch s_pp. In one embodiment, the minimum distance s_pt between the nearest side row of the support pillar structure (such as the first type of support pillar structure 20A) and the lateral isolation trench 79 may be less than the pillar-to-pillar pitch s_pp. In one embodiment, for at least one of the lateral isolation trenches 79, the plurality of laterally protruding portions 79B are closer to the nearest side row of the first type of support pillar structure 20A than the plurality of neck regions 79N to the nearest side row of the first type of support pillar structure 20A. For example, each protruding portion 79B in the lateral isolation trench 79 is spaced from the two nearest first type of support pillar structures 20A in the nearest side row by a distance s_pt, while each neck portion 79N in the same lateral isolation trench 79 is spaced from the nearest first type of support pillar structure 20A in the nearest side row by a distance greater than s_pt.

[0194] In one embodiment, at least one of the lateral isolation trenches 79 always has a uniform width in the region located between the neighboring clusters of the memory opening filling structures 58, which are laterally spaced from each other by the respective lateral isolation trenches 79.

[0195] Reference Figure 35 may be executed with reference to Figure 12 and Figure 13The described processing steps replace the optional lower sacrificial liner 103, the source-level sacrificial layer 104, the optional upper sacrificial liner 105, and a surface portion of the memory film 50 with the source contact layer 114. The source-level material layer 110 may be formed under an alternating stack of the insulating layer 32 and the sacrificial material layer 42. Optionally, a dielectric surface conversion process (such as an oxidation process or a nitridation process) may be performed to convert a surface portion of the source-level material layer 110 physically exposed from under each lateral isolation trench 79 to form a trench bottom dielectric liner 129.

[0196] Reference Figure 36 , the sacrificial material layer 42 may be replaced with the conductive layer 46. An alternating stack of the insulating layer 32 and the conductive layer 46 may be formed. The alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 is separated from each other along the second horizontal direction hd2 by the lateral isolation trenches 79.

[0197] Reference Figure 37A and Figure 37B , the reference Figure 17A and Figure 17E described processing steps may be performed to form an insulating spacer 74 in the peripheral region of the lateral isolation trench 79.

[0198] Reference Figure 38A and Figure 38B , the reference Figure 18A and Figure 23E described processing steps may be performed to form a conductive filling structure 76. Each conductive filling structure 76 may include the same set of components as described with reference to the first exemplary structure. Each consecutive combination of the insulating spacer 74 and the conductive filling structure fills a corresponding lateral isolation trench 79 and constitutes a lateral isolation trench filling structure (74, 76).

[0199] The second exemplary structure includes a three-dimensional memory device. The three-dimensional memory device includes: a pair of alternating stacks (32, 46), where each alternating stack (32, 46) within the pair of alternating stacks (32, 46) includes an insulating layer 32 and a conductive layer 46 that are staggered along a vertical direction, and where the pair of alternating stacks (32, 46) are laterally spaced apart from each other by a lateral isolation trench 79 that extends laterally along a first horizontal direction hd1; a memory opening 49 that extends vertically through a corresponding one of the pair of alternating stacks (32, 46); a memory opening fill structure 58 that is located in a corresponding one of the memory openings 49 and includes a corresponding vertical stack of memory elements (which may include a portion of the memory material layer 54 that is at the level of the conductive layer 46), a corresponding vertical semiconductor channel 60, and a corresponding vertical stack of memory elements; a row of support pillar structures (such as a first type of support pillar structure 20A), where each row of support pillar structures extends laterally along the first horizontal direction hd1 and vertically through a corresponding one of the pair of alternating stacks (32, 46); and a lateral isolation trench fill structure (74, 76) that has a variable width along a second horizontal direction hd2 and is located in the lateral isolation trench 79, the lateral isolation trench fill structure including: a plurality of neck portions 78N that have a pair of straight sidewalls that extend along the first horizontal direction hd1 and have a first width w1 along a second horizontal direction hd2 that is perpendicular to the first horizontal direction; and a plurality of lateral protruding portions 78B that have a second width w2 that is greater than the first width w1 along the second horizontal direction hd2, where the plurality of lateral protruding portions 78B are staggered from the plurality of neck portions 78B along the first horizontal direction hd1.

[0200] In one embodiment, each row of support pillar structures (such as a first type of support pillar structure 20A) extends along the first horizontal direction hd1 with a uniform pitch p_pp; and the variable width of the lateral isolation trench fill structure (74, 76) has a periodic undulation along the first horizontal direction hd1 that has the same periodicity as the uniform pitch p_pp.

[0201] In one embodiment, the lateral isolation trench fill structure (74, 76) is laterally spaced apart from the nearest row in the row of support pillar structures (such as a first type of support pillar structure 20A) along the second horizontal direction hd2.

[0202] In one embodiment, within a Cartesian coordinate system that employs a first axis parallel to a first horizontal direction hd1 and a second axis parallel to a second horizontal direction hd2 and represents each coordinate as a combination of a first component and a second component, a first Euclidean plane EP1 that contains the position of the geometric center of the nearest row of support pillar structures (such as the first type of support pillar structure 20A) is represented by a first set of fixed values of the first component in the Cartesian coordinate system, a second Euclidean plane EP2 that contains the position of the maximum value of the variable width is represented by a second set of fixed values of the first component in the Cartesian coordinate system, and each fixed value within the second set of fixed values is offset from the fixed values within the first set of fixed values by a product of an odd number and half of the uniform pitch p_pp. In one embodiment, the geometric centers of the support pillar structures (such as the first type of support pillar structure 20A) within a row of support pillar structures (such as the first type of support pillar structure 20A) are entirely located within the first Euclidean plane EP1.

[0203] In one embodiment, each of the plurality of neck portions has a uniform width, which is a first width w1; and each of the lateral protrusion portions has a maximum width, which is a second width w2. In one embodiment, the second width w2 is greater than the first width w1 by a certain difference, and this difference is in the range of 50% to 150% of the maximum lateral dimension (such as the diameter) of one of the support pillar structures (such as the first type of support pillar structure 20A).

[0204] In one embodiment, each pair of adjacent support pillar structures (such as the first type of support pillar structure 20A) within the nearest row of support pillar structures (such as the first type of support pillar structure 20A) are laterally spaced from each other along the first horizontal direction hd1 by a pillar-to-pillar pitch s_pp; and the minimum distance between the nearest row of support pillar structures (such as the first type of support pillar structure 20A) and the lateral isolation trench fill structures (74, 76) is less than the pillar-to-pillar pitch s_pp. In one embodiment, the plurality of lateral protrusion portions 78B are closer to the nearest row of support pillar structures (such as the first type of support pillar structure 20A) than the plurality of neck regions 78N to the nearest row of support pillar structures (such as the first type of support pillar structure 20A).

[0205] In one embodiment, each of the plurality of protrusion portions 78B protrudes into the space between two adjacent support pillar structures 20A in the nearest row of support pillar structures along the second horizontal direction hd2. In one embodiment, the plurality of lateral protrusion portions 78B are closer to the nearest row of support pillar structures 20A than the plurality of neck regions 78N to the nearest row of support pillar structures 20A.

[0206] In one embodiment, the rows of support post structures (such as the first type support post structures 20A) contain only one or more dielectric materials. In one embodiment, the rows of support post structures (such as the first type support post structures 20A) are arranged as two rectangular arrays of support post structures (such as the first type support post structures 20A) located within corresponding alternating stacks (32, 46) in the pair of alternating stacks (32, 46).

[0207] In one embodiment, each of the pair of alternating stacks (32, 46) includes a corresponding stepped region in which the lateral extent of the conductive layer 46 within each of the alternating stacks (32, 46) along the first horizontal direction hd1 varies with the vertical distance from a horizontal plane including the bottommost surface of the pair of alternating stacks (32, 46); and a row of support post structures (such as the first type support post structures 20A) are located in the stepped region of the pair of alternating stacks (32, 46). In one embodiment, the lateral isolation trench filling structure (74, 76) has a uniform width throughout the region between a first subset of memory opening filling structures 58 of a first alternating stack (32, 46) extending vertically through the pair of alternating stacks (32, 46) and a second subset of memory opening filling structures 58 of a second alternating stack (32, 46) extending vertically through the pair of alternating stacks (32, 46).

[0208] refer to Figure 39A and Figure 39B , executable reference Figure 25A and Figure 25B The processing steps described are to form various contact via structures (88, 86). In this case, the contact-level dielectric layer 80 overlies the alternating stack (32, 46) and includes a plurality of portions laterally separated by lateral isolation trenches 79. The drain contact via structure 88 extends vertically through the contact-level dielectric layer 80 and contacts the top surface of a corresponding one of the memory opening fill structures 58. All top surfaces of the support post structures (such as the first type support post structure 20A) contact the bottom surface of the contact-level dielectric layer 80.

[0209] Then, you can execute the reference Figures 26A to 30 The processing steps described are used to form a bonded assembly of memory die 900 and logic die 700. Alternatively, Figure 31 and Figure 32 The illustrated configuration can be compared with the reference Figures 33A to 39A The described modifications are taken together to provide an alternative embodiment of the second exemplary structure.

[0210] In the second embodiment of the second exemplary structure, the lateral protrusion 78B of the lateral isolation trench filling structure (74, 76) can reduce the mechanical deformation of the three-dimensional memory array in the contact region 300. Specifically, the protrusion 78B protrudes into the space between two adjacent first-type support pillar structures 20A in the nearest row along the second horizontal direction hd2. This reduces the distance between the lateral isolation trench filling structure (74, 76) and the nearest first-type support pillar structure 20A in the nearest row. This reduces the deflection of the alternating stacks (32, 46) along the second horizontal direction hd2 and the tilting of the alternating stacks into the lateral isolation trench 79 during manufacturing. Therefore, the mechanical stability and reliability of the three-dimensional memory array can be enhanced.

[0211] Reference Figure 40A and Figure 40B , a third exemplary structure according to an embodiment of the present disclosure can be derived from Figure 3A and Figure 3B the first exemplary structure illustrated by forming a combination of the first-type support openings 19A and the third-type support openings 19C in the contact region 300. The first-type support openings 19A of the third exemplary structure are formed in a region that does not have any area overlap with the subsequently formed lateral isolation trenches, and the third-type support openings 19C are formed in a region that has an area overlap with the subsequently formed lateral isolation trenches.

[0212] Each of the first-type support openings 19A in the first-type support openings 19A may have a corresponding circular or elliptical horizontal cross-sectional shape. Each of the second-type support openings 19B formed in the transition region 200 may have a corresponding circular or elliptical horizontal cross-sectional shape. Each of the third-type support openings 19C in the third-type support openings 19C may have a corresponding circular or elliptical horizontal cross-sectional shape.

[0213] In Figure 40B one embodiment shown, the first-type support openings 19A may be formed as a plurality of rows extending laterally along the first horizontal direction hd1. In one embodiment, the first-type support openings 19A within each row of the first-type support openings 19A may be arranged in a first periodic pattern along the first horizontal direction hd1. The first periodicity of the first-type support openings 19A within each row corresponds to the center-to-center distance between the geometric centers of a pair of adjacent first-type support openings 19A and is referred to herein as the first center-to-center pitch pcc1.

[0214] The plurality of rows of the first-type support openings 19A may be spaced apart from each other along the second horizontal direction hd2. In one embodiment, the groups of rows of the first-type support openings 19A may be arranged as a two-dimensional periodic array of the first-type support openings 19A, such as a rectangular periodic array.

[0215] In one embodiment, the third type of support opening 19C may be formed as rows that also extend laterally along the first horizontal direction hd1. Each row of the third type of support opening 19C may surround an area in which a lateral isolation trench is to be subsequently formed. In one embodiment, each row of the third type of support opening 19C may be formed between a pair of adjacent rectangular arrays of the first type of support opening 19A. In one embodiment, the third type of support opening 19C within each row of the third type of support opening 19C may be arranged in a second periodicity along the first horizontal direction hd1. The second periodicity of the third type of support opening 19C within each row corresponds to the center-to-center distance between the geometric centers of a pair of adjacent third type of support openings 19C and is referred to herein as the second center-to-center pitch pcc2.

[0216] In one embodiment, the horizontal cross-sectional shape of each third type of support opening 19C may be a circular shape with a uniform radius of curvature that is equal to the radius of the circular shape. In one embodiment, each first type of support opening 19A may have a first maximum lateral dimension (such as a diameter) in a horizontal cross-sectional view, and the radius of curvature of each third type of support opening 19C may be in the range of 50% to 200% (such as 75% to 150%) of half of the first maximum lateral dimension. In one embodiment, the radius of curvature of each third type of support opening 19C may be the same as half of the first maximum lateral dimension.

[0217] In one embodiment, each row of the first type of support opening 19A may have a first center-to-center pitch pcc1 along the first horizontal direction hd1, and each row of the third type of support opening 19C may have a second center-to-center pitch pcc2 along the first horizontal direction hd1 that is equal to the first center-to-center pitch pcc1. In one embodiment, each row of the third type of support opening 19C may be laterally offset from the nearest row of the first type of support opening 19A by half of the second center-to-center pitch pcc2, which is equal to the first center-to-center pitch pcc1. In one embodiment, the center of gravity of one of the third type of support openings 19C may be laterally offset from the center of gravity of the nearest first type of opening 19A of the first type of support opening 19A by a lateral offset distance equal to half of the first center-to-center pitch pcc1, and half of the first center-to-center pitch is equal to half of the second center-to-center pitch pcc2. As used herein, the center of gravity of a volume refers to the center of gravity of a hypothetical object that fills the volume and always has a uniform density. The center of gravity of a volume has a set of Cartesian coordinates that are the average of all the Cartesian coordinates of the volume.

[0218] In one embodiment, each pair of adjacent first type support openings 19A that are laterally spaced apart from each other along the first horizontal direction hd1 may be spaced apart from each other by a first spacing s1. Each pair of adjacent first type support openings 19A that are laterally spaced apart from each other along the second horizontal direction hd2 may be spaced apart from each other by a second spacing s2. Multiple pairs of adjacent first type support openings 19A and third type support openings 19C may be spaced apart from each other by a third spacing s3. The first spacing s1 may be in the range of 20nm to 300nm (such as 40nm to 150nm), but smaller and larger spacings may also be used. The ratio of the second spacing s2 to the first spacing s1 may be in the range of 0.5 to 2.0 (such as 0.75 to 1.5), but smaller and larger ratios may also be used. The ratio of the third spacing s3 to the first spacing s1 may be in the range of 0.5 to 2.0 (such as 0.75 to 1.5), but smaller and larger ratios may also be used.

[0219] refer to Figure 41A and Figure 41B , executable reference Figure 4 The processing steps are described to deposit a sacrificial fill material, such as amorphous carbon or diamond-like carbon, in the memory openings 49 and the support openings 19. Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T by a planarization process such as a recess etching process or a chemical mechanical polishing process. The remaining portions of the sacrificial fill material filling the memory openings 49 constitute sacrificial memory opening filling structures 47. The remaining portions of the sacrificial fill material filling the first type support openings 19A constitute the first type sacrificial support opening filling structures 17A. The remaining portions of the sacrificial fill material filling the second type support openings 19B constitute the second type sacrificial support opening filling structures 17B. The remaining portions of the sacrificial fill material filling the third type support openings 19C constitute the third type sacrificial support opening filling structures 17C, as shown in FIG. Figure 41B shown.

[0220] refer to Figure 42, a hard mask layer 21 may be applied over the third exemplary structure and may be lithographically patterned to cover the memory array region 100 and the transition region 200 without covering the contact region 300. The hard mask layer 21 may include a dielectric material such as silicon oxide or silicon nitride and may have a thickness in the range of 10 nm to 50 nm, although smaller and larger thicknesses may also be employed. The first type of sacrificial support opening filling structures 17A and the third type of sacrificial support opening filling structures 17C may be selectively removed relative to the hard mask layer 21, the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), and the material of the in-process source electrode level material layer 110' by performing a selective removal process such as an ashing process to reopen the first type of support opening 19A and the third type of support opening 19C. A cavity is formed in the volume of the first type of support opening 19A and the third type of support opening 19C.

[0221] Reference Figure 43A and Figure 43B , a dielectric filling material such as silicon oxide may be deposited in the first type of support opening 19A and the third type of support opening 19C. The excess of the dielectric filling material and the hard mask layer above the horizontal plane covering the top surface of the stepped dielectric material portion 65 may be removed by a planarization process such as a recess etching process or a chemical mechanical polishing process. The remaining portion of the dielectric filling material filling the first type of support opening 19A constitutes the first type of support pillar structure 20A. The remaining portion of the dielectric filling material filling the third type of support opening 19C constitutes the third type of support pillar structure 20C, as Figure 43B shown. The first type of support pillar structure 20A and the third type of support pillar structure 20C extend vertically through the vertical alternating sequence (32, 42) in the contact region 300. In one embodiment, the first type of support pillar structure 20A and the third type of support pillar structure 20C are substantially composed of at least one dielectric material (such as silicon oxide).

[0222] Each of the first type of support pillar structure 20A and the third type of support pillar structure 20C has a corresponding circular or elliptical horizontal cross-sectional shape. In one embodiment, each horizontal cross-sectional shape of the first type of support pillar structure 20A and the third type of support pillar structure 20C may have a uniform radius of curvature equal to the radius of the corresponding horizontal cross-sectional shape. In one embodiment, each of the first type of support pillar structures in the first type of support pillar structure 20A may have a first maximum lateral dimension in a horizontal cross-sectional view. In one embodiment, each radius of curvature of the first type of support pillar structure 20A and the third type of support pillar structure 20C may be in the range of 50% to 200% of half of the first maximum lateral dimension.

[0223] In one embodiment, the first type of support pillar structure 20A can be arranged in multiple rows extending laterally along a first horizontal direction hd1, and the third type of support pillar structure 20C can be arranged in a row extending laterally along the first horizontal direction hd1. In one embodiment, the first type of support pillar structure 20A can be arranged in a rectangular periodic array, and the third type of support pillar structure 20C can be arranged in a row located between a pair of corresponding neighboring rectangular periodic arrays of the first type of support pillar structure 20A. In one embodiment, each row of the first type of support pillar structure 20A has a first center-to-center pitch pcc1 along the first horizontal direction hd1, and each row of the third type of support pillar structure 20C has a second center-to-center pitch pcc2 equal to the first center-to-center pitch pcc1 along the first horizontal direction hd1.

[0224] In one embodiment, the center of gravity of one of the third type of support pillar structures in the third type of support pillar structure 20C can be laterally offset from the center of gravity of the nearest first type of support pillar structure 20A in the first type of support pillar structure 20A by a lateral offset distance equal to half of the first center-to-center pitch pcc1.

[0225] Reference Figure 44A and Figure 44B , the sacrificial memory opening fill structure 47 and the second type of sacrificial support opening fill structure 17B can be selectively removed relative to the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), the first type of support pillar structure 20A, the third type of support pillar structure 20C, and the in-process source electrode level material layer 110' by performing a selective removal process such as an ashing process. A cavity is formed in the volume of the memory opening 49 and the second type of support opening 19B.

[0226] See Figures 45A to 45B , the processing steps described with reference to Figures 8A to 8D can be performed to form a memory opening fill structure 58 in the memory opening 49 and a second type of support pillar structure 20B in the second type of support opening 19B. In one embodiment, each memory opening fill structure in the memory opening fill structure 58 includes a memory film 50 and a vertical semiconductor channel 60. In one embodiment, the memory film 50 includes a layer stack of a barrier dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56, and the portion of the charge storage layer 54 at the level of the sacrificial material layer 42 includes a vertical stack of memory elements.

[0227] Reference Figure 45C, in a first alternative configuration of the third exemplary structure, the third type of support pillar structure 20C is elongated along the second horizontal direction hd2. In this configuration, the third type of support pillar structure 20C may have an oval (e.g., elliptical) horizontal cross-sectional shape.

[0228] Reference Figure 45D , in a second alternative configuration of the third exemplary structure, the third type of support pillar structure 20C is arranged in two rows extending along the second horizontal direction hd2. In this configuration, the third type of support pillar structure 20C may have a circular horizontal cross-sectional shape.

[0229] Reference Figures 46A to 46C , a dielectric material such as undoped silicate glass or doped silicate glass may be deposited over the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 may be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses may also be employed.

[0230] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form various openings therein. The openings in the photoresist layer include elongated laterally undulating openings that extend generally along the first horizontal direction hd1 in a strip region between the clusters adjacent to the memory opening fill structure 58.

[0231] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), and the stepped dielectric material portion 65 and into the in-process source-level material layer 110' (if present). Lateral isolation trenches 79 may be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the in-process source-level material layer 110' (if present). The lateral isolation trenches 79 extend vertically through each layer within the alternating stack (32, 42) and into the upper portion of the semiconductor material layer (which may be located in the in-process source-level material layer 110' or, if the in-process source-level material layer 110' is omitted, may include the top portion of the carrier substrate 9). The lateral isolation trenches 79 extend laterally along the first horizontal direction hd1 (e.g., the word line direction). In one embodiment, the lower source-level semiconductor layer 112 may be physically exposed under each lateral isolation trench 79.

[0232] In one embodiment, each lateral isolation trench 79 may have a uniform width along a second horizontal direction hd2. The uniform width is less than the lateral dimension of each third type of support pillar structure 20C. Each row of the third type of support pillar structure 20C may be cut by a corresponding lateral isolation trench 79 into a corresponding pair of rows of the remaining dielectric material of the third type of support pillar structure 20C. The lateral isolation trench 79 may be formed through the inverse stepped dielectric material portion 65 and the alternating stack (32, 42) and through the rows of the third type of support pillar structure 20C, while the first type of support pillar structure 20A is not etched or cut during the formation of the lateral isolation trench 79. Thus, the first type of support pillar structure 20A does not change during the formation of the lateral isolation trench 79.

[0233] Each remaining portion of the third type of support pillar structure 20C is referred to herein as an auxiliary support pillar structure 20P. In one embodiment, the first type of support pillar structure 20A is arranged as a plurality of rows extending laterally along a first horizontal direction hd1. In one embodiment, each row of the third type of support pillar structure 20C may be arranged along the first horizontal direction hd1. In one embodiment, each third type of support pillar structure 20C within a row of the third type of support pillar structure 20C includes a corresponding central portion that is etched through during the formation of the lateral isolation trench 79, and a corresponding pair of outer portions remaining after the formation of the lateral isolation trench 79 constitutes a corresponding pair of auxiliary support pillar structures 20P.

[0234] In Figure 46C In one embodiment shown, each auxiliary support pillar structure 20P may have a horizontal cross-sectional shape of a sector of a circle or an ellipse, and may have a planar vertically extending surface 20S exposed to the corresponding lateral isolation trench 79. As used herein, "sector" refers to a cut portion of a circle or an ellipse. In one embodiment, each row of the first type of support pillar structure 20A has a first center-to-center pitch pcc1 along the first horizontal direction hd1. In one embodiment, each row of the auxiliary support pillar structure 20P may have a second center-to-center pitch pcc2 equal to the first center-to-center pitch pcc1 along the first horizontal direction hd1. In one embodiment, the center of gravity of the support pillar structures 20 within a row of the support pillar structures 20 is laterally offset from the center of gravity of the nearest first type of support pillar structure in the first type of support pillar structure 20A by half of the first center-to-center pitch pcc1 along the first horizontal direction hd1.

[0235] In one embodiment, each first type support pillar structure in the first type support pillar structure 20A has a corresponding circular or elliptical horizontal cross-sectional shape. In one embodiment, each auxiliary support pillar structure in the auxiliary support pillar structure 20P may have a corresponding horizontal cross-sectional shape of a circular or elliptical sector. In addition, each auxiliary support pillar structure in the auxiliary support pillar structure 20P may have a planar vertical extension surface 20S that is exposed to the corresponding lateral isolation trench 79 when the lateral isolation trench 79 is formed. In one embodiment, the curved portion of the horizontal cross-sectional shape of the sector may have a radius of curvature greater than half the width of each lateral isolation trench 79. In one embodiment, the first type support pillar structure 20A may have a first maximum lateral dimension in a horizontal cross-sectional view, and the radius of curvature is in the range of 50% to 200% of half of the first maximum lateral dimension.

[0236] In one embodiment, the first type support pillar structures 20A may be arranged in a plurality of rows extending laterally along a first horizontal direction hd1, and the auxiliary support pillar structures 20P may be arranged in two rows extending laterally along the first horizontal direction hd1. In one embodiment, the two rows of the auxiliary support pillar structures 20P are laterally spaced from each other by a lateral spacing equal to the width of the lateral isolation trench 79.

[0237] In one embodiment, the two rows of the auxiliary support pillar structures 20P may be formed around each lateral isolation trench 79. In one embodiment, the two rows of the auxiliary support pillar structures 20P include a first row and a second row. In one embodiment, the center of curvature of the curved sidewall of the auxiliary support pillar structure 20P within the first row is located within a vertical line passing through the lateral isolation trench 79, and the center of curvature of the curved sidewall of another auxiliary support pillar structure 20P within the second row is located within this vertical line. The two auxiliary support pillar structures 20P sharing the same vertical line with the center of curvature of the curved sidewall may be the remaining parts of the same third type support pillar structure 20C.

[0238] If the third type support pillar structures 20C are arranged in the first configuration or the second configuration as shown respectively Figure 45C or Figure 45D then the lateral isolation trench 79 may be wider along a second horizontal direction hd2 than the Figure 45B and Figure 46B configurations shown. The wider lateral isolation trench 79 still divides the third type support pillar structure 20C, which is elongated or arranged in two rows in the first configuration or the second configuration as shown Figure 45C or Figure 45D Therefore, if the third type support pillar structures 20C are in Figure 45C or Figure 45Darranged in the first configuration or the second configuration as shown, and if two rows of the auxiliary support pillar structure 20P are formed around each lateral isolation trench 79 in the first configuration or the second configuration, a structure that is the same as or similar to the Figure 46C structure shown is still formed.

[0239] If the third type of support pillar structure 20C is arranged in the Figure 45D second configuration as shown, a lateral isolation trench 79 is formed through the inverse stepped dielectric material portion 65, through the alternating stack (32, 46), and through the first row and the second row of the third type of support pillar structure 20C to cut each third type of support pillar structure in the first row and the second row into a corresponding pair of auxiliary support pillar structures 20P. Each auxiliary support pillar structure in the pair of auxiliary support pillar structures 20P has a horizontal cross-sectional shape of a circular or elliptical sector and has a planar vertical extension surface 20S in the opposite sidewalls of the lateral isolation trench 79 facing each other.

[0240] Referring to Figure 47 , the processing steps described in Figure 12 can be performed to form the source cavity 109.

[0241] Referring to Figure 48 , the processing steps described in Figure 13 can be performed to form the source contact layer 114. Optionally, a dielectric surface conversion process (such as an oxidation process or a nitridation process) can be performed to convert the surface portion of the source level material layer 110 physically exposed from under each lateral isolation trench 79 to form the trench bottom dielectric liner 129.

[0242] Referring to Figure 49A and Figure 49B , the processing steps described in Figure 14 and Figure 15A can be performed to form the laterally extending cavity 43.

[0243] Referring to Figure 50 , the processing steps described in Figures 15B to 15D and Figure 16The described processing steps form a conductive layer 46 within a laterally extending cavity 43. A first alternating stack (32, 46) of an insulating layer 32 and the conductive layer 46 and a second alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 can be formed around each laterally isolating trench 79. The first alternating stack (32, 46) includes a first stepped surface that includes a first horizontally extending surface section and a first vertically extending surface section that are adjacent to each other. The second alternating stack (32, 46) includes a second stepped surface that includes a second horizontally extending surface section and a second vertically extending surface section that are adjacent to each other. Each of the first type support pillar structures 20A and the auxiliary support pillar structures 20P extends vertically through the stepped surfaces of the respective alternating stacks (32, 46).

[0244] Reference Figure 51A and Figure 51B , an insulating material can be conformally deposited in the laterally isolating trench 79 and can be anisotropically etched to form insulating spacers 74 in the peripheral portion of the laterally isolating trench 79. The insulating spacers 74 include a dielectric material such as undoped silicate glass or doped silicate glass.

[0245] At least one metal material can be conformally deposited in the remaining volume of the laterally isolating trench 79 on the physically exposed surfaces of the insulating spacers 74, the source level material layer 110, and the contact level dielectric layer 80. The at least one metal material can include at least one metal nitride barrier material and at least one metal filling material. The excess portion of the at least one metal material can be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80. Each remaining portion of the at least one metal material located within the respective laterally isolating trench 79 constitutes a conductive filling structure 76. Each adjacent combination of the insulating spacers 74 and the conductive filling structures 76 constitutes a laterally isolating trench filling structure (74, 76).

[0246] Reference Figure 52A and Figure 52B , a photoresist layer (not shown) can be applied above the contact level dielectric layer 80 and can be lithographically patterned to form openings above each memory opening filling structure in the memory opening filling structure 58 and above the horizontally extending surfaces of the stepped surfaces in the contact region. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact level dielectric layer 80 and the stepped dielectric material portion 65. Drain contact vias can be formed through the contact level dielectric layer 80 above the memory opening filling structure 58. Layer contact vias can be formed through the contact level dielectric layer 80 and the stepped dielectric material portion 65 on the top surface of a respective one of the conductive layers in the conductive layer 46. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0247] At least one conductive material (such as a combination of a metal barrier material and a metal fill material) may be deposited in the drain contact via cavity and the layer contact via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material filling the drain contact via cavity constitutes a drain contact via structure 88 contacting the top surface of a corresponding one of the drain regions 63. The remaining portion of the at least one conductive material filling the layer contact via cavity constitutes a layer contact via structure 86 contacting the top surface of a corresponding one of the conductive layers 46.

[0248] refer to Figure 53A and Figure 53B , executable reference Figure 26A and Figure 26B The processing steps are described to form the connection level dielectric layer 90, the connection level via structure (98, 96), the bit line level dielectric layer 120 and the bit line level metal line (128, 126). The bit line level metal line may include a bit line 128 extending laterally along the second horizontal direction hd2, and a bit line level interconnect metal line 126 that can be used to provide an electrical connection with the layer connection via structure 96.

[0249] refer to Figure 54 , executable reference Figure 27 The described processing steps are to form additional dielectric material layers and additional metal interconnect structures. A memory die 900 is provided, which includes a memory array, a memory side metal interconnect structure 980, and a memory side bonding pad 988 embedded in the memory side dielectric material layer 960. The memory die 900 includes a memory device, which may include a three-dimensional memory array including an alternating stack of insulating layers 32 and conductive layers 46, and further includes a two-dimensional array of NAND strings (e.g., memory opening filling structures 58) extending vertically through the alternating stacks (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two-dimensional array of NAND strings. In one embodiment, the memory side metal interconnect structure 980 includes bit lines 128 of the two-dimensional array of NAND strings.

[0250] refer to Figure 55 , which can provide reference Figure 28 The described logic die 700. The executable reference Figure 29 The processing steps are described to form a bonded assembly of memory die 900 and logic die 700. Logic die 700 includes peripheral circuitry configured to control the operation of conductive layer 46 and the vertical stack of memory elements.

[0251] refer to Figure 56, the carrier substrate 9 may be removed, for example, by grinding, polishing, cleaving, an isotropic etching process and / or an anisotropic etching process. If a polishing process such as a chemical mechanical polishing process is used to remove the carrier substrate 9. If an etching process such as a wet etching process is used to remove the carrier substrate 9, the blocking insulating layer 106 may then be used as an etching stop material layer. One or more source contact structures 6 may be formed on the backside surface of the source level material layer 110 through the blocking insulating layer 106.

[0252] Figure 57A and Figure 57B As mentioned above about Figure 15B After forming the outer blocking dielectric layer 44, Figure 49B 8 is a vertical cross-sectional view of an alternative configuration of the third exemplary structure of the corresponding vertical planes A-A' and B-B' in FIG. However, in this embodiment, since the planar vertical extension surface 20S of the auxiliary support column structure 20P is exposed in the sidewall of the lateral isolation trench 79, the external blocking dielectric layer 44 is also formed on the planar vertical extension surface 20S of the auxiliary support column structure 20P exposed in the sidewall of the lateral isolation trench 79.

[0253] Figure 58A and Figure 58B As mentioned above about Figure 15C and Figure 15D The conductive layer 46 is deposited along the Figure 49B Vertical cross-sectional views of an alternative configuration of the third exemplary structure along corresponding vertical planes AA′ and BB′ in FIG.

[0254] Figure 59A and Figure 59B As mentioned above about Figure 16 After removing the conductive layer 46 from the lateral isolation trench 79, the conductive layer 46 is removed along the Figure 49B 4 is a vertical cross-sectional view of an alternative configuration of the third exemplary structure of the corresponding vertical planes A-A' and BB' in FIG. However, in this embodiment, the external blocking dielectric layer 44 may remain on the planar vertically extending surface 20S of the auxiliary support column structure 20P exposed in the sidewall of the lateral isolation trench 79. In one embodiment, the conductive layer 46 may be laterally recessed relative to the insulating layer 32, which forms the sidewall of the lateral isolation trench 79 and the planar vertically extending surface 20S of the auxiliary support column structure 20P exposed in the sidewall of the lateral isolation trench 79. The lateral recess 46R may be formed in the sidewall of the lateral isolation trench 79 at the level of the conductive layer 46.

[0255] Figure 60A and Figure 60B As mentioned above about Figures 17A to 17E After forming the insulating spacer 74 in the lateral isolation trench 79, theFigure 49B Vertical cross-sectional view of an alternative configuration of a third exemplary structure of the corresponding vertical planes A-A' and B-B' in []. However, in this embodiment, the external blocking dielectric layer 44 may be located between the insulating spacer 74 and the planar vertical extension surface 20S of the auxiliary support pillar structure 20P, and the planar vertical extension surface is coplanar with the insulating layer 32 in the sidewall of the lateral isolation trench 79. The external blocking dielectric layer 44 may include a first insulating material, such as an insulating metal oxide, such as an alumina layer, while the insulating spacer 74 and the auxiliary support pillar structure 20P include a second insulating material different from the first insulating material, such as silicon oxide. In one embodiment, the insulating spacer 74 may include a laterally protruding insulating fin 74F that protrudes into the lateral recess 46R located at the level of the conductive layer 46.

[0256] Referring to all the drawings and according to various embodiments of the present disclosure, a memory device includes: a pair of alternating stacks (32, 46) of an insulating layer 32 and a conductive layer 46, wherein the pair of alternating stacks (32, 46) are laterally spaced apart from each other by a lateral isolation trench 79 extending laterally along a first horizontal direction hd1; a memory opening 49 that vertically extends through a corresponding one of the pair of alternating stacks (32, 46); a memory opening filling structure 58 located in the memory opening 49, wherein each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50) and a vertical semiconductor channel 60; a lateral isolation trench filling structure (74, 76) located in the lateral isolation trench 79; and a support pillar structure 20 that vertically extends through a corresponding one of the pair of alternating stacks (32, 46), wherein the support pillar structure 20 includes a first type of support pillar structure 20A and an auxiliary support pillar structure 20P, the first type of support pillar structure each having a corresponding circular or elliptical horizontal cross-sectional shape, and the auxiliary support pillar structure each having a horizontal cross-sectional shape of a circular or elliptical sector and having a planar vertical extension surface 20S.

[0257] In one embodiment, the curved portion of the horizontal cross-sectional shape of the sector has a radius of curvature greater than half of the width of the lateral isolation trench filling structure (74, 76). In one embodiment, the first type of support pillar structure 20A has a first maximum lateral dimension in a horizontal cross-sectional view; and the radius of curvature is in the range of 50% to 200% of half of the first maximum lateral dimension.

[0258] In one embodiment, the first type of support pillar structures 20A are arranged in a plurality of rows extending laterally along a first horizontal direction hd1; and the auxiliary support pillar structures 20P are arranged in two rows extending laterally along the first horizontal direction hd1. In one embodiment, the two rows of the auxiliary support pillar structures 20P are laterally spaced from each other by a lateral spacing equal to the width of the lateral isolation trench fill structures (74, 76).

[0259] In one embodiment, each row of the first type of support pillar structures 20A has a first center-to-center pitch pcc1 along the first horizontal direction hd1; and each row of the auxiliary support pillar structures 20P has a second center-to-center pitch pcc2 equal to the first center-to-center pitch pcc1 along the first horizontal direction hd1. In one embodiment, the center of gravity of one of the auxiliary support pillar structures in the auxiliary support pillar structures 20P is laterally offset from the center of gravity of the nearest first type of support pillar structure 20 in the first type of support pillar structures 20A by a lateral offset distance equal to half of the first center-to-center pitch pcc1.

[0260] In one embodiment, the two rows of the auxiliary support pillar structures 20P include a first row and a second row; the center of curvature of the curved sidewall of the support pillar structure 20 in the first row is located within a vertical line passing through the lateral trench fill structure; and the center of curvature of the curved sidewall of another support pillar structure 20 in the second row is located within the vertical line.

[0261] In one embodiment, the first alternating stack (32, 46) within the pair of alternating stacks (32, 46) includes a first stepped surface; the second alternating stack (32, 46) within the pair of alternating stacks (32, 46) includes a second stepped surface; and each support pillar structure in the support pillar structures 20 extends vertically through the first stepped surface or the second stepped surface. In one embodiment, the memory device further includes: a first inverse-stepped dielectric material portion 65 overlying the first stepped surface; a second inverse-stepped dielectric material portion 65 overlying the second stepped surface; a first layer of contact via structures 86 extending vertically through the first inverse-stepped dielectric material portion 65 and contacting a corresponding conductive layer within the first alternating stack (32, 46); and a second layer of contact via structures 86 extending vertically through the second inverse-stepped dielectric material portion 65 and contacting a corresponding conductive layer within the second alternating stack (32, 46).

[0262] In one embodiment, the planar vertical extension surface 20S extends parallel to at least a portion of the sidewall of the lateral isolation trench fill structures (74, 76) (e.g., the sidewall of the spacer 74 at the level of the insulating layer 32). InFigure 60A and Figure 60B In one embodiment as shown, the external barrier dielectric layer 44 includes an insulating material different from the lateral isolation trench fill structure (e.g., different from the spacer 74). A first portion of the external barrier dielectric layer 44 is located between the conductive layer 46 and the insulating layer 32, and a second (e.g., vertical) portion of the external barrier dielectric layer 44 is located between the sidewalls of the lateral isolation trench fill structures (74, 76) and the planar vertical extension surfaces 20S of each of the auxiliary support pillar structures in the auxiliary support pillar structure 20P. In Figure 60B one embodiment as shown, the lateral isolation trench fill structures (74, 76) include laterally protruding insulating fins 74F that protrude into a lateral recess 46R located at the level of the conductive layer 46.

[0263] In one embodiment, the memory device includes at least one source layer 114 underlying the pair of alternating stacks (32, 46), wherein each memory opening fill structure in the memory opening fill structures 58 includes a corresponding vertical semiconductor channel 60 having a bottom end electrically connected to a corresponding one of the at least one source layer 114. In one embodiment, the pair of alternating stacks (32, 46), the memory opening fill structures 58, the lateral isolation trench fill structures (74, 76), and the support pillar structure 20 are located in the memory die 900; and the memory die 900 is bonded to the logic die 700, which includes peripheral circuitry configured to control the operation of the vertical stack of the conductive layer 46 and the memory elements.

[0264] In one embodiment, each memory opening fill structure in the memory opening fill structures 58 includes a memory film 50 and a vertical semiconductor channel 60; the memory film 50 includes a layer stack of a barrier dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56; and a portion of the charge storage layer 54 located at the level of the conductive layer 46 includes a vertical stack of memory elements.

[0265] Various embodiments of the present disclosure can be used to provide additional auxiliary support pillar structures 20P, which can be used to provide mechanical support to the three-dimensional memory device during replacement of the sacrificial material layer 42 with the conductive layer 46, and reduce or prevent deflection of the conductive layer 46 at the diagonal between the support pillar structure 20 and the lateral isolation trench 79. In addition, unintended vertical penetration of the lateral isolation trench 79 into the area under the auxiliary support pillar structure 20P is also reduced. Further, no additional process steps are required to form the auxiliary support pillar structure 20P, thereby reducing the number of process steps.

[0266] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision various modifications to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprising" or "including" contemplates all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the performance of a processing step, an embodiment in which such element or such processing step is not performed is also clearly envisioned, provided that the resulting device or apparatus can provide an equivalent result. Thus, whenever the formation of such element or such processing step is omitted and can provide the same result or an equivalent result, the auxiliary verb "can" as applied to the formation of an element or the performance of a processing step should also be interpreted as "may" or "may, or may not", and these equivalent results include slightly superior results and slightly inferior results. In the case where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible for those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each such document is hereby incorporated by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: A pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks includes insulating layers and conductive layers that are interleaved along a vertical direction, and wherein the pair of alternating stacks are laterally spaced apart from each other by a lateral isolation trench that extends laterally along a first horizontal direction; Memory openings that vertically extend through a respective one of the pair of alternating stacks; Memory opening fill structures, each memory opening fill structure being located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel; And A lateral isolation trench fill structure, the lateral isolation trench fill structure being located in the lateral isolation trench, the lateral isolation trench fill structure including: A plurality of neck portions having a pair of straight sidewalls that extend along the first horizontal direction and having a first width along a second horizontal direction that is perpendicular to the first horizontal direction; And A plurality of lateral protrusion portions having a second width that is greater than the first width along the second horizontal direction, wherein the plurality of lateral protrusion portions are interleaved with the plurality of neck portions along the first horizontal direction.

2. The three-dimensional memory device according to claim 1, wherein: The memory opening fill structures are located in a memory array region; A layer contact via structure that contacts a respective one of the conductive layers and is located in a contact region that is laterally offset from the memory array region along the first horizontal direction; and The plurality of lateral protrusion portions are at least located in a transition region that is located between the memory array region and the contact region.

3. The three-dimensional memory device according to claim 2, wherein: Each memory opening fill structure in the memory opening fill structures further includes a respective drain region that is contacted by a respective drain contact via structure; and The transition region and the contact region do not have any drain contact via structures.

4. The three-dimensional memory device according to claim 3, the three-dimensional memory device further comprising: A first type of support pillar structure, each first type of support pillar structure vertically extending through a respective one of the pair of alternating stacks and being located in the contact region and being substantially composed of at least one dielectric material; And A second type of support pillar structure, each second type of support pillar structure vertically extending through a respective one of the pair of alternating stacks and being located in the transition region and including a respective set of dielectric material layers and a respective semiconductor material layer.

5. The three-dimensional memory device according to claim 4, wherein: Each lateral protrusion portion among the plurality of lateral protrusion portions is positioned adjacent to a respective one of the plurality of second type of support pillar structures along the second horizontal direction; The respective vertical stack of memory elements includes portions of respective memory membranes that are at the levels of the conductive layers; And The corresponding memory film has the same set of materials as the corresponding set of dielectric material layers and has the same thickness as the corresponding set of dielectric material layers.

6. The three-dimensional memory device according to claim 4, wherein the plurality of lateral protrusions are located only in the transition region and not in the memory array region or the contact region.

7. The three-dimensional memory device according to claim 6, wherein a plurality of staggered lateral protrusions and neck portions are located between a corresponding pair of straight surface segments that extend along the first horizontal direction in the memory array region and the contact region.

8. The three-dimensional memory device according to claim 2, wherein the plurality of lateral protrusions are also located in the memory array region.

9. The three-dimensional memory device according to claim 1, wherein: the plurality of lateral protrusions have a uniform pitch along the first horizontal direction; and each of the plurality of lateral protrusions has the second width that varies along the second horizontal direction and a pair of laterally convex surface segments that are laterally spaced apart from each other along the second horizontal direction.

10. The three-dimensional memory device according to claim 1, wherein each of the plurality of lateral protrusions includes four laterally convex surface segments that are laterally spaced apart from each other and do not directly contact each other.

11. The three-dimensional memory device according to claim 1, wherein each of the plurality of lateral protrusions includes a corresponding uniformly wide portion having a second width.

12. The three-dimensional memory device according to claim 1, wherein the lateral isolation trench filling structure includes an insulating spacer and a conductive filling structure that is laterally surrounded by the insulating spacer.

13. The three-dimensional memory device according to claim 12, wherein: the conductive filling structure includes discrete air gaps located at the middle of the lateral protrusions and at the middle of the neck portions; and the discrete air gaps are enclosed and do not continue along the first horizontal direction through the interface region between the lateral protrusions and the neck portions.

14. The three-dimensional memory device according to claim 1, wherein the insulating spacer includes: a pair of outer longitudinal sidewalls, each of the pair of outer longitudinal sidewalls including a plurality of laterally convex surface segments that are staggered with a plurality of first laterally straight surface segments; and a pair of inner longitudinal sidewalls, each of the pair of inner longitudinal sidewalls including a plurality of laterally concave surface segments that are staggered with a plurality of second laterally straight surface segments.

15. A three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers; memory openings that vertically extend through the alternating stack in a memory array region; memory opening filling structures that are located in respective ones of the memory openings and include respective vertical stacks of memory elements and respective vertical semiconductor channels; A layer contact via structure that contacts a corresponding one of the conductive layers in the conductive layer and is located in a contact region, the contact region being laterally offset from the memory array region along the first horizontal direction; A lateral isolation trench fill structure that is positioned adjacent to the alternating stack, the lateral isolation trench fill structure including a plurality of narrower neck portions and wider lateral protrusion portions, the wider lateral protrusion portions alternating with the neck portions along the first horizontal direction and being positioned in a transition region between the memory array region and the contact region along the first horizontal direction; A first type of support pillar structure that each vertically extends through the alternating stack in the contact region and is substantially composed of at least one dielectric material; and A second type of support pillar structure that each vertically extends through the alternating stack in the transition region and includes a corresponding set of dielectric material layers and a corresponding semiconductor material layer.

16. A method of forming a three-dimensional memory device, the method comprising: Forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer over a substrate; Forming a memory opening through the vertical alternating sequence; Forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; Forming a lateral isolation trench extending generally along a first horizontal direction through the vertical alternating sequence, wherein the lateral isolation trench includes a plurality of neck portions that have a first width along a second horizontal direction perpendicular to the first horizontal direction between a corresponding pair of straight surface segments extending along the first horizontal direction, and the lateral isolation trench further includes a plurality of lateral protrusion portions that have a second width greater than the first width along the second horizontal direction, wherein the plurality of lateral protrusion portions are staggered with the plurality of neck portions along the first horizontal direction; and Replacing a remaining portion of the continuous sacrificial material layer with a conductive layer to form a pair of alternating stacks of an insulating layer and a conductive layer separated by the lateral isolation trench along the second horizontal direction.

17. The method according to claim 16, wherein: The memory opening fill structure is formed in a memory array region; The method further includes forming a layer contact via structure on a corresponding one of the conductive layers in a contact region, the contact region being laterally offset from the memory array region along the first horizontal direction; and A subset of the plurality of lateral protrusion portions is formed in a transition region that is located between the memory array region and the contact region along the first horizontal direction.

18. The method according to claim 17, the method further comprising: A drain contact via structure is formed on a top surface of the memory opening filling structure in the memory array region, and no drain contact via structure is formed in the transition region or the contact region; A first type of support pillar structure is formed through the vertical alternating sequence in the contact region, wherein the first type of support pillar structure is substantially composed of at least one dielectric material; and A second type of support pillar structure is formed through the vertical alternating sequence in the transition region, wherein each second type of support pillar structure in the second type of support pillar structure includes a corresponding set of dielectric material layers and a corresponding semiconductor material layer.

19. The method according to claim 17, wherein: An entire portion of the lateral isolation trench filling structure located in the memory array region has a uniform array region width smaller than the second width; and An entire portion of the lateral isolation trench filling structure located in the contact region has a uniform contact region width smaller than the second width.

20. The method according to claim 17, wherein the plurality of lateral protrusions are formed only in the transition region.

21. A three-dimensional memory device, the three-dimensional memory device comprising: A pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks includes insulating layers and conductive layers that are staggered along a vertical direction, and wherein the pair of alternating stacks are laterally spaced apart from each other by a lateral isolation trench that extends laterally along a first horizontal direction; Memory openings that vertically extend through a corresponding one of the pair of alternating stacks; Memory opening filling structures that are located in corresponding ones of the memory openings and include corresponding vertical semiconductor channels and corresponding vertical stacks of memory elements; Rows of support pillar structures, wherein each row of the support pillar structures extends laterally along the first horizontal direction and vertically extends through a corresponding one of the pair of alternating stacks; and A lateral isolation trench filling structure that has a variable width along a second horizontal direction and is located in the lateral isolation trench, the lateral isolation trench filling structure including: A plurality of neck portions that have a pair of straight sidewalls extending along the first horizontal direction and have a first width along the second horizontal direction that is perpendicular to the first horizontal direction; and A plurality of lateral protrusions that have a second width greater than the first width along the second horizontal direction, wherein the plurality of lateral protrusions are staggered along the first horizontal direction with respect to the plurality of neck portions.

22. The three-dimensional memory device according to claim 21, wherein: Each row of the support pillar structures extends along the first horizontal direction with a uniform pitch; and The variable width of the lateral isolation trench filling structure has a periodic undulation along the first horizontal direction, the periodic undulation having the same periodicity as the uniform pitch.

23. The three-dimensional memory device according to claim 22, wherein the lateral isolation trench filling structure is laterally spaced from the nearest row in the rows of the support pillar structure along the second horizontal direction.

24. The three-dimensional memory device according to claim 23, wherein: A first Euclidean plane including the position of the geometric center of the nearest row of the support pillar structure is represented by a first set of fixed values of a first component in a Cartesian coordinate system, the Cartesian coordinate system adopting a first axis parallel to the first horizontal direction and a second axis parallel to the second horizontal direction and representing each coordinate by a combination of the first component and the second component; A second Euclidean plane including the position of the maximum value of the variable width is represented by a second set of fixed values of the first component in the Cartesian coordinate system; and Each fixed value within the second set of fixed values is offset from the fixed value within the first set of fixed values by a product of an odd number and half of the uniform pitch.

25. The three-dimensional memory array according to claim 23, wherein: Each of the plurality of neck portions has a uniform width, and the uniform width is the first width; Each of the lateral protruding portions has a maximum width, and the maximum width is the second width.

26. The three-dimensional memory device according to claim 23, wherein: Each pair of adjacent support pillar structures within the nearest row of the support pillar structure are laterally spaced from each other by a pillar-to-pillar pitch along the first horizontal direction; and The minimum distance between the nearest row of the support pillar structure and the lateral isolation trench filling structure is less than the pillar-to-pillar pitch.

27. The three-dimensional memory device according to claim 26, wherein the plurality of lateral protruding portions are closer to the nearest row of the support pillar structure than the plurality of neck regions to the nearest row of the support pillar structure.

28. The three-dimensional memory device according to claim 23, wherein each of the plurality of protruding portions protrudes into a space between two adjacent support pillar structures in the nearest row of the support pillar structure along the second horizontal direction.

29. The three-dimensional memory device according to claim 23, wherein the plurality of lateral protruding portions are closer to the nearest row of the support pillar structure than the plurality of neck regions to the nearest row of the support pillar structure.

30. The three-dimensional memory device according to claim 21, the three-dimensional memory device further comprising: A contact-level dielectric layer, the contact-level dielectric layer covering the pair of alternating stacks and including two portions laterally spaced by the lateral isolation trench; and A drain contact via structure, the drain contact via structure vertically extending through the contact-level dielectric layer and contacting the top surface of a corresponding one of the memory opening filling structures of the memory opening filling structures, wherein all top surfaces of the support pillar structure contact the bottom surface of the contact-level dielectric layer.

31. The three-dimensional memory device according to claim 21, wherein the support pillar structure only includes one or more dielectric materials.

32. The three-dimensional memory device according to claim 21, wherein the rows of the support pillar structures are arranged as two rectangular arrays of support pillar structures within respective alternating stacks of the pair of alternating stacks.

33. The three-dimensional memory device according to claim 21, wherein: each of the pair of alternating stacks includes a respective stepped region in which a lateral extent of the conductive layers within each of the alternating stacks varies with a vertical distance from a horizontal plane including a bottommost surface of the pair of alternating stacks; and the rows of the support pillar structures are located in the stepped regions of the pair of alternating stacks.

34. The three-dimensional memory device according to claim 21, wherein the lateral isolation trench filling structure has a uniform width throughout a region between a first subset of the memory opening filling structures that vertically extend through a first alternating stack within the pair of alternating stacks and a second subset of the memory opening filling structures that vertically extend through a second alternating stack within the pair of alternating stacks.

35. A method of forming a three-dimensional memory device, the method comprising: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer over a substrate; forming memory openings through the vertical alternating sequence; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures in the memory opening filling structures includes a respective vertical stack of memory elements and a vertical semiconductor channel; forming rows of support pillar structures, wherein each row of the support pillar structures is periodically arranged at a uniform pitch along a first horizontal direction and vertically extends through the vertical alternating sequence; forming lateral isolation trenches that generally extend along the first horizontal direction through the vertical alternating sequence, wherein the lateral isolation trenches have a variable width along a second horizontal direction, the variable width having a periodic undulation along the first horizontal direction, the periodic undulation having the same periodicity as the uniform pitch; and replacing a remaining portion of the continuous sacrificial material layer with conductive layers to form a pair of alternating stacks of insulating layers and conductive layers separated by the lateral isolation trenches along the second horizontal direction.

36. The method according to claim 35, wherein the lateral isolation trenches include a plurality of lateral protrusions that are staggered along the first horizontal direction with a nearest-side row of the rows of the support pillar structures and are laterally spaced apart from the nearest-side row of the rows of the support pillar structures along the second horizontal direction.

37. The method according to claim 36, wherein: a first Euclidean plane including a position of a geometric center of the nearest-side row of the support pillar structures is represented by a first set of fixed values of a first component in a Cartesian coordinate system that employs a first axis parallel to the first horizontal direction and a second axis parallel to the second horizontal direction and represents each coordinate by a combination of the first component and a second component; The second Euclidean plane containing the position of the maximum value of the variable width is represented by a second set of fixed values of the first component in the Cartesian coordinate system; and Each fixed value within the second set of fixed values is offset from the fixed values within the first set of fixed values by a product of an odd number and half of the uniform pitch.

38. The method according to claim 36, wherein: The lateral isolation trenches include a plurality of neck portions staggered along the first horizontal direction with respect to the plurality of lateral protrusions; and Each neck portion within the plurality of neck portions abuts a corresponding pair of lateral protrusions within the plurality of lateral protrusions.

39. The method according to claim 38, wherein: Each neck portion among the plurality of neck portions has a uniform width, which is a first width; and Each lateral protrusion among the lateral protrusions has a maximum width, which is greater than the first width.

40. The method according to claim 36, wherein: Each pair of adjacent support pillar structures within the nearest row of the support pillar structures are laterally spaced from each other along the first horizontal direction by a pillar-to-pillar pitch; and The minimum distance between the nearest row of the support pillar structures and the lateral isolation trench filling structure is less than the pillar-to-pillar pitch.

41. A memory device, the memory device comprising: A pair of alternating stacks of an insulating layer and a conductive layer, wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench extending laterally along a first horizontal direction; Memory openings that vertically extend through a respective one of the pair of alternating stacks; Memory opening filling structures that are located in the memory openings, wherein each memory opening filling structure among the memory opening filling structures includes a respective vertical stack of memory elements and a vertical semiconductor channel; A lateral isolation trench filling structure that is located in the lateral isolation trench; and Support pillar structures that vertically extend through a respective one of the pair of alternating stacks, wherein the support pillar structures include a first type of support pillar structure and auxiliary support pillar structures, the first type of support pillar structures each having a respective circular or elliptical horizontal cross-sectional shape, and the auxiliary support pillar structures each having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically extending surface.

42. The memory device according to claim 41, wherein the curved portion of the horizontal cross-sectional shape of the sector has a radius of curvature greater than half of the width of the lateral isolation trench filling structure.

43. The memory device according to claim 41, wherein: The first type of support pillar structures are arranged in a plurality of rows extending laterally along the first horizontal direction; and The auxiliary support pillar structures are arranged in two rows extending laterally along the first horizontal direction.

44. The memory device according to claim 43, wherein the two rows of the auxiliary support pillar structures are laterally spaced from each other by a lateral pitch equal to the width of the lateral isolation trench filling structure.

45. The memory device according to claim 43, wherein: each row of the first type of support pillar structure has a first center-to-center pitch along the first horizontal direction; and each row of the auxiliary support pillar structure has a second center-to-center pitch equal to the first center-to-center pitch along the first horizontal direction.

46. The memory device according to claim 45, wherein the center of gravity of one of the auxiliary support pillar structures in the auxiliary support pillar structure is laterally offset from the center of gravity of the nearest first type of support pillar structure in the first type of support pillar structure by a lateral offset distance equal to half of the first center-to-center pitch.

47. The memory device according to claim 43, wherein: the two rows of the auxiliary support pillar structure include a first row and a second row; the center of curvature of the curved sidewall of the auxiliary support pillar structure in the first row is located within a vertical line passing through the lateral trench filling structure; and and the center of curvature of the curved sidewall of another auxiliary support pillar structure in the second row is located within the vertical line.

48. The memory device according to claim 41, wherein: the first alternating stack within the pair of alternating stacks includes a first stepped surface; the second alternating stack within the pair of alternating stacks includes a second stepped surface; and each support pillar structure in the support pillar structure extends vertically through the first stepped surface or the second stepped surface.

49. The memory device according to claim 48, the memory device further comprising: a first inverse stepped dielectric material portion overlying the first stepped surface; a second inverse stepped dielectric material portion overlying the second stepped surface; a first layer of contact via structure extending vertically through the first inverse stepped dielectric material portion and contacting a corresponding conductive layer within the first alternating stack; and and a second layer of contact via structure extending vertically through the second inverse stepped dielectric material portion and contacting a corresponding conductive layer within the second alternating stack.

50. The memory device according to claim 41, wherein the planar vertical extension surface extends parallel to at least a portion of the sidewall of the lateral isolation trench filling structure.

51. The memory device according to claim 50, the memory device further comprising an external barrier dielectric layer, the external barrier dielectric layer including an insulating material different from the lateral isolation trench filling structure, wherein a first portion of the external barrier dielectric layer is located between the conductive layer and the insulating layer, and a second portion of the external barrier dielectric layer is located between the sidewall of the lateral isolation trench filling structure and the planar vertical extension surface of each auxiliary support pillar structure in the auxiliary support pillar structure.

52. The memory device according to claim 41, wherein the lateral isolation trench filling structure includes a laterally protruding insulating fin protruding into a lateral recess at the level of the conductive layer.

53. A method of forming a memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a stepped surface by patterning the alternating stack; forming an inverse-stepped dielectric material portion over the stepped surface; forming a support opening fill structure through the inverse-stepped dielectric material portion and underlying portions of the alternating stack; forming memory openings through the alternating stack; forming a memory opening fill structure in the memory openings, wherein each memory opening fill structure in the memory opening fill structure includes a respective vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench through the inverse-stepped dielectric material portion, through the alternating stack, and through a first row of a first support pillar structure of the support pillar structure to cut each first support pillar structure in the first support pillar structure into a respective pair of auxiliary support pillar structures, each auxiliary support pillar structure in the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a circular or oval sector and having a planar vertical extension surface in opposite sidewalls of the lateral isolation trench; and replacing the sacrificial material layer with a conductive layer.

54. The method according to claim 53, wherein each first support pillar structure in the first support pillar structure includes a respective central portion that is etched through during formation of the lateral isolation trench and a respective pair of outer peripheral portions including the respective pair of auxiliary support pillar structures.

55. The method according to claim 53, wherein a second support pillar structure in the support pillar structure is not cut by the lateral isolation structure and has a respective circular or oval horizontal cross-sectional shape.

56. The method according to claim 53, wherein: the second support pillar structures are arranged in a plurality of rows extending laterally along the first horizontal direction; and a plurality of pairs of the auxiliary support pillar structures are arranged in two rows along the first horizontal direction.

57. The method according to claim 56, wherein: each row of the second support pillar structures has a first center-to-center pitch along the first horizontal direction; and the rows of the first support pillar structures have a second center-to-center pitch along the first horizontal direction equal to the first center-to-center pitch.

58. The method according to claim 53, the method further comprising forming a lateral isolation trench fill structure in the lateral isolation trench, wherein the lateral isolation trench fill structure includes a laterally protruding insulating fin that protrudes into a lateral recess at a level of the conductive layer.

59. The method according to claim 58, the method further comprising forming an external barrier dielectric layer before forming the lateral isolation trench fill structure, wherein: the external barrier dielectric layer includes an insulating material different from the lateral isolation trench fill structure; a first portion of the external barrier dielectric layer is located between the conductive layer and the insulating layer; and The second portion of the external blocking dielectric layer is located between the sidewall of the lateral isolation trench filling structure and the planar vertical extension surface of each auxiliary support pillar structure in the auxiliary support pillar structure.

60. A method of forming a memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a stepped surface by patterning the alternating stack; forming an inverse-stepped dielectric material portion over the stepped surface; forming a support opening filling structure through the inverse-stepped dielectric material portion and a underlying portion of the alternating stack; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure comprises a respective vertical stack of memory elements and a vertical semiconductor channel; forming a lateral isolation trench through the inverse-stepped dielectric material portion, through the alternating stack, and through a first row and a second row of a first support pillar structure of the support pillar structure to cut each of the first support pillar structure and the second support pillar structure into a respective pair of auxiliary support pillar structures, each auxiliary support pillar structure in the pair of auxiliary support pillar structures having a horizontal cross-sectional shape of a circular or oval sector and having a planar vertical extension surface in opposite sidewalls of the lateral isolation trench; and replacing the sacrificial material layer with a conductive layer.

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