Digital deformable mirror control system for adaptive optics

Abstract

The invention discloses a digital deformable mirror control system for adaptive optics, and belongs to the technical field of optical system control. The system comprises a remote control platform, a driving system and a power supply system, the remote control platform comprises a direct-current power supply, a level interface, a driving signal sending module, a signal control module and an image processing module, and the direct-current power supply is connected with the driving signal sending module through the level interface; the signal control module receives a wavefront correction instruction of the image processing module, generates a plurality of paths of digital control signals and sends the digital control signals to the driving signal sending module; the driving system comprises an FPGA, a level conversion interface, a plurality of digital potentiometers and the same number of driving channels. According to the invention, a hierarchical voltage stabilization structure is adopted, stable operation of the system is ensured, and the system has good dynamic adaptability and is suitable for high-precision remote control and complex signal processing scenes.

Description

Technical Field

[0001] The present invention relates to a deformable mirror control system, and particularly to a digital deformable mirror control system for adaptive optics, belonging to the technical field of optical system control. Background Art

[0002] With the rapid development of optical technology, Adaptive Optics (AO) systems have been widely used in fields such as astronomy, medical imaging, and high-precision optical measurement. The core of an adaptive optics system lies in achieving real-time compensation for wavefront distortion to improve imaging quality and beam transmission efficiency. Among them, the deformable mirror (DM), as a key wavefront correction element, compensates for dynamic aberrations by adjusting the mirror surface shape, and its performance directly determines the overall effect of the system.

[0003] However, in the prior art, the drive control system of the deformable mirror mainly adopts an analog signal processing method, and there are the following key problems: (1) The accuracy of the analog drive circuit is limited by its own physical characteristics, and it is difficult to achieve high-resolution control of the mirror surface shape; (2) During the transmission and processing of analog signals, it is easily affected by external noise interference, resulting in distortion of the control signal, thereby reducing the wavefront correction effect; (3) The traditional drive system has a problem of insufficient response speed and is difficult to effectively meet the requirements of rapidly changing dynamic aberrations; (4) The complex analog circuit design not only increases the volume and power consumption of the system, but also limits its development towards integration and miniaturization.

[0004] The above defects seriously restrict the performance of the adaptive optics system, and there is an urgent need for a deformable mirror control system based on digital technology to achieve high-precision, high-response speed, and high-stability wavefront correction. Summary of the Invention

[0005] Object of the Invention: Aiming at the above problems, the object of the present invention is to provide a digital deformable mirror control system for adaptive optics.

[0006] Technical Solution: A digital deformable mirror control system for adaptive optics according to the present invention includes a remote control platform for receiving the amplitude and frequency of the deformable mirror, generating a digital control signal and sending it to the drive system; A drive system for controlling the deformable mirror according to the received digital control signal; A power supply system for supplying power to the drive system; Wherein the remote control platform includes a DC power supply, a level interface, a drive signal sending module, a signal control module, and an image processing module. The DC power supply is connected to the drive signal sending module through the level interface. The signal control module receives the wavefront correction instruction from the image processing module and generates multiple digital control signals to be sent to the drive signal sending module; The drive system includes an FPGA, a level conversion interface, multiple digital potentiometers, and the same number of drive channels. The FPGA receives digital control signals from the remote control platform through the level conversion interface, processes them, and then transmits them to the drive channels through the digital potentiometers.

[0007] Further, each drive channel is composed of a DC-DC conversion circuit, a high-precision instrumentation amplifier, and a high-voltage drive chip connected in series in sequence.

[0008] Further, the power supply system includes a first buck regulator, a second buck regulator, a first voltage reference source, a second voltage reference source, and a boost regulator; The boost regulator is used to adjust the external input voltage to supply power to the DC-DC conversion circuit and the high-voltage drive chip; the first voltage reference source provides a reference voltage for the first buck regulator; the second voltage reference source provides a reference voltage for the second buck regulator, and the first buck regulator and the second buck regulator supply power to the level conversion interface, the FPGA, and the digital potentiometers.

[0009] Further, the image processing module collects the wavefront aberration image of the deformable mirror through a CMOS sensor. After denoising and flat-field correction, it uses the Zernike polynomial reconstruction algorithm to calculate the wavefront phase distribution and generate a wavefront correction instruction.

[0010] Further, the FPGA has a multi-channel parallel PID control algorithm built in, and each channel is independently configured parameter groups, and the synchronous update of the multi-channel control quantities is realized through matrix operations; Among them, the control law of each channel is: , where, is the control quantity at the k-th sampling moment, e i represents the i phase difference error value at the k-th sampling moment, is the discrete integral of the historical error, is the aberration error at the k-th sampling moment, is the sampling period,

[0011] Further, the digital deformable mirror control system also includes a user interface, and the user interface is connected to the drive signal sending module.

[0012] Further, the drive signal sending module includes a serial communication protocol conversion unit, which converts the digital control signal into a differential signal conforming to the FPGA level standard using the SPI bus protocol, and transmits it to the FPGA of the drive system through a shielded twisted pair at a rate not less than 1 Mbps, and includes channel address coding and a check field in the data frame structure.

[0013] Furthermore, the signal control module incorporates a multiplexer and a shift register array. Based on the wavefront correction instructions provided by the image processing module, it uses time-division multiplexing technology to encapsulate the correction data into 32-bit data packets according to the channel numbers. Each data packet contains a 16-bit amplitude control word and a 16-bit phase compensation parameter, and verifies the data integrity within each transmission cycle through the CRC-16 check algorithm. After passing the verification, it generates a multi-channel parallel control signal with synchronous trigger pulses.

[0014] Beneficial effects: Compared with the prior art, the remarkable advantages of the present invention are as follows: (1) High precision and high response speed: The digital deformable mirror control system described in the present invention can accurately adjust the shape of the deformable mirror and quickly respond to changes in optical wave distortion. (2) Flexibility and scalability: By using FPGA, the digital deformable mirror control system of the present invention can be quickly adjusted according to different application requirements and has strong adaptability. (3) Stability and reliability: The present invention uses a DC-DC conversion circuit and a high-voltage amplifier to ensure the stability of the drive signal, and the buck regulator and boost regulator ensure the stable operation of the system under different power supply conditions. (4) Easy maintenance and upgrade: The digital deformable mirror control system of the present invention is convenient for software upgrade and maintenance, reducing the long-term use cost. Description of the Drawings

[0015] Figure 1 is a structural block diagram of the digital deformable mirror control system; Figure 2 is a structural block diagram of the remote control platform; Figure 3 is a structural block diagram of the FPGA control; Figure 4 is a structural block diagram of the drive system. Detailed Embodiments

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0017] Combined with Figure 1 as shown, a digital deformable mirror control system for adaptive optics described in this embodiment includes a remote control platform for receiving the amplitude and frequency of the deformable mirror, generating a digital control signal and sending it to the drive system; a drive system for controlling the deformable mirror according to the received digital control signal; a power supply system for supplying power to the drive system; The remote control platform includes a DC power supply, a level interface, a drive signal sending module, a signal control module, and an image processing module. The DC power supply is connected to the drive signal sending module through the level interface. The signal control module receives the wavefront correction instruction from the image processing module and generates multiple digital control signals to be sent to the drive signal sending module. The drive system includes an FPGA, a level conversion interface, multiple digital potentiometers, and the same number of drive channels. The FPGA receives the control signal from the remote control platform through the level conversion interface, processes it, and then transmits it to the drive channels through the digital potentiometers.

[0018] In the example, the DC power supply is a multi-channel isolated output power supply that can provide a 12V voltage.

[0019] As shown in Figure 1 The deformable mirror control system includes three parts: a remote control platform, a drive system, and a power supply system, which are used to control the deformable mirror device. The remote control platform analyzes the aberration information of the optical system in real time through the image processing module and generates corresponding correction signals. These correction signals are transmitted to the drive system through the drive signal sending module. The drive system uses an FPGA as the main control chip, configures 8 independent digital potentiometers, a DC-DC conversion circuit, and a high-voltage amplification circuit to form a multi-channel drive architecture. The FPGA receives the instructions from the remote control platform, precisely adjusts the voltage parameters of each channel through the digital potentiometers, boosts the voltage through the DC-DC conversion circuit, and then outputs high-precision drive signals through the high-voltage amplification circuit to achieve independent control of multiple actuators in the deformable mirror device. The power supply system provides multi-level stable power supplies for the drive system and the remote control platform through a buck regulator, a boost regulator, and a voltage reference source to ensure the normal operation of each module of the system. The deformable mirror device, as the actuator, generates deformation under the action of the high-voltage drive signal, thereby dynamically adjusting the optical wavefront phase. Based on the feedback mechanism of the adaptive optical system, this system can real-time correct the aberration caused by environmental disturbances or optical device defects, significantly improving the imaging quality of the optical system.

[0020] The drive signal sending module contains a serial communication protocol conversion unit, which converts the digital control signals into differential signals that meet the FPGA level standard using the SPI bus protocol, and transmits them to the FPGA of the drive system through shielded twisted pair at a rate not less than 1Mbps. Moreover, the channel address encoding and check field are included in the data frame structure.

[0021] The signal control module is built-in with a multiplexer and a shift register array. Based on the wavefront correction instructions provided by the image processing module, it uses time-division multiplexing technology to encapsulate the correction data into 32-bit data packets according to the channel numbers. Each data packet contains a 16-bit amplitude control word and a 16-bit phase compensation parameter, and verifies the data integrity within each transmission cycle through the CRC-16 check algorithm. After passing the verification, it generates 8-way parallel control signals with synchronous trigger pulses.

[0022] The image processing module collects the wavefront distortion image of the deformable mirror through a CMOS sensor. After denoising and flat-field correction, it uses the Zernike polynomial reconstruction algorithm to calculate the wavefront phase distribution and generate wavefront correction instructions.

[0023] Furthermore, the digital deformable mirror control system further includes a user interface, and the user interface is connected to the drive signal sending module.

[0024] As shown in Figure 2 , the remote control platform supports the Ethernet communication protocol, is built-in with a Web server and a JSON data interface, and allows users to remotely configure the adjustment rate of the digital potentiometer and the gain parameters of the high-voltage amplifier circuit through an external terminal, and to monitor the voltage, current and temperature status of each channel in real time. Among them, the deformable mirror device is used as the execution terminal, and its deformable mirror array or piezoelectric ceramic driver adjusts the mirror deformation according to the instructions to correct the phase error in the optical path in real time. The corrected wavefront information is fed back to the image processing module through a high-sensitivity wavefront sensor to form a closed-loop control. In the feedback path, the system calculates the residual between the actual wavefront and the target wavefront , and dynamically updates the PID parameters and calibration data to ensure long-term stability.

[0025] The image processing module collects the wavefront distortion image of the deformable mirror device through a wavefront sensor such as a CMOS sensor at a rate of more than a thousand frames per second. After denoising and flat-field correction, it uses the Zernike polynomial reconstruction algorithm to calculate the wavefront phase distribution. This algorithm decomposes the wavefront distortion into a linear combination of Zernike modes, and the mathematical expression is: , where represents the phase distribution function of the measured wavefront, is the nth-order Zernike basis function, is the corresponding coefficient. By solving the overdetermined equation system through singular value decomposition, the optimal coefficient vector A is quickly obtained, and then an actuator displacement instruction with 16-bit precision is generated, where represents the Zernike mode response matrix, Represents the wavefront sensor slope measurement vector.

[0026] After receiving the parsed instructions, the signal control module realizes optimized resource allocation through the dynamic scheduler. This module adopts the non-linear calibration look-up table technology to map 16-bit digital instructions into the target voltage values of each channel. The mapping formula is: , In the formula, Represents the maximum nominal voltage value allowed for output.

[0027] The dynamic scheduler combines real-time feedback error to dynamically adjust the channel priorities. The priority rule is defined as: , In the formula, Represents the dynamic priority weight of the i-th channel. The scheduler arranges the channel processing order in descending order according to to enable high-error channels to quickly suppress the cumulative deviation of large-error channels and dynamically balance the response delay differences among multiple channels. Represents the real-time voltage feedback value of the i-th channel, is the target voltage value of the i-th channel, is the channel response time threshold to ensure that high-error channels are processed first and avoid system oscillation.

[0028] The drive signal transmission module encapsulates the control instructions into data frames using the SPI protocol. The frame structure includes a synchronization header (0xAA), channel number, 16-bit control instructions, and CRC-16 check code. The check algorithm is based on the polynomial , ensuring the integrity and reliability of data transmission. Here, x represents the formal variable in the polynomial, represents the generating polynomial in the CRC check, which is the core parameter of the CRC check mechanism and is used to generate the check code and verify the integrity of data transmission. As the hardware acceleration core of the protocol stack, the FPGA completes data encapsulation and parsing at a rate of more than 20 Mbps, and the end-to-end communication delay is less than 10 microseconds, significantly improving the real-time performance of the system.

[0029] The drive system includes a level conversion interface, FPGA, multiple digital potentiometers, and the same number of drive channels. The level conversion interface includes a bidirectional level conversion chip that supports 1.2V to 3.3V logic level conversion and integrates ESD protection function to ensure signal integrity and anti-interference ability between the FPGA and the remote control platform.

[0030] In the example, a total of 8 digital potentiometers and 8 drive channels are set in the drive system, namely the first digital potentiometer, the second digital potentiometer to the eighth digital potentiometer, and the first drive channel, the second drive channel to the eighth drive channel.

[0031] The adjustable resistance of each digital potentiometer ranges from 0Ω to 50KΩ, and the typical range of the resistance value varying with temperature is from -10ppm / °C to +10ppm / °C. Digital calibration and temperature compensation are achieved through the SPI interface of the FPGA.

[0032] Furthermore, each drive channel is composed of a DC-DC conversion circuit, a high-precision instrumentation amplifier, and a high-voltage drive chip connected in series in sequence, where the high-precision instrumentation amplifier and the high-voltage drive chip constitute a high-voltage amplification circuit.

[0033] Each drive channel corresponds to an independent high-voltage amplification circuit. The high-voltage amplification circuit includes a high-precision instrumentation amplifier and a high-voltage drive chip. The high-voltage drive chip has 32 independent high-voltage amplifiers, and the output voltage is 0 - 250V. The typical working current of each channel is 0 - 60µA, which is used to drive the piezoelectric ceramics of the deformable mirror.

[0034] The deformable mirror control system of this system realizes the high-precision dynamic deformation adjustment of the deformable mirror through multi-channel parallel control and closed-loop feedback correction technology, effectively compensating for the real-time aberration of the optical system. As Figure 3 shown, the system uses an FPGA as the core control unit, receives the aberration correction instruction signal generated by the image processing module, and completes the parsing and routing of the control instruction through the signal processing module. The FPGA internally integrates an eight-channel parallel PID control algorithm, and each channel is independently configured parameter group. The synchronous update of the control quantities of multiple channels is realized through matrix operations. The PID parameters are dynamically adjusted by fuzzy logic in the level conversion interface, connected to the fuzzy controller. The calibration data memory pre-stores the calibration parameters and non-linear compensation data of the deformable mirror, providing a reference for the PID control to improve the repeatability and stability of the system. The feedback loop real-time collects the data of the high-precision instrumentation amplifier to form a closed-loop control mechanism to dynamically adjust the drive signal to cope with environmental disturbances or complex aberration scenarios. In this example, the FPGA model used is EP3C55F484I7.

[0035] The FPGA internally integrates an eight-channel parallel PID control algorithm, and the control law of each channel is: , where is the control quantity at the k-th sampling moment, e i represents the phase difference error value at the i -th sampling moment, is the discrete integral of the historical error, is the aberration error at the k-th sampling moment, is the sampling period, are the proportional gain, integral gain, and differential gain respectively.

[0036] As Figure 4The structure block diagram of the drive system is shown. The core of this deformable mirror control system is to achieve digital dynamic deformation control of the deformable mirror device through high-precision signal conditioning and multi-stage power amplification technology. As the execution unit of the system, the drive link of the deformable mirror device completes voltage boosting through a DC-DC conversion circuit. Specifically, the DC-DC conversion circuit adopts a BOOST topology structure and further amplifies it to 0 - 250V through a high-voltage amplification circuit to drive the deformable mirror actuator. Specifically, a high-voltage drive chip HV256 outputs a driving voltage with a high dynamic range to accurately drive the micro-actuator array of the deformable mirror, thereby realizing the dynamic adjustment of the optical wavefront phase. Between the DC-DC conversion circuit and the high-voltage drive chip, a high-precision instrumentation amplifier INA188 is used for signal conditioning to monitor the output voltage in real time, and closed-loop feedback regulation is achieved through an FPGA to ensure the high precision and fast response ability of the system, with the voltage stability better than 0.01%. This architecture design can effectively compensate for the dynamic aberration in the optical system and significantly improve the imaging quality of the optical system.

[0037] Furthermore, the power supply system includes a first buck regulator, a second buck regulator, a first voltage reference source, a second voltage reference source, and a boost regulator; The boost regulator is used to adjust the external input voltage and supply power to the DC-DC conversion circuit and the high-voltage drive chip; the first voltage reference source provides a reference voltage for the first buck regulator; the second voltage reference source provides a reference voltage for the second buck regulator, and the first buck regulator and the second buck regulator supply power to the level conversion interface, FPGA, and digital potentiometer.

[0038] Both the first buck regulator and the second buck regulator adopt Buck circuits; the boost regulator adopts a Flyback topology. The switching frequency of the boost regulator is 0 - 65kHz, the conversion efficiency is greater than 90%, and it integrates overcurrent and short-circuit protection functions.

[0039] The housing of the deformable mirror control system in this example is an aluminum alloy shielding structure, with a multi-layer PCB layout inside. The high-voltage and low-voltage areas are isolated by optocouplers to ensure that the electromagnetic compatibility meets the IEC 61000-4-5 standard.

Claims

1. A digital deformable mirror control system for adaptive optics, characterized in that, It includes a remote control platform, which is used to receive the amplitude and frequency of the deformable mirror, generate digital control signals and send them to the drive system; The drive system controls the deformable mirror according to the received digital control signals; The power supply system supplies power to the drive system; Among them, the remote control platform includes a DC power supply, a level interface, a drive signal sending module, a signal control module and an image processing module. The DC power supply is connected to the drive signal sending module through the level interface. The signal control module receives the wavefront correction instruction of the image processing module and generates multiple-channel digital control signals to be sent to the drive signal sending module; The drive system includes an FPGA, a level conversion interface, multiple digital potentiometers and the same number of drive channels. The FPGA receives the digital control signals of the remote control platform through the level conversion interface, and after processing, transmits them to the drive channels through the digital potentiometers.

2. The digital deformable mirror control system for adaptive optics according to claim 1, characterized in that, Each drive channel is composed of a DC-DC conversion circuit, a high-precision instrumentation amplifier and a high-voltage drive chip connected in series in sequence.

3. A digital deformable mirror control system for adaptive optics according to claim 2, characterized in that, The power supply system includes a first buck regulator, a second buck regulator, a first voltage reference source, a second voltage reference source and a boost regulator; The boost regulator is used to adjust the external input voltage and supply power to the DC-DC conversion circuit and the high-voltage drive chip; the first voltage reference source provides a reference voltage for the first buck regulator; the second voltage reference source provides a reference voltage for the second buck regulator, and the first buck regulator and the second buck regulator supply power to the level conversion interface, the FPGA and the digital potentiometers.

4. A digital deformable mirror control system for adaptive optics according to claim 1, characterized in that The image processing module collects the wavefront distortion image of the deformable mirror through a CMOS sensor. After denoising and flat-field correction, it uses the Zernike polynomial reconstruction algorithm to calculate the wavefront phase distribution and generate a wavefront correction instruction.

5. A digital deformable mirror control system for adaptive optics according to claim 1, characterized in that, The FPGA incorporates a multi-channel parallel PID control algorithm, and each channel can be configured independently. For the parameter group, the synchronous update of the control quantities of multiple channels is achieved through matrix operations. Among them, the control law of each channel is as follows: , where is the control quantity at the k-th sampling moment, e i represents i the phase difference error value at the -th sampling moment, is the discrete integral of the historical error, is the aberration error at the k-th sampling moment, are the proportional gain, integral gain, and derivative gain respectively.

6. The digital deformable mirror control system for adaptive optics according to claim 1, characterized in that, It also includes a user interface, and the user interface is connected to the drive signal sending module.

7. A digital deformable mirror control system for adaptive optics according to claim 1, characterized in that, The drive signal sending module contains a serial communication protocol conversion unit, which converts the digital control signals into differential signals conforming to the FPGA level standard using the SPI bus protocol, and transmits them to the FPGA of the drive system through a shielded twisted pair at a rate not lower than 1 Mbps, and includes channel address encoding and a check field in the data frame structure.

8. A digital deformable mirror control system for adaptive optics according to claim 1, wherein The signal control module is built-in with a multiplexer and a shift register array. Based on the wavefront correction instruction provided by the image processing module, it uses time-division multiplexing technology to encapsulate the correction data into 32-bit data packets according to the channel number. Each data packet contains a 16-bit amplitude control word and a 16-bit phase compensation parameter, and verifies the data integrity within each transmission cycle through the CRC-16 check algorithm. After passing the verification, it generates multiple-channel parallel control signals with synchronous trigger pulses.

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