True random number generator circuit based on 1T1R and method for generating random numbers

Abstract

The present invention discloses a true random number generator circuit based on 1T1R and a method for generating random numbers thereof, belonging to the field of information security. The present invention aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally include logic gates, triggers, and clock signal generators, resulting in high circuit energy consumption, low throughput, and a large area. The present invention comprises a memristor, a transistor, and a T trigger; one end of the memristor is connected to an input voltage #imgabs0#, and the other end thereof is connected in series to the drain of the transistor via a first wire; the gate of the transistor is connected to a fixed voltage #imgabs1#, and the source is grounded; the first wire connecting the memristor and the transistor leads to a second wire, which is connected to the clock end of the T trigger, and the intersection of the first and second wires is an output node #imgabs2#.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to a true random number generator circuit based on 1T1R and a method for generating random numbers thereof. Background Art

[0002] Hardware-based true random number generators (TRNGs) utilize physical processes to produce truly random values, making them inherently unpredictable. This makes them more secure than traditional pseudo-random number generators (PRNGs), which rely on deterministic algorithms and seed values. Therefore, they are ideal for data encryption and secure communications. Mainstream memory technologies, such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory (FLASH), are all based on charge storage. However, as process nodes shrink to 10nm and beyond, these memory technologies face significant scalability challenges, hindering their ability to meet future demands for energy-efficient, miniaturized, and high-performance TRNGs in terms of power consumption, speed, density, and durability. Resistive random access memory (RRAM) devices stand out due to their unique advantages. Compared to other emerging non-volatile memories, memristors feature a simple metal-insulator-metal (MIM) structure, resulting in lower manufacturing costs and higher storage density. Their lower programming voltage, faster write / read speeds, and improved scalability simultaneously meet the requirements of low power consumption and high access speed, making memristors promising for compact, low-power secure hardware designs. In addition, when the memristor switches between high and low resistance states, its periodic changes and the noise in the read current constitute the two main sources of entropy. With their inherent random properties, they provide a new method for generating high-quality random numbers.

[0003] Early TRNGs exploited the random properties of the switching voltage or programmed state of non-volatile memristors to generate random numbers. These methods typically rely on random variations relative to a reference value. However, when the reference value drifts over time or over the device's operating cycle, the randomness can be compromised, reducing the reliability of the TRNG. Furthermore, many TRNG circuits utilizing non-volatile memristors require an additional reset process to ensure the memristor's state returns to its initial state. However, this process increases energy consumption and reduces system efficiency, making it difficult for TRNG designs to meet the requirements of high speed, low energy consumption, and high stability. To overcome these limitations, volatile memristors have been introduced into TRNG designs. Unlike non-volatile memristors, volatile memristors automatically return to a high-resistance state without the application of external voltage, eliminating the need for an additional reset process and reducing reset energy overhead. Furthermore, the fast response of volatile memristors, which eliminate the reset step, can significantly improve TRNG throughput, enabling the generation of random bit streams at a higher rate, thus meeting the high-speed, high-quality random number requirements of lightweight applications and secure communications. However, most TRNG circuit designs based on volatile memristors usually have peripheral circuits including logic gates, triggers, and clock signal generators, resulting in high energy consumption, low throughput, and a large area occupation. They are no longer suitable for the development trend of high integration and low power consumption in lightweight application scenarios. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the present invention proposes a true random number generator circuit based on 1T1R, including a memristor, a transistor and a T trigger;

[0005] One end of the memristor is connected to the input voltage The other end is connected in series to the drain of the transistor through a first wire; the gate of the transistor is connected to a fixed voltage , the source is grounded; the first wire connecting the memristor and the transistor leads to a second wire, which is connected to the clock terminal of the T trigger, and the cross connection point of the first wire and the second wire is the output node ;

[0006] The T flip-flop is used to turn the output node Connected to the clock signal terminal as input; input terminal T continuously inputs a stable high-level valid signal High. As the clock terminal continuously inputs an oscillation signal, the output terminal Q flips with the clock terminal, flipping and recording the state transition of the memristor device to achieve a similar counting function; every time a fixed period of time is input , the number of flips is random, and the final output is The result of binarizing the number of flips is a generated random number, so as to realize a self-clocking circuit without an additional high-frequency clock signal generator.

[0007] As a further improvement of the present invention, the memristor is a volatile memristor, and its initial state is a high-resistance state.

[0008] As a further improvement of the present invention, the 1T1R structure is prepared by stacking and integrating a transistor and a memristor. Specifically, after a silicon dioxide layer is formed on a silicon substrate by thermal oxidation, the gate area is defined by a patterned photolithography process, and a gate film is deposited, i.e., the bottom gate is prepared; then, a gate oxide layer is deposited as an isolation layer; then, a patterned photolithography process is used to define the channel area, and the channel layer of the transistor is deposited; the source and drain areas are defined by a patterned photolithography process, and the source and drain electrode layers are plated by magnetron sputtering; on this basis, a through hole is defined by a patterned photolithography process, i.e., the memristor area is defined, which is located above the source / drain electrodes on one side, and then the bottom electrode, the interlayer dielectric layer, and the top electrode are sputtered and deposited in sequence.

[0009] As a further improvement of the present invention, the entropy source of the true random number generator circuit utilizes the random oscillation cycle time of the memristor to continuously provide raw entropy data with high randomness.

[0010] In a second aspect, the present invention provides a method for generating random numbers based on the above-mentioned true random number generator circuit, comprising the following steps:

[0011] step:

[0012] Step 1: Input a fixed voltage to one end of the memristor , the memristor and transistor continuously produce a voltage divider effect, the voltage across the memristor constantly oscillates between above the threshold turn-on voltage and below the holding voltage, and jumps and oscillates between high-resistance and low-resistance states; because the time of each cycle when the memristor switches between high and low resistance states is random, the number of times the memristor flips within a fixed input time is also random;

[0013] Step 2: Output Node The oscillation output reflects the flip state of the memristor, which is used as the input of the clock signal end of the falling edge T flip-flop, so the T flip-flop output The flip of also reflects the random oscillation of the memristor;

[0014] Step 3: Enter a fixed period of time After that, the odd and even number of flips of the memristor during this period of time is mapped to the output state of the T flip-flop, which is specifically expressed as follows: The low level refers to the logic "0", the output The high level refers to the logic "1", realizing the binary expression of the number of flips. When the input terminal repeatedly gives multiple sections with fixed duty cycles, Square wave signal, output of T flip-flop That is, output a string of random numbers.

[0015] Beneficial effects of the present invention:

[0016] The proposed true random number generator circuit utilizes a volatile memristor architecture combined with simple peripheral circuitry to generate random numbers. This architecture eliminates the need for a device reset step. By utilizing the volatile memristor to achieve rapid flipping, the circuit design not only ensures high-quality randomness in the generated random numbers, but also effectively improves system throughput, reduces power consumption, and demonstrates excellent integration potential.

[0017] It can generate self-oscillation signals without relying on external clock modules. This feature can simplify peripheral circuit design, reduce system power consumption, and save chip area.

[0018] The 1T1R structure is used in the memristor circuit, making the circuit highly integrated, with a relatively simple preparation process and a small chip area.

[0019] The overall circuit structure is simple and is manufactured based on a standard CMOS process platform, with good compatibility and engineering practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is based on the TRNG circuit structure of 1T1R;

[0021] Figure 2 is a structural diagram of a memristor according to the present invention;

[0022] Figure 3 is the IV curve of the volatile memristor of the present invention;

[0023] Figure 4 This is a diagram showing the process of applying 1T1R to a TRNG circuit of the present invention;

[0024] Figure 5 It is a flow chart of a method for generating random numbers based on a 1T1R true random number generator circuit of the present invention;

[0025] Figure 6 It is the simulation experiment waveform diagram of the present invention.

[0026] In the figure: 1. Memristor, 2. T trigger, 3. Transistor, A1. First wire, A2. Second wire, 101. Silicon substrate, 102. Silicon dioxide layer, 103. Bottom gate, 104. Gate oxide layer, 105. Channel layer, 106. Source and drain electrode layer, 107. Bottom electrode, 108. Interlayer dielectric layer, 109. Top electrode. DETAILED DESCRIPTION

[0027] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the description. Conversely, these embodiments are provided for the purpose of providing a more thorough and comprehensive understanding of the disclosure of the present application.

[0028] The analyzer in this embodiment is an electrical characteristic parameter analyzer, which is used to accelerate the development of various materials, semiconductor devices and advanced processes, complete process control, reliability analysis and fault analysis, and provide synchronous current-voltage curve testing, namely IV curve testing.

[0029] Example 1

[0030] like Figure 1 As shown, a 1T1R true random number generator circuit includes a memristor 1, a transistor 3 and a T flip-flop 2; the memristor 1 is a volatile memristor, and its initial state is a high-resistance state;

[0031] The metal ion migration mechanism is used to realize a volatile memristor, and its IV curve is as follows: Figure 3 As shown, the volatility of the memristor 1 is specifically manifested as follows: when the voltage across the memristor 1 is greater than its turn-on voltage threshold When the voltage across memristor 1 is lower than its holding voltage, memristor 1 switches from high resistance state to low resistance state. , the memristor 1 automatically switches from a low-resistance state to a high-resistance state.

[0032] One end of the memristor 1 is connected to the input voltage The other end is connected in series to the drain of transistor 3 through the first wire A1; the gate of transistor 3 is connected to a fixed voltage , the source is grounded; the first wire A1 connecting the memristor 1 and the transistor 3 leads to the second wire A2, which is connected to the clock terminal of the T trigger 2. The cross connection point of the first wire A1 and the second wire A2 is the output node .

[0033] like Figure 2 As shown, the basic structure of the memristor 1 includes a bottom electrode 107, an interlayer dielectric layer 108 and a top electrode 109, wherein the top electrode 109 is made of Ag, Cu or other active metals, the interlayer dielectric layer 108 is often made of an oxide dielectric layer, and the bottom electrode 107 is made of inert metals such as Pt, W, Au or heavily doped silicon.

[0034] like Figure 4As shown in the figure, the 1T1R (1 transistor 1 resistor) in the true random number generator (TRNG) circuit uses a process where memristor 1 is stacked on transistor 3, undergoing five photolithography steps. Transistor 3 has voltage-controlled conduction characteristics, with its on / off state controlled by gate voltage. Memristor 1 is a simple metal-insulator-metal (MIM) structure fabricated on top of transistor 3 and exhibits typical volatility.

[0035] The 1T1R structure is fabricated by integrating a transistor and a memristor in a stacked structure. Specifically, after thermal oxidation forms a silicon dioxide layer 102 on a silicon substrate 101, a patterned photolithography process is used to define the gate region, and a gate film is deposited, forming the bottom gate 103. A gate oxide layer 104 is then deposited to serve as an isolation layer. Patterned photolithography is then used to define the channel region, and the channel layer 105 of transistor 3 is deposited. Patterned photolithography is also used to define the source and drain regions, and magnetron sputtering is used to deposit the source and drain electrode layer 106. This completes the fabrication of transistor 3, with the source / drain electrodes being symmetrical and undefined. Furthermore, patterned photolithography is used to define a through-hole, defining the memristor region, located above one source / drain electrode. Subsequently, a bottom electrode 107, an interlayer dielectric layer 108, and a top electrode 109 are sequentially sputtered, ultimately enabling the 1T1R application in a TRNG circuit.

[0036] The entropy source of the TRNG circuit utilizes the random oscillation cycle time of memristor 1 to continuously provide highly random raw entropy data for subsequent random number generation, ensuring the unpredictability of the output random numbers. This oscillation time is the spontaneous oscillation generated by the device under voltage division. Each oscillation cycle is short and highly random, making it suitable for high-speed, high-quality random number generation.

[0037] The T flip-flop 2 is used to turn the output node Connected to the clock signal terminal as input; input terminal T continuously inputs a stable high-level valid signal High. As the clock terminal continuously inputs an oscillation signal, the output terminal Q flips with the clock terminal, flipping and recording the state transition of the memristor 1 device to achieve a similar counting function; every time a fixed period of time is input , the number of flips is random, and the final output is The result of binarizing the number of flips is a generated random number, so as to realize a self-clocking circuit without an additional high-frequency clock signal generator.

[0038] To ensure that the memristor 1 can achieve spontaneous flipping, that is, to achieve a change in the resistance state of the memristor 1, the resistance value of the transistor 3 is determined by the following process:

[0039] The low resistance value of memristor 1 is , maintain voltage , the high resistance of memristor 1 is , threshold turn-on voltage When the input voltage is When , Ohm's law shows that the minimum resistance of transistor 3 is , the maximum value is By controlling the gate voltage, the resistance of transistor 3 can be kept within this range. Therefore, the resistance of transistor 3 in the TRNG circuit is determined by memristor 1 and the input voltage.

[0040] Based on the above, the TRNG circuit proposed in this paper utilizes a volatile memristor combined with simple peripheral circuitry to achieve random number generation. This circuit design eliminates the device reset step and leverages the high-speed state flipping characteristics of memristor 1 to achieve high throughput. This circuit achieves significant gains in energy efficiency, throughput, and integration. The 1T1R structure employed offers the advantages of high integration, a relatively simple fabrication process, and a small footprint. This achievement provides a novel solution for future information security challenges facing resource constraints, high reliability, and energy conservation requirements.

[0041] Example 2

[0042] A method for generating random numbers based on a 1T1R true random number generator circuit comprises the following steps:

[0043] Step 1: Input a fixed voltage to one end of the memristor , the memristor and transistor continuously produce a voltage divider effect, the voltage across the memristor constantly oscillates between above the threshold turn-on voltage and below the holding voltage, and jumps and oscillates between high-resistance and low-resistance states; because the time of each cycle when the memristor switches between high and low resistance states is random, the number of times the memristor flips within a fixed input time is also random;

[0044] Step 2: Output Node The oscillating output reflects the flipping state of the memristor, which is used as the input of the clock signal end of the falling edge T flip-flop. Therefore, the flipping of the output end of the T flip-flop also reflects the random oscillation of the memristor.

[0045] Step 3: Enter a fixed period of time After that, the odd and even number of flips of the memristor during this period of time is mapped to the output state of the T flip-flop, which is specifically expressed as follows: The low level refers to the logic "0", the output The high level refers to the logic "1", realizing the binary expression of the number of flips. When the input terminal repeatedly gives multiple sections with fixed duty cycles, Square wave signal, output of T flip-flop That is, output a string of random numbers.

[0046] Based on the above content, the random number generation method of the present invention can generate a self-oscillating signal without the need for an external clock circuit, thereby reducing peripheral circuits, lowering power consumption, and saving area.

[0047] In order to further illustrate the method for generating random numbers provided by the present invention, the following is described in detail in conjunction with specific embodiments:

[0048] like Figure 5 As shown, the method for generating random numbers based on the true random number generator circuit provided in Example 1 includes the following steps:

[0049] Step 1: Apply voltage across the transistor gate and source The voltage is applied to realize the gate control mechanism, so that the resistance of the transistor is lower than the resistance value when the memristor is in the high-resistance state and higher than the resistance value when the memristor is in the low-resistance state;

[0050] Step 2: Input a fixed voltage to one end of the memristor , The voltage value is greater than the turn-on voltage threshold of the memristor ;

[0051] Step 3: The transistor and memristor continue to produce a voltage divider effect; in addition, the memristor is initially in a high-resistance state;

[0052] Step 4: When the transistor resistance is lower than the high-resistance state of the memristor, the input voltage basically falls on the memristor, and the memristor undergoes the first jump, that is, from the high-resistance state to the low-resistance state; at this time, the transistor resistance is higher than the low-resistance state of the memristor, the input voltage basically falls on the transistor, and the output node Output close to ;

[0053] Step 5: When the input voltage is basically across the transistor, the voltage across the memristor is lower than the holding voltage. When , the memristor undergoes a second jump, that is, it jumps from the low resistance state back to the high resistance state; at this time, the transistor resistance is lower than the high resistance state of the memristor, and the input voltage basically falls on the memristor. The output is close to 0V, and the resistance of the memristor returns to its initial high resistance state;

[0054] Step 6: Repeat steps 3 to 5 to make the memristor continuously jump and oscillate between high resistance state and low resistance state. The output voltage value oscillates spontaneously;

[0055] Step 7: Output Node Continue to serve as the input of the clock signal end of the falling edge T trigger;

[0056] Step 8: Input a stable high-level active signal High to the T input of the T flip-flop. As the clock inputs an oscillating signal, when the T flip-flop detects a falling edge, the output Q flips with the clock.

[0057] Step 9: Enter a fixed period of time After that, the odd and even number of flips of the memristor during this period of time is mapped to the output state of the T flip-flop, which is specifically expressed as follows: The low level refers to the logic "0", the output The high level refers to the logic "1", realizing the binary expression of the number of flips. When the input terminal repeatedly gives multiple sections with fixed duty cycles, Square wave signal, output of T flip-flop That is, output a string of random numbers.

[0058] In order to verify the performance of the proposed true random number generator circuit, an experimental simulation is carried out. The simulation waveform is as follows: Figure 6 This simulation mainly verifies the function of the above circuit and proves the feasibility and effectiveness of the designed structure in randomness and circuit implementation.

[0059] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A true random number generator circuit based on 1T1R, characterized in that: Including memristors, transistors, and T flip-flops; One end of the memristor is connected to the input voltage The other end of the first terminal is connected in series to the drain of the transistor via a first wire; The gate of the transistor is connected to a fixed voltage , the source is grounded; the first wire connecting the memristor and the transistor leads to a second wire, which is connected to the clock terminal of the T trigger, and the cross connection point of the first wire and the second wire is the output node ; The T flip-flop is used to turn the output node Connected to the clock signal terminal as input; input terminal T continuously inputs a stable high-level valid signal High. As the clock terminal continuously inputs an oscillation signal, the output terminal Q flips with the clock terminal, flipping and recording the state transition of the memristor device to achieve a similar counting function; every time a fixed period of time is input , the number of flips is random, and the final output is is the result of binarizing the number of flips, and the result is the generated random number.

2. The 1T1R-based true random number generator circuit according to claim 1, characterized in that: The memristor is a volatile memristor, and its initial state is a high-resistance state.

3. The 1T1R-based true random number generator circuit according to claim 1, characterized in that: The 1T1R structure is prepared by stacking and integrating a transistor and a memristor. Specifically, after a silicon dioxide layer is formed on a silicon substrate by thermal oxidation, a patterned photolithography process is used to define the gate region, and a gate film is deposited to prepare the bottom gate. Then, a gate oxide layer is deposited as an isolation layer. Then, a patterned photolithography process is used to define the channel region, and the channel layer of the transistor is deposited. Then, a patterned photolithography process is used to define the source and drain regions, and the source and drain electrode layers are deposited by magnetron sputtering. On this basis, a through hole is defined by a patterned photolithography process, that is, the memristor region is defined, which is located above the source / drain electrodes on one side, and then the bottom electrode, interlayer dielectric layer, and top electrode are sputtered and deposited in sequence.

4. The 1T1R-based true random number generator circuit according to claim 1, characterized in that: The entropy source of the true random number generator circuit utilizes the random oscillation cycle time of the memristor to continuously provide raw entropy data with high randomness.

5. A method for generating random numbers based on a 1T1R-based true random number generator circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1: Input a fixed voltage to one end of the memristor , the memristor and transistor continuously produce a voltage divider effect, the voltage across the memristor constantly oscillates between above the threshold turn-on voltage and below the holding voltage, and jumps and oscillates between high-resistance and low-resistance states; because the time of each cycle when the memristor switches between high and low resistance states is random, the number of times the memristor flips within a fixed input time is also random; Step 2: Output Node The oscillation output reflects the flip state of the memristor, which is used as the input of the clock signal end of the falling edge T flip-flop, so the T flip-flop output The flip of also reflects the random oscillation of the memristor; Step 3: Enter a fixed period of time After that, the odd and even number of flips of the memristor during this period of time is mapped to the output state of the T flip-flop, which is specifically expressed as follows: A low level indicates logic "0", output The high level refers to logic "1", which realizes the binary expression of the number of flips. When the input terminal repeatedly gives multiple sections with fixed duty cycles, Square wave signal, output of T flip-flop That is, output a string of random numbers.

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