Method for updating prototype system firmware through FPGA platform

Abstract

The invention discloses a method for updating prototype system firmware by an FPGA (Field Programmable Gate Array) platform, which comprises the following steps of: S1, converting binary firmware content to be updated into a format read by a firmware storage module through a Linux command, and embedding the binary firmware content into the firmware storage module to generate a bit stream file; s2, the bit stream file is loaded to an FPGA platform, after resetting is completed, an instruction for reading a chip device ID is sent to the Flash chip firstly, and device ID information output by the Flash chip is received; s3, sending an instruction of opening write enable to the Flash chip, and then sending an instruction of erasing the whole chip; and S4, reading the data from the firmware storage module and burning the data into the Flash chip. According to the method, the step of replacing the firmware content in the Flash chip on the FPGA prototype platform is simplified, hardware equipment such as a professional Flash burner is not needed, the FPGA platform does not need to be powered off and shut down, the Flash chip does not need to be taken down from the FPGA platform, the use loss of the FPGA prototype platform is reduced, the replacement efficiency is remarkably improved, and the requirement for replacing firmware in batches on multiple FPGA prototype verification platforms is met.

Description

Technical Field

[0001] The present invention relates to the field of chip prototype verification, and in particular, provides a convenient method for updating the firmware content in a Flash chip for an FPGA platform. Background Art

[0002] In the field of ASIC chip prototype verification, an ASIC chip prototype system is usually built on an FPGA platform before tape-out, and an operating system and various system-level benchmark test programs are run. The prototype system can generally be regarded as a simplified computer system, which runs in the FPGA platform in the form of a bitstream file and contains most of the functional modules of the ASIC chip design, such as processor cores, interconnect buses, and peripheral interfaces. After the FPGA platform is reset and released, the prototype system needs to read the firmware program from an external non-volatile memory for hardware initialization and loading the operating system. The firmware program is usually stored in the Flash chip connected to the FPGA platform. During the process of ASIC chip design and verification, with the update and iteration of the ASIC design code and the adaptation and update of the firmware program, there are frequent situations of updating the firmware program. For the Flash chip storing the firmware program in the FPGA platform, the current conventional method of replacing the firmware content in the Flash chip requires first powering off the machine, removing the Flash chip and putting it into a dedicated programmer for firmware content update, then putting the Flash chip back into the FPGA platform and fixing it, and finally powering on the FPGA platform again to run the prototype system after the firmware update. The whole process is as Figure 1 shown. Since the machines for FPGA prototype verification are mostly placed in the computer room and the power-on and power-off steps of the machines are cumbersome, this results in a complex and time-consuming process for replacing the firmware of the Flash chip. Summary of the Invention

[0003] Aiming at the problems existing in the prior art, the purpose of the present invention is to provide a method for updating the firmware of a prototype system on an FPGA platform, which can improve the efficiency of replacing the firmware content in the Flash chip of the FPGA prototype system.

[0004] To achieve the above purpose, the present invention provides a method for updating the firmware of a prototype system on an FPGA platform, and the method includes the following steps: S1. Convert the binary firmware content to be updated into a format that can be read by the firmware storage module through Linux commands and embed it into the firmware storage module. Through the EDA tool corresponding to the FPGA platform, synthesize, implement the Verilog HDL code, and generate a bitstream file; S2. Load the bitstream file onto the FPGA platform. After reset completion, first send an instruction to read the chip device ID to the Flash chip and receive the device ID information output by the Flash chip, and check whether the device ID information is correct; S3. Send an instruction to enable writing to the Flash chip, and then send a whole-chip erase instruction. During the erasure, continuously read the status register to determine whether the chip has completed the erasure operation; S4. Finally, send an instruction to enable writing to the Flash chip, and then send a programming instruction. The content to be programmed is obtained from the firmware storage module. During the programming, continuously read the status register to determine whether the chip has completed the programming operation.

[0005] Furthermore, the FPGA includes a Flash controller module, a firmware storage module, and a TOP control module.

[0006] Furthermore, the FPGA platform includes a UART communication module, a Flash controller module, a firmware storage module, and a TOP control module.

[0007] Furthermore, the TOP control module is used to connect each internal module and is used to instruct the Flash controller module, the UART communication module, and the firmware storage module to perform different operations.

[0008] Furthermore, the firmware storage module is implemented through the internal resources of the FPGA, and the storage capacity is adjustable within the storage resources supported by the FPGA chip to be applicable to firmware of different file sizes.

[0009] Furthermore, the Flash controller module is used to perform different process operations on the Flash chip according to different instruction types transmitted by the TOP control module; including sending instructions, sending instructions - receiving data, sending instructions - sending addresses - receiving data, and / or sending instructions - sending addresses - sending data.

[0010] Furthermore, the Flash controller module is used to implement all operation controls on the Flash chip, including: reading and writing registers, erasing, programming, and / or reading stored content.

[0011] Furthermore, the communication module is used to interact with the host computer.

[0012] Furthermore, after embedding the firmware content into the firmware storage module, through the corresponding EDA tool of the FPGA, a bitstream file is compiled and generated. After loading the bitstream file onto the FPGA platform, the operation of updating the firmware can be performed.

[0013] Furthermore, the method can be implemented on multiple FPGA models that meet the hardware resource requirements.

[0014] The beneficial effects of the present invention are as follows: This method simplifies the steps of replacing the firmware content in the Flash chip of the FPGA prototype platform, significantly improves the replacement efficiency, reduces the usage loss of the FPGA prototype platform, enables remote batch operation, and reduces the time required to replace the firmware content of the FPGA prototype platform by more than 80%. Brief Description of the Drawings

[0015] Figure 1 is a schematic diagram of the steps for conventional firmware content update; Figure 2 is a schematic diagram of the steps for updating the firmware content of the present invention; Figure 3 is a schematic diagram of the hardware architecture of the present invention; Figure 4 is a logic control flow chart of the present invention. Detailed Description of the Invention

[0016] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0018] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] The following will be combined with Figures 2 - 4 The specific embodiments of the present invention will be described in detail. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present invention and are not used to limit the present invention.

[0020] The present invention provides a method for updating the firmware content in a Flash chip based on an FPGA bitstream file, without the need to power off the FPGA platform, remove the Flash chip, or use a dedicated Flash programmer. The present invention can also complete the replacement of the content in the Flash chip without the participation of a host computer, relying only on the original FPGA platform, by generating and downloading the bitstream. The whole process is as Figure 2 shown. Due to the lack of usage restrictions on the programmer and the host computer, the present invention can also meet the requirement of batch replacement of firmware for multiple FPGA prototype verification platforms.

[0021] The present invention provides a method for updating the firmware of a prototype system on an FPGA platform, which can simplify the cumbersome steps of replacing the Flash firmware content during the FPGA prototype verification process. The present invention is implemented through Verilog HDL code. As Figure 3 shown, the top layer of the FPGA platform is the TOP control module, which includes a firmware storage module, a UART communication module (optional), and a Flash controller module.

[0022] Among them, the TOP control module is used for interconnection of internal modules and for instructing the Flash controller module to perform different operations on an external Flash chip, including reading and writing registers, erasing, programming, reading stored content, etc.

[0023] The firmware storage module is used to store the firmware content. The firmware storage module is implemented through the internal resources of the FPGA, and the storage capacity is adjustable within the storage resources supported by the FPGA chip. The firmware content can be converted into a file format recognizable by the firmware storage module through Linux commands and embedded into the firmware storage module.

[0024] The UART communication module can be selectively set or not set as needed. It is used to interact with the host computer and can be used to output relevant status or information, including information such as the Flash chip device ID, status register, and stored content. It can also be used to receive signals sent by the host computer, such as erasing, programming, reading ID, etc. After detecting the signal transmitted by the host computer, the TOP control module can send corresponding instructions to the Flash controller according to the signal content to achieve the interactive control of the host computer over the Flash chip.

[0025] The Flash controller module is mainly used for interacting with external Flash chips, and it can implement control operations such as content reading, writing, erasing, and status reading of Flash chips. The Flash controller module can perform different process operations on the Flash chip according to different instruction types transmitted by the TOP control module, including sending instructions, sending instructions - receiving data, sending instructions - sending addresses - receiving data, and sending instructions - sending addresses - sending data.

[0026] The method of the present invention includes the following steps: S1. Convert the binary firmware content into a format that can be read by the firmware storage module through Linux commands and embed it into the firmware storage module. Through the corresponding EDA tool of the FPGA, first synthesize the Verilog HDL code into a netlist, then perform placement and routing, and finally generate a bitstream file. S2. Load the bitstream file onto the FPGA platform. After resetting, the Flash controller module sends an instruction to read the chip device ID to the Flash chip and receives the device ID information output by the Flash chip. The TOP control module executes the subsequent steps after verifying that the device ID information is correct. S3. Then the Flash controller module sends an instruction to enable writing to the Flash chip, and then sends an instruction to erase the entire chip. During the erasing process, continuously read the status register to determine whether the chip has completed the erasing operation. S4. Finally, the Flash controller module sends an instruction to enable writing to the Flash chip again, and then sends a programming instruction. The content to be programmed is obtained from the firmware storage module. During the programming process, continuously read the status register to determine whether the chip has completed the programming operation.

[0027] Figure 3 The hardware structure of the embodiment of the present invention is shown. The embodiment of the present invention is implemented based on the FPGA of the Xilinx platform. As Figure 3 shown, the embodiment of the present invention includes a UART communication module, a Flash controller module, a firmware storage module (BRAM), and a TOP control module. In the embodiment of the present invention, a communication module is used for communication based on the UART protocol. The firmware storage module is implemented in the form of BRAM. BRAM is a type of storage resource in the FPGA, and it can load and store files in the.coe format. After downloading the bitstream file generated by the embodiment of the present invention to the FPGA platform, the logical control process of the Flash chip in the embodiment of the present invention is as Figure 4As shown in the figure. The present invention simulates the functions of erasing and programming Flash chips by a professional Flash programmer on the FPGA platform through pure Verilog HDL, and realizes the update of the firmware content in the Flash chip on the FPGA platform without power-off, without removing the Flash chip, and without relying on external devices such as professional programmers.

[0028] The implementation of replacing the firmware content provided by the embodiments of the present invention includes the following steps: Step S1 includes: S1.1: Under the Linux environment, use the xxd command and sed command to convert the binary bin format firmware file into a coe format file that meets the requirements, and convert the original binary bin format firmware file ($1) into a coe format file ($1.coe). The specific commands are as follows: 1. xxd -c 8 -p $1 2>&1 $1.coe / / Convert the binary firmware content into hexadecimal 2. sed -i's / \(.\)\(.\) / \1\2 / g' $1.coe / / For every two hexadecimal numbers as a group, insert a space between each group 3. sed -i '1imemory_initialization_vector=' $1.coe / / Insert the prefix content of the standard format of the coe file to indicate that the content after this sentence is the data content to be stored 4. sed -i '1imemory_initialization_radix=16' $1.coe / / Insert the prefix content of the standard format of the coe file to indicate that the data is stored in hexadecimal form 5. sed -i '$a ;' $1.coe / / Insert a semicolon at the last line to represent the end of the data content S1.2: Use the Tcl script to set the firmware storage module of the embodiments of the present invention to a data bit width of 8 bits and a depth of 640000 bits through the EDA tool Vivado of the Xilinx platform. It can store firmware with a file size within 625 KB, and import the $1.coe file obtained in step S1.1 into the firmware storage module. Then import the TOP control module, UART communication module, Flash controller module, and firmware storage module into the Vivado tool for logic synthesis, placement and routing, and generate a bitstream file.

[0029] Step S2 includes: S2.1: Download the bitstream file into the FPGA prototype verification platform. After reset, the embodiments of the present invention first enter the workflow of verifying the Flash chip device ID. The Flash controller module communicates with the Flash chip according to the SPI protocol, and first sends an instruction to read the Flash chip device ID to the Flash chip; S2.2: Temporarily store the device ID information transmitted back by the Flash chip in the register of the TOP control module. After the Flash chip transmission is completed, the TOP control module outputs the device ID information in the register to the host computer through the UART communication module.

[0030] Step S3 includes: S3.1: If the Flash chip device ID is correct, send a burnable command through the host computer. The UART communication module will feedback the burnable command to the TOP control module, and then the TOP control module will enter the erasure process. The Flash controller module sends an instruction to enable writing to the Flash chip, and then sends an instruction to erase the entire chip.

[0031] S3.2: Then, the embodiments of the present invention continuously send an instruction to read the Flash chip status register to the Flash chip. The TOP control module judges whether the Flash chip is erased completely according to the status register information feedback by the Flash chip. When the erasure is completed, the UART communication module will output a prompt of erasure completion through the uart serial port.

[0032] Step S4 includes: S4.1: The TOP control module enters the burning process. The burning is carried out in units of pages (Page), and 256 Byte of data is burned for each page. The Flash controller module first sends an instruction to enable writing to the Flash chip, then sends a burning instruction. After sending the burning instruction, it will send the starting address of the burned page, and then sequentially obtain 256 Byte of data from the BRAM firmware storage module and send it to the Flash chip.

[0033] S4.2: After the transmission of 256 Byte of data is completed, the Flash controller module will enter the state of reading the status register, and continuously judge whether the Flash chip has completed the burning operation of this page according to the read status register information.

[0034] S4.3: After detecting that the Flash chip has completed the burning of one page, the Flash controller module will repeat steps S4.1 and S4.2 to perform the burning of the next page. During the entire burning process, the starting address of the burned page and the address for obtaining data in the BRAM firmware storage module increase correspondingly.

[0035] S4.4: When the page address to be programmed reaches the specified page address and the programming of this page is completed, the UART communication module outputs a signal indicating the completion of programming, and the overall steps of the embodiment of the present invention are completed.

[0036] In the description of this specification, the descriptions referring to terms such as "embodiment", "example", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art can combine or combine different embodiments or examples described in this specification and the features therein without contradiction.

[0037] Although the above content has shown and described the embodiments of the present invention, it can be understood that the above embodiments are exemplary and cannot be construed as limiting the present invention. Those of ordinary skill in the art can perform update operations such as changes, modifications, substitutions, and variations on the above embodiments within the scope of the present invention.

Claims

1. A method for updating the prototype system firmware of an FPGA platform, characterized in that, The method includes the following steps: S1. Convert the content of the binary firmware to be updated into a format readable by the firmware storage module through Linux commands and embed it into the firmware storage module. Then, through the EDA tool corresponding to the FPGA platform, synthesize, implement, and generate a bitstream file for the Verilog HDL code; S2. Load the bitstream file onto the FPGA platform. After resetting, first send an instruction to read the chip device ID to the Flash chip and receive the device ID information output by the Flash chip, and check whether the device ID information is correct; S3. Send an instruction to enable writing to the Flash chip, and then send an instruction to erase the entire chip. During the erasing process, continuously read the status register to determine whether the chip has completed the erasing operation; S4. Finally, send an instruction to enable writing to the Flash chip, and then send a programming instruction. The content to be programmed is obtained from the firmware storage module. During the programming process, continuously read the status register to determine whether the chip has completed the programming operation.

2. The method for updating the prototype system firmware of the FPGA platform according to claim 1, wherein The FPGA includes a Flash controller module, a firmware storage module, and a TOP control module.

3. The method for updating the prototype system firmware of the FPGA platform according to claim 1, characterized in that, The FPGA platform includes a UART communication module, a Flash controller module, a firmware storage module, and a TOP control module.

4. The method for updating the prototype system firmware of the FPGA platform according to claim 2 or 3, wherein The TOP control module is used to connect internal modules and is used to instruct the Flash controller module, the UART communication module, and the firmware storage module to perform different operations.

5. The method for updating the prototype system firmware of the FPGA platform according to claim 2 or 3, characterized in that, The firmware storage module is implemented through the internal resources of the FPGA, and its storage capacity can be adjusted within the storage resources supported by the FPGA chip to be applicable to firmware of different file sizes.

6. The method for updating the prototype system firmware of the FPGA platform according to claim 2 or 3, characterized in that, The Flash controller module is used to perform different process operations on the Flash chip according to different instruction types transmitted by the TOP control module; including sending instructions, sending instructions - receiving data, sending instructions - sending addresses - receiving data, and / or sending instructions - sending addresses - sending data.

7. The method for updating the prototype system firmware of the FPGA platform according to claim 6, characterized in that, The Flash controller module is used to implement all operation controls on the Flash chip, including: reading and writing registers, erasing, programming, and / or reading stored content.

8. The method for updating the prototype system firmware of the FPGA platform according to claim 3, wherein The communication module is used to interact with the host computer.

9. The method for updating the prototype system firmware of the FPGA platform according to claim 7, wherein After embedding the firmware content into the firmware storage module, a bitstream file is compiled and generated through the EDA tool corresponding to the FPGA. After loading the bitstream file onto the FPGA platform, the operation of updating the firmware is performed.

10. The method for updating the prototype system firmware of the FPGA platform according to any one of claims 1-3, characterized in that, The method is implemented on multiple FPGA models that meet the hardware resource requirements.

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