Platform heterogeneous inter-core communication method and device and communication equipment

Abstract

The invention discloses a platform heterogeneous inter-core communication method and device and communication equipment, and the method comprises the steps: a main processor carries out initialization, and the initialization comprises the steps: determining a shared memory region, dividing the shared memory region into a plurality of cache regions, writing the addresses and use information of the cache regions into a resource table, and storing the resource table into a shared memory; establishing an RPMsg channel with the slave processor in the shared memory through the service announcement message; when communication is needed, determining a cache region which can be used by the to-be-transmitted message according to the resource table; and performing message interaction with the slave processor by using the determined cache region and the RPMsg channel. By means of the scheme, the inter-core communication of the multi-core heterogeneous system can meet the requirements of ecological expansion and development, and secondary development of the system is facilitated.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a method and apparatus for inter-core communication between heterogeneous platforms and a communication device. Background Art

[0002] Currently, with the continuous improvement of the manufacturing processes of various chips, traditional integrated circuit design has evolved from the integration of transistors to the integration of logic gates, and then to IP (Intellectual Property) integration (which refers to integrating multiple IP modules into a chip or system and performing customized design to achieve the required functions and performance), and SoC (System on Chip). Compared with ordinary chips, SoC chips have a high degree of integration and are the future development direction of the chip industry.

[0003] In the SoC of a smart phone, it not only contains a CPU (Central Processing Unit), but also includes modules or subsystems such as a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), and a modem. At the same time, each subsystem has multiple cores. In order to make full use of the high performance of multi-core processors, a communication solution for multiple architectures and multiple systems needs to be provided. That is to say, the cores of different architectures integrated on the same SoC, namely IP Cores (IP cores, which refer to logic functional blocks that can be used to generate ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays)), can all provide communication solutions.

[0004] Some existing IPC (Inter-Process Communication) solutions generally have the following problems: First, with the iterative evolution of SoC, it becomes more and more complex, and the system software requirements are also more and more extensive. Existing IPC cannot take into account the needs of ecological expansion and development. Second, it is not easy to expand the ecosystem and cooperate with downstream partners. Summary of the Invention

[0005] Embodiments of this application provide a method and apparatus for inter-core communication between heterogeneous platforms and a communication device, so that the inter-core communication of a multi-core heterogeneous system can take into account the needs of ecological expansion and development and facilitate the secondary development of the system.

[0006] On the one hand, embodiments of this application provide a method for inter-core communication between heterogeneous platforms, and the method includes:

[0007] The main processor is initialized, and the initialization includes determining a shared memory area, dividing the shared memory area into multiple buffer areas, writing the buffer area addresses and usage information into a resource table, and saving the resource table into the shared memory;

[0008] Establish an RPMsg channel with the slave processor in the shared memory through a service announcement message;

[0009] When communication is required, determine the buffer area that can be used by the message to be transmitted according to the resource table;

[0010] Use the determined buffer area and the RPMsg channel to perform message interaction with the slave processor.

[0011] Optionally, the method further includes: pre-establishing a Mailbox and setting a mailbox controller, where the Mailbox includes an inbox and an outbox of the main processor, and an inbox and an outbox of the slave processor; the mailbox controller is used to transfer the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the main processor to the inbox of the slave processor, and send an interrupt request to the slave processor; transfer the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the slave processor to the inbox of the main processor, and send an interrupt request to the main processor.

[0012] Optionally, the establishing an RPMsg channel with the slave processor in the shared memory through a service announcement message includes:

[0013] Send a service name announcement to the slave processor through a Mailbox interrupt, where the service name announcement includes a service name;

[0014] Receive the service name confirmation sent by the slave processor through the Mailbox interrupt, and determine that the establishment of the RPMsg channel corresponding to the service name is successful.

[0015] Optionally, the method further includes: establishing an RPMsg endpoint corresponding to the RPMsg channel, and the RPMsg endpoint has a unique local address.

[0016] Optionally, the performing message interaction with the slave processor using the determined buffer area and the RPMsg channel includes:

[0017] When a message needs to be sent, determine the message packet to be sent, where the message packet includes: a message header and a message body; the message header includes: a source address, a destination address, a length, and a flag bit; the source address is the local address of the RPMsg endpoint of the sender, the destination address is the local address of the RPMsg endpoint of the receiver; the length represents the length of the message packet; the flag bit indicates whether the corresponding buffer area is in use;

[0018] Write the message packet into the determined buffer area;

[0019] Send a Mailbox interrupt message to the slave processor, so that the slave processor reads the message packet from the buffer area and obtains the message body information by parsing the message header of the message packet;

[0020] Receive the Mailbox interrupt response message sent by the slave processor, and release the buffer area occupied by the message packet.

[0021] Optionally, the message interaction with the slave processor by using the determined buffer area and the RPMsg channel includes:

[0022] Receive the Mailbox interrupt message sent by the slave processor;

[0023] Determine the buffer area corresponding to the Mailbox interrupt message, and read the message packet from the buffer area;

[0024] After reading the message packet, send a Mailbox interrupt response message to the slave processor, so that the slave processor releases the buffer area occupied by the message packet;

[0025] Parse the message header of the message packet to obtain the message body information.

[0026] Optionally, the sending the Mailbox interrupt message to the slave processor includes: writing the Mailbox interrupt message into the outbox of the main processor; the Mailbox interrupt message includes: message arrival notification, service name, buffer area ID, message packet address; the receiving the Mailbox interrupt response message sent by the slave processor includes: reading the Mailbox interrupt response message in the inbox of the main processor, and the Mailbox interrupt response message includes: message read notification, service name, buffer area ID, message packet address.

[0027] Optionally, the mailbox controller works in an independent thread.

[0028] Optionally, the method further includes:

[0029] Establish a receiving callback function corresponding to the RPMsg endpoint;

[0030] After obtaining the message body information, execute the receiving callback function according to the message body information.

[0031] On the other hand, an embodiment of the present application further provides a platform heterogeneous inter-core communication device, and the device includes: a main processor, one or more slave processors, and a shared memory;

[0032] The main processor is used for initialization, and the initialization includes determining a shared memory area, dividing the shared memory area into multiple buffer areas, writing the buffer area addresses and usage information into a resource table, and saving the resource table into the shared memory; establishing an RPMsg channel with the slave processor in the shared memory through a service announcement message; when communication is needed, determining the buffer areas that can be used by the message to be transmitted according to the resource table; and performing message interaction with the slave processor by using the determined buffer areas and the RPMsg channel.

[0033] Optionally, the main processor is further used for pre-establishing a Mailbox and setting a mailbox controller, where the Mailbox includes an inbox and an outbox of the main processor, and an inbox and an outbox of the slave processor; the mailbox controller is used for transferring a Mailbox interrupt message or a Mailbox interrupt response message in the outbox of the main processor to the inbox of the slave processor, and sending an interrupt to the slave processor; and transferring a Mailbox interrupt message or a Mailbox interrupt response message in the outbox of the slave processor to the inbox of the main processor, and sending an interrupt to the main processor.

[0034] Optionally, the main processor and the slave processor are further respectively used for establishing a receive callback function corresponding to the RPMsg endpoint; after obtaining the message body information, executing the receive callback function according to the message body information.

[0035] On the other hand, an embodiment of the present application further provides a communication device, including the platform heterogeneous inter-core communication device described above.

[0036] On the other hand, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the steps of the platform heterogeneous inter-core communication method described above are executed.

[0037] On the other hand, an embodiment of the present application further provides a computer program product, including a computer program and / or instructions, and when the computer program / instructions are executed by a processor, the steps of the platform heterogeneous inter-core communication method described above are implemented.

[0038] The platform heterogeneous inter-core communication method, device, and communication device provided by the embodiments of the present application are directed to a multi-core heterogeneous system, based on the standard OpenAMP (asymmetric multi-processing inter-core communication framework) architecture, and optimizing it, using shared memory to implement IPC communication, and can provide a unified interface for upper-layer applications, facilitating secondary development of the system.

[0039] Furthermore, encapsulating the message to be transmitted into a unified format facilitates the interaction of various types of messages between cores.

[0040] Furthermore, through the optimization of memory management and the adoption of Mailbox interrupts, the complete decoupling of memory access between the AP (Application Processor) and the CP (Communication Processor) can be achieved, facilitating the ecological expansion of the system and downstream cooperation. Description of the Drawings

[0041] Figure 1 is a flowchart of a platform heterogeneous inter-core communication method provided by an embodiment of the present application;

[0042] Figure 2 is a schematic structural diagram of the information stored in the buffer area in an embodiment of the present application;

[0043] Figure 3 is a schematic diagram of the data reading and writing process in the buffer area of the virtual ring structure in an embodiment of the present application;

[0044] Figure 4 is a schematic diagram of the structure of the Mailbox and the working process of the mailbox controller in an embodiment of the present application;

[0045] Figure 5 is a schematic structural diagram of the platform heterogeneous system applied in an embodiment of the present application;

[0046] Figure 6 is a schematic structural diagram of a platform heterogeneous inter-core communication device provided by an embodiment of the present application. Detailed Embodiments

[0047] To make the above objects, features, and beneficial effects of the present application more obvious and understandable, the following detailed description of the specific embodiments of the present application will be given with reference to the accompanying drawings.

[0048] OpenAMP is an open-source architecture mainly used to manage devices based on heterogeneous microprocessor systems. Its core goal is to simplify efficient communication between multi-processor systems and provide a cross-platform, scalable, and flexible solution.

[0049] OpenAMP is mainly based on the following key technologies and protocols:

[0050] Remoteproc (Remote Processor) subsystem: It provides the ability to start, stop, and manage remote processors, enabling different processors in a heterogeneous system to work together.

[0051] RPMsg (Remote Processor Messaging): A lightweight messaging mechanism for low-latency, high-performance data transfer between processors. Rpmsg supports dynamic channel creation, making inter-process communication more flexible.

[0052] VirtIO (Virtual IO Interface): Based on the vring (virtual ring) interface in the Linux kernel, it realizes two-way communication buffer management, reducing the CPU burden and improving communication efficiency.

[0053] PAL (Platform Abstraction Layer): Provides a set of APIs (Application Programming Interface), hiding the complexity of the underlying hardware and enabling OpenAMP to run seamlessly on different platforms.

[0054] The embodiments of this application provide a platform heterogeneous core intercommunication method, device, and communication equipment. By optimizing the standard OpenAMP framework, a unified interface is provided for upper-layer applications, facilitating the invocation of upper-layer applications. Unified management of shared memory is achieved on the main processor side, and complete decoupling of memory access between the AP and CP sides is realized, meeting the application requirements of multi-architecture and multi-system.

[0055] As Figure 1 shown, it is a flowchart of the platform heterogeneous core intercommunication method provided by the embodiments of this application, including the following steps:

[0056] Step 101, the main processor performs initialization, and the initialization includes determining the shared memory area, dividing the shared memory area into multiple buffer areas, writing the buffer area address and usage information into the resource table, and saving the resource table into the shared memory.

[0057] The resource table may also include system version information, some necessary parameters set, etc., and the embodiments of this application do not limit this.

[0058] It should be noted that different buffer areas can correspond to different services. The buffer area adopts a Vring (virtual ring) structure, and each buffer area corresponds to an ID for identifying the buffer area.

[0059] Step 102, the main processor and the slave processor establish an RPMsg channel in the shared memory through a service announcement message.

[0060] In some embodiments, the main processor and the slave processor can be processors based on different operating systems.

[0061] The establishment of the RPMsg channel can be initiated by the main processor, and the establishment process of the RPMsg channel is as follows:

[0062] (1) The main processor sends a service name announcement to the slave processor, and the service name announcement includes a service name, for example, the service name is A;

[0063] (2) After receiving the service name announcement, the slave processor records the service name; then it sends a service name confirmation to the main processor.

[0064] (3) Correspondingly, the main processor receives the service name confirmation sent by the slave processor and determines that the establishment of the RPMsg channel corresponding to the service name is successful.

[0065] It should be noted that the service name announcement and the service name confirmation can be sent but are not limited to by means such as Mailbox interrupts, and the embodiments of the present application do not make limitations in this regard.

[0066] After the establishment of the RPMsg channel, the main processor and the slave processor can also respectively establish RPMsg endpoints corresponding to the RPMsg channel, and the RPMsg endpoints have unique local addresses, so as to identify the sender and receiver of the message when the main and slave processors perform message interaction.

[0067] After the establishment of the RPMsg channel, the main and slave processors can use the RPMsg channel to perform message interaction.

[0068] Step 103, when the main processor and the slave processor need to communicate, determine the buffer that the message to be transmitted can use according to the resource table.

[0069] As mentioned above, different buffers can correspond to different services. The main processor can set the service types corresponding to each buffer. For example, it can be pre-agreed with the slave processor, or mark the service type corresponding to each buffer in the resource table.

[0070] Correspondingly, whether the communication is initiated by the main processor actively or by the slave processor actively, the buffer that can be used for the current service can be selected according to the resource table.

[0071] Step 104, use the determined buffer and the RPMsg channel to perform message interaction with the slave processor.

[0072] In some embodiments, the message to be sent can be encapsulated into a unified structure, and for the convenience of description, it is called a message packet.

[0073] For example, in a non-limiting embodiment, the message packet may include a message header and a message body. Among them, the message header may include: source address (src), destination address (dst), length (len), and flag bits (flags); the source address is the local address of the RPMsg endpoint of the sender, and the destination address is the local address of the RPMsg endpoint of the receiver; the length represents the length of the message packet; the flag bits indicate whether the corresponding buffer is in use. The message body is the message content to be sent, such as data, control information, etc.

[0074] When sending a message, the message packet with the above structure is written into the buffer. As Figure 2 shown, it is a schematic diagram of the structure of the information stored in the buffer in an embodiment of the present application.

[0075] A starting section of the buffer is the information area, and then comes the message packet (or called the RPMsg buffer).

[0076] Among them, the length of the information area is related to the length of the message body to be sent, and the following information is recorded in the information area:

[0077] (1) desc: Records the address, length of each message packet, and the sequence number of the next message packet;

[0078] (2) avail: Records the usage of the buffer by the slave processor, including the sequence number and length of each message packet written by the slave processor;

[0079] (3) used: Records the usage of the buffer by the master processor, including the sequence number and length of each message packet written by the master processor.

[0080] It should be noted that the information recorded in the above information area will be updated synchronously according to the message packets written into the buffer. When the master processor operates on this buffer (such as writing a message packet or releasing a message packet), the master processor completes the information update operation; when the slave processor operates on this buffer, the slave processor completes the information update operation.

[0081] The buffer is a virtual ring structure. As Figure 3 shown, the master processor and the slave processor communicate through a predefined rule using Virtqueue (virtual queue). The master processor packs the messages to be sent and stores them in the virtual ring buffer vring1, and the slave processor reads the message packets from vring1. The slave processor packs the messages to be sent and stores them in the virtual ring buffer vring0, and the master processor reads the message packets from vring0.

[0082] In some embodiments, messages can be sent by means of Mailbox interrupt.

[0083] For example, when the main processor needs to send a message to the slave processor, the interaction process is as follows:

[0084] (1) The main processor determines the message packet to be sent and writes the message packet into the determined buffer.

[0085] (2) The main processor sends a Mailbox interrupt message to the slave processor so that the slave processor reads the message packet from the buffer and obtains the message body information by parsing the message header of the message packet.

[0086] (3) After receiving the Mailbox interrupt message, the slave processor determines the buffer corresponding to the Mailbox interrupt message and reads the message packet from the buffer.

[0087] (4) After reading the message packet, the slave processor sends a Mailbox interrupt response message to the main processor.

[0088] (5) After receiving the Mailbox interrupt response message sent by the slave processor, the main processor releases the buffer occupied by the message packet.

[0089] The interaction process when the slave processor needs to send a message to the main processor is similar to the above and will not be elaborated here.

[0090] In some embodiments, a Mailbox can be established in advance and a mailbox controller can be set, as Figure 4 shown.

[0091] The Mailbox 400 includes an inbox (out_fifo for AP) and an outbox (in_fifo for AP) of the main processor, and an inbox (out_fifo for CP) and an outbox (in_fifo for CP) of the slave processor; the mailbox controller 401 is used to transfer the Mailbox interrupt message mail or the Mailbox interrupt response message in the outbox of the main processor to the inbox of the slave processor and send an interrupt request irq to the slave processor; transfer the Mailbox interrupt message or the Mailbox interrupt response message in the outbox of the slave processor to the inbox of the main processor and send an interrupt request irq to the main processor.

[0092] Referring to Figure 4 taking the main processor sending a Mailbox interrupt message to the slave processor as an example, the process is as follows:

[0093] After the main processor writes the message packet to be sent into the corresponding buffer, it writes the Mailbox interrupt message into the outbox of the main processor; the Mailbox interrupt message may include, but is not limited to, the following information: message arrival notification, service name, buffer ID, message packet address, etc.

[0094] (2) The mailbox controller transfers the above Mailbox interrupt message to the inbox of the slave processor and sends an interrupt request to the slave processor.

[0095] (3) After receiving the interrupt request, the slave processor reads the Mailbox interrupt message in the inbox of the slave processor. According to the Mailbox interrupt message, it reads the message packet sent by the main processor from the corresponding buffer and parses the message packet to obtain the corresponding message.

[0096] (4) After the slave processor reads the message packet, it writes the Mailbox interrupt response message into the outbox of the slave processor; the Mailbox interrupt response message includes: message read notification, service name, buffer ID, message packet address.

[0097] (5) The mailbox controller transfers the above Mailbox interrupt response message to the inbox of the main processor and sends an interrupt request to the main processor.

[0098] (6) After receiving the interrupt request, the main processor reads the Mailbox interrupt response message in the inbox of the main processor. According to the service name, buffer ID, and message packet address indicated by the Mailbox interrupt response message, it releases the buffer occupied by the corresponding message packet.

[0099] It should be noted that the mailbox controller works in an independent thread, so that the main processor, the slave processor, and the mailbox controller can work in independent threads respectively without affecting each other. This can not only improve the flexibility and efficiency of the system, but also completely decouple the memory access of the AP and the CP, facilitating the ecological expansion and downstream cooperation of the system.

[0100] When the aforementioned RPMsg channel is established, the service name announcement sent by the main processor and the service name confirmation sent by the slave processor can also be sent in the form of Mailbox interrupt. The sending process is similar to the sending process of the above messages. The difference is that the message content of the service name announcement and the service name confirmation does not need to be packetized and can be directly written into the outbox of the corresponding process.

[0101] To more clearly illustrate the platform heterogeneous inter-core communication method provided by the embodiments of the present application, Figure 5 FIG. shows the structural schematic diagram of the platform heterogeneous system to which the platform heterogeneous inter-core communication method of the embodiments of the present application is applied.

[0102] Referring to Figure 5 , under the standard OpenAMP framework, SMSG (a message sent by a Mailbox interrupt) and SMEM (shared memory management module) are added. The main processor can use SMEM to implement shared memory management and use SMSG to perform read and write operations on the Mailbox. Among them, the main processor and the slave processor can be processors based on different operating systems. For example, the main processor core can be a Linux OS (operating system), and the slave processor core can be a Baremetal system (a server system directly based on hardware) or an RTOS (Real Time Operate System, real-time operating system), etc.

[0103] It should be noted that there can be one or more slave processors in the platform heterogeneous system, and the main processor can establish an RPMsg channel with each slave processor respectively to achieve message interaction.

[0104] In this embodiment, the main processor is the processor core that controls and initiates communication, and is responsible for managing the entire communication process, including creating, configuring, and closing the RPMsg channel; the slave processor is the processor core that receives and responds to communication. It waits for the request of the main processor and executes corresponding operations. After establishing the RPMsg channel, both the main processor and the slave processor can actively send messages to each other.

[0105] The platform heterogeneous inter-core communication method provided by the embodiment of the present application is based on the standard OpenAMP framework and optimizes it. It realizes the unified management of shared memory through SMEM, and sends Mailbox interrupts through SMSG, thereby realizing communication between different cores. The main processor and the slave processor can also provide one or more different applications for users. For example, the main processor and the slave processor respectively establish receive callback functions corresponding to the RPMsg endpoints, and after obtaining the message body information sent by the other party, execute the receive callback function according to the message body information. The receive callback function can be defined by the user, and the embodiment of the present application does not make any limitations in this regard. Moreover, using the OpenAMP framework, a unified interface can also be provided for upper-layer applications, which is convenient for upper-layer applications to call and is also convenient for secondary development.

[0106] Correspondingly, the embodiment of the present application also provides a platform heterogeneous inter-core communication device, as Figure 6 shown, which is a schematic structural diagram of the device.

[0107] The platform heterogeneous inter-core communication device 600 includes: a main processor 601, one or more slave processors 602, and a shared memory 603. Among them:

[0108] The main processor 601 is used for initialization, and the initialization includes determining a shared memory area, dividing the shared memory area into multiple buffer areas, writing the buffer area addresses and usage information into a resource table, and saving the resource table into the shared memory 603; establishing an RPMsg channel in the shared memory with the slave processor 602 through a service announcement message; when communication is required, determining the buffer areas that can be used by the message to be transmitted according to the resource table; and performing message interaction with the slave processor 602 by using the determined buffer areas and the RPMsg channel.

[0109] In some embodiments, the main processor 600 is further used for pre-establishing a Mailbox and setting a mailbox controller, where the Mailbox includes an inbox and an outbox of the main processor, as well as an inbox and an outbox of the slave processor; the mailbox controller is used for transferring the Mailbox interrupt message or the Mailbox interrupt response message in the outbox of the main processor to the inbox of the slave processor, and sending an interrupt to the slave processor; and transferring the Mailbox interrupt message or the Mailbox interrupt response message in the outbox of the slave processor to the inbox of the main processor, and sending an interrupt to the main processor.

[0110] In some embodiments, the main processor 601 and the slave processor 602 can also respectively establish a receive callback function corresponding to the RPMsg endpoint; after obtaining the message body information, execute the receive callback function according to the message body information.

[0111] Correspondingly, an embodiment of the present application further provides a communication device, which is characterized by including the above platform heterogeneous inter-core communication device 600.

[0112] For other related descriptions of the above platform heterogeneous inter-core communication device and the communication device, reference can be made to the relevant descriptions in the corresponding previous embodiments, which will not be elaborated here.

[0113] In specific implementation, the above platform heterogeneous inter-core communication device can correspond to chips with corresponding functions in network devices and / or user devices, such as SOC (System-On-a-Chip), baseband chips, chip modules, etc.

[0114] In specific implementations, for each device and product described in the above embodiments, each module / unit included therein can be a software module / unit, a hardware module / unit, or can be partially a software module / unit and partially a hardware module / unit. For example, for each device and product applied to or integrated into a chip, each module / unit included therein can be implemented in the form of hardware such as circuits. Alternatively, at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated within the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits. For each device and product applied to or integrated into a chip module, each module / unit included therein can be implemented in the form of hardware such as circuits. Different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components of the chip module. Alternatively, at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated within the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits. For each device and product applied to or integrated into a terminal, each module / unit included therein can be implemented in the form of hardware such as circuits. Different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components within the terminal. Alternatively, at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated within the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0115] An embodiment of the present application also discloses a storage medium, which is a computer-readable storage medium, having a computer program stored thereon. When the computer program runs, it can execute Figure 1 some or all of the steps of the platform heterogeneous core-to-core communication method shown in

[0116] The storage medium can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, etc. The storage medium can also include a non-volatile memory or a non-transitory memory, etc. Figure 1 An embodiment of the present application also discloses a computer program product, including a computer program / instructions. When the computer program and / or instructions are executed by a processor, they implement

[0117] It should be understood that the term "and / or" in this text is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text indicates that the associated objects before and after are in an "or" relationship.

[0118] In the embodiments of this application, "a plurality of" means two or more.

[0119] In the embodiments of this application, the descriptions such as first and second are only for illustration and to distinguish the described objects, without an order, and do not represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation to the embodiments of this application.

[0120] In the embodiments of this application, "connection" refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and this application does not make any limitation on this.

[0121] It should be understood that in various embodiments of this application, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0122] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner.

[0123] In several embodiments provided in the present application, it should be understood that the disclosed methods, apparatuses, and devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the apparatuses or units can be in electrical, mechanical, or other forms.

[0124] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, the functional units in each embodiment of the present application can be integrated in a processing unit, or each unit can be physically arranged separately, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of a combination of hardware and software functional units.

[0126] The above integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above software functional units stored in a storage medium include several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute some steps of the methods described in each embodiment of the present application.

[0127] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A platform heterogeneous inter-core communication method, characterized in that, The method includes: The main processor performs initialization, and the initialization includes determining a shared memory area, dividing the shared memory area into multiple buffer areas, writing the buffer area addresses and usage information into a resource table, and saving the resource table into the shared memory; Establish an RPMsg channel with the slave processor in the shared memory through a service announcement message; When communication is needed, determine the buffer area that can be used by the message to be transmitted according to the resource table; Use the determined buffer area and the RPMsg channel to perform message interaction with the slave processor.

2. The method according to claim 1, wherein The method further includes: Pre-establish a Mailbox and set a mailbox controller. The Mailbox includes an inbox and an outbox of the main processor, and an inbox and an outbox of the slave processor; the mailbox controller is used to transfer the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the main processor to the inbox of the slave processor, and send an interrupt request to the slave processor; transfer the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the slave processor to the inbox of the main processor, and send an interrupt request to the main processor.

3. The method according to claim 1, wherein The establishing an RPMsg channel with the slave processor in the shared memory through a service announcement message includes: Send a service name announcement to the slave processor through a Mailbox interrupt, and the service name announcement includes a service name; Receive the service name confirmation sent by the slave processor through the Mailbox interrupt, and determine that the establishment of the RPMsg channel corresponding to the service name is successful.

4. The method according to claim 2, wherein The method further includes: Establish an RPMsg endpoint corresponding to the RPMsg channel, and the RPMsg endpoint has a unique local address.

5. The method according to claim 4, wherein The using the determined buffer area and the RPMsg channel to perform message interaction with the slave processor includes: When a message needs to be sent, determine a message packet to be sent. The message packet includes: a message header and a message body; the message header includes: a source address, a destination address, a length, and a flag bit; the source address is the local address of the RPMsg endpoint of the sender, and the destination address is the local address of the RPMsg endpoint of the receiver; the length represents the length of the message packet; the flag bit indicates whether the corresponding buffer area is in use; Write the message packet into the determined buffer area; Send a Mailbox interrupt message to the slave processor, so that the slave processor reads the message packet from the buffer area and obtains the message body information by parsing the message header of the message packet; Receive the Mailbox interrupt response message sent by the slave processor, and release the buffer area occupied by the message packet.

6. The method according to claim 5, wherein The using the determined buffer area and the RPMsg channel to perform message interaction with the slave processor includes: Receive the Mailbox interrupt message sent by the slave processor; Determine the buffer area corresponding to the Mailbox interrupt message, and read the message packet from the buffer area; After reading the message packet, send a Mailbox interrupt response message to the slave processor, so that the slave processor releases the buffer area occupied by the message packet; Parse the message header of the message packet to obtain the message body information.

7. The method according to claim 5, wherein Sending the Mailbox interrupt message to the slave processor includes: Writing the Mailbox interrupt message into the outbox of the master processor; the Mailbox interrupt message includes: message arrival notification, service name, buffer ID, message packet address; Receiving the Mailbox interrupt response message sent by the slave processor includes: Reading the Mailbox interrupt response message in the inbox of the master processor, the Mailbox interrupt response message includes: message read notification, service name, buffer ID, message packet address.

8. The method according to claim 2, wherein The mailbox controller works with an independent thread.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Establishing a receive callback function corresponding to the RPMsg endpoint; After obtaining the message body information, execute the receive callback function according to the message body information.

10. An inter-core communication device for platform heterogeneous cores, characterized in that, The device includes: a master processor, one or more slave processors, and shared memory; The master processor is used for initialization, and the initialization includes determining the shared memory area, dividing the shared memory area into multiple buffers, writing the buffer address and usage information into the resource table, and saving the resource table into the shared memory; establishing an RPMsg channel with the slave processor in the shared memory through a service announcement message; when communication is required, determining the buffer that the message to be transmitted can use according to the resource table; and performing message interaction with the slave processor by using the determined buffer and the RPMsg channel.

11. The platform heterogeneous inter-core communication device according to claim 10, wherein The master processor is further used for pre-establishing a Mailbox and setting a mailbox controller, the Mailbox includes the inbox and outbox of the master processor, and the inbox and outbox of the slave processor; the mailbox controller is used for transferring the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the master processor to the inbox of the slave processor, and sending an interrupt to the slave processor; transferring the Mailbox interrupt message or Mailbox interrupt response message in the outbox of the slave processor to the inbox of the master processor, and sending an interrupt to the master processor.

12. The platform heterogeneous inter-core communication device according to claim 10 or 11, wherein The master processor and the slave processor are further respectively used for establishing a receive callback function corresponding to the RPMsg endpoint; after obtaining the message body information, execute the receive callback function according to the message body information.

13. A communication device, characterized in that, Including the platform heterogeneous inter-core communication device according to any one of claims 10 to 12.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run by a processor, it executes the steps of the platform heterogeneous inter-core communication method according to any one of claims 1 to 9.

15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program and / or instruction is executed by a processor, it implements the steps of the platform heterogeneous inter-core communication method according to any one of claims 1 to 9.

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