Capacitance measuring device and method for capacitor array in chip

Abstract

The invention relates to a capacitance measuring device and a capacitance measuring method for a capacitor array in a chip, which are characterized in that a traditional capacitance measuring circuit is optimally designed, a differential capacitance measuring technology based on vertical and horizontal line mutual capacitance is adopted, and the tolerance between every two mutual capacitances is processed and analyzed, so that the capturing capability of tiny capacitance change is improved. Excitations with opposite phases are applied to adjacent emission electrodes, the capacitance difference is extracted according to the current cancellation principle, the influence of circuit device process deviation and environment temperature drift is effectively eliminated, nA-magnitude composite current signals are converted into voltage through a differential capacitance measurement module, direct-current offset is eliminated in combination with high-pass and low-pass filtering, and the high-pass filtering and low-pass filtering are combined. The signal stability under high gain is ensured; the frequency domain signal processing module is used for extracting the amplitude and phase of excitation, converting an analog signal into a digital signal, and reducing the noise influence to the minimum so as to generate a high-entropy key, so that the measurement result is high in robustness and accuracy, and the anti-interference capability is relatively strong.

Description

Technical Field

[0001] The invention belongs to the technical field of physical unclonable function measurement in chips, and relates to a capacitance measurement device and method for a capacitance array in a chip. Background Art

[0002] The security measurement technology based on Strong-SC-PUF is a secure and reliable Strong PUF (Physical Unclonable Function) circuit Strong-SC-PUF proposed based on switched capacitor (SC). It uses excitation to select and configure in two identical capacitors at the Nth level, and uses LSSA (Least Squares Spectral Analysis) to sample the total capacitance deviation of the circuit and convert it into a digital response, thereby providing a large number of challenge-response pairs (CRPs), and having good uniqueness and bias. At the same time, it adopts a reliability enhancement strategy of built-in self-test (BIST), which can automatically test and select the PUF output with a large capacitance deviation. The selected output achieves very high reliability and no longer requires an expensive error correction mechanism. However, this technology uses the BIST strategy to increase the complexity of circuit design and the overall test time, and its anti-interference ability needs to be improved in the face of non-invasive attacks such as electromagnetic interference. Summary of the Invention

[0003] Aiming at the problems existing in the above-mentioned traditional technologies, the present invention proposes a capacitance measurement device for a capacitance array in a chip and a capacitance measurement method for a capacitance array in a chip, which can maintain the high robustness and accuracy of measurement results and improve the anti-interference ability.

[0004] In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions: On the one hand, a capacitance measurement device for a capacitance array in a chip is provided, including a microcontroller, a capacitance array of a chip to be measured, a differential capacitance measurement module, and a frequency domain signal processing module; the capacitance array includes a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrode and the receiving electrode corresponds to a capacitance; Synchronous amplitude-matched and phase-opposite excitation signals are respectively input to every two adjacent transmitting electrodes of the capacitance array through the differential capacitance measurement module, a composite current signal generated on the common receiving electrode of every two adjacent transmitting electrodes of the capacitance array is obtained and converted into a measurement signal in voltage form, and after ADC sampling of the measurement signal by the frequency domain signal processing module, a fast Fourier transform is performed, and the capacitance tolerance of every two capacitors of the capacitance array is extracted from the measurement signal as a characteristic parameter of the capacitance array. The microcontroller is used to control the generation of the excitation signal of the differential capacitance measurement module and generate a PUF identifier of the chip to which the capacitance array belongs according to the characteristic parameter.

[0005] In one embodiment, the differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is respectively connected to each transmitting electrode of the capacitor array through the first low-pass filter and the fully differential amplifier in sequence. The input terminals of the junction field effect transistor transimpedance amplifier are respectively connected to each receiving electrode of the capacitor array. The output terminal of the junction field effect transistor transimpedance amplifier is connected to the frequency domain signal processing module through the high-pass filter, the AC amplifier, and the second low-pass filter in sequence. The dual-channel DAC circuit is used to generate synchronous excitation signals with amplitude matching and opposite phases.

[0006] In one embodiment, the frequency domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a bi-phase lock-in amplifier connected in sequence. The input terminal of the successive approximation register ADC chip is connected to the differential capacitance measurement module for ADC sampling of the measurement signal. The discrete Fourier transform circuit and the bi-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller calculates the tolerance using the amplitude and phase information.

[0007] In one embodiment, the capacitance measurement device of the capacitor array in the above chip further includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module. The input terminals of the transmitting electrode integrity detection module are respectively connected to each transmitting electrode of the capacitor array, and the output terminal of the transmitting electrode integrity detection module is connected to the microcontroller. The input terminals of the receiving electrode integrity detection module are respectively connected to each receiving electrode of the capacitor array, and the output terminal of the receiving electrode integrity detection module is connected to the microcontroller. The transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrodes of the capacitor array, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrodes of the capacitor array.

[0008] On the other hand, a capacitance measurement method for a capacitor array in a chip is also provided, including the steps of: Construct a capacitor array on the printed circuit board where the chip to be measured is located through orthogonal wiring on the top layer and the bottom layer; Input synchronous excitation signals with amplitude matching and opposite phases to every two adjacent transmitting electrodes of the capacitor array through the differential capacitance measurement module, and obtain the composite current signal generated on the common receiving electrode of every two adjacent transmitting electrodes and convert it into a voltage-form measurement signal; Perform fast Fourier transform on the measurement signal after ADC sampling through the frequency domain signal processing module, and extract the tolerance of every two capacitors in the capacitor array as the characteristic parameter of the capacitor array; the characteristic parameter is used to generate the PUF identifier of the chip to which the capacitor array belongs.

[0009] One of the above technical solutions has the following advantages and beneficial effects: In the capacitance measurement device and method of the capacitance array in the above chip, by optimizing the design of the traditional capacitance measurement circuit and adopting the differential capacitance measurement technology based on the mutual capacitance of vertical and horizontal lines, the tolerance between every two mutual capacitances is processed and analyzed to improve the ability to capture minute capacitance changes. By applying excitation signals with opposite phases to adjacent emission electrodes and using the principle of current cancellation to extract capacitance differences, the influence of process deviations of circuit devices and environmental temperature drift is effectively eliminated. The differential capacitance measurement module converts the composite current signal in the nA range into a voltage, and combines high-pass and low-pass filtering to eliminate DC offset to ensure signal stability at high gain. The frequency-domain signal processing module extracts the amplitude and phase of the excitation, converts the analog signal into a digital signal, minimizes the influence of noise, generates a high-entropy key, and has high robustness and accuracy of measurement results and strong anti-interference ability. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0011] Figure 1 It is a schematic diagram of the module architecture of the capacitance measurement device of the capacitance array in a chip in an embodiment; Figure 2 It is a schematic diagram of the layout of a 16×16 capacitance network in an embodiment; Figure 3 It is a schematic diagram of a simplified 2×2 capacitance model in an embodiment; Figure 4 It is a schematic diagram of a differential capacitance measurement system in an embodiment; Figure 5 It is a block diagram of the peripheral circuit of XC7Z020 in an embodiment; Figure 6 It is a schematic diagram of the generation and preprocessing of an excitation signal in an embodiment; Figure 7 It is a schematic diagram of a fully differential amplifier circuit in an embodiment; Figure 8 For an embodiment of I RX Schematic diagram of current-to-voltage processing; Figure 9 It is a schematic diagram of the implementation of a JFET-TIA circuit in an embodiment; Figure 10Schematic diagram of voltage signal filtering and amplification in an embodiment; Figure 11 Schematic diagram of mV-level signal amplification circuit in an embodiment; Figure 12 Simplified block diagram of the (SAR) ADC circuit in an embodiment; Figure 13 Schematic diagram of the full link of the measurement circuit in an embodiment; Figure 14 For an embodiment of I RX Simplified schematic diagram of current-to-voltage conversion processing; Figure 15 Schematic diagram of the overall circuit architecture of the capacitance measurement device for the capacitance array in the chip in an embodiment; Figure 16 Schematic diagram of the flow of the capacitance measurement method for the capacitance array in the chip in an embodiment. Detailed implementation manners

[0012] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0013] It should be noted that referring to "embodiment" herein means that the specific features, structures or characteristics described in combination with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0014] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0015] Although the current PUF measurement technology continues to develop in terms of stability and accuracy, it still faces many challenges. The following analyzes the defects of the prior art from a technical perspective and explains how the present invention will solve these problems in a causal reasoning manner. (1) Environmental sensitivity leads to insufficient stability because it relies on physical parameters such as delay time, power consumption, and current waveform (such as SRAM PUF, oscillator PUF, thermal noise PUF, etc.) for measurement, which is greatly affected by temperature, voltage fluctuations and electromagnetic interference. The consequence is that the characteristic value is poorly stable, and a dynamic compensation algorithm (such as real-time temperature-voltage feedback) is required to maintain response consistency. Defect summary: poor environmental sensitivity, insufficient CRP stability, and the need for additional compensation mechanisms.

[0016] (2) The measurement accuracy is limited. The reason is that the traditional measurement circuit design method is limited by chip performance and environmental noise, and it is difficult to achieve fast and high-precision measurement of fF (femtofarad) level capacitance. The consequence is that it cannot meet the parallel detection requirements of tiny capacitors. Defect summary: The measurement accuracy is limited, which limits the application of PUF in high-security chips. (3) Dependence on error correction mechanism. The reason is that the measurement accuracy is not enough and it needs to rely on expensive error correction mechanism (such as error correction code ECC). The consequence is to increase the complexity and resource overhead of the system and affect the effect. Defect summary: The error correction cost is high and it is not suitable for resource-constrained scenarios (such as IoT devices).

[0017] Based on the existing technology, the present invention combines intelligent detection and PUF optimization to propose a new high-precision measurement solution: a multi-layer electrode network (including transmitting electrodes TX and receiving electrodes RX) is constructed through the PCB where the chip is located, and tiny capacitors are formed between the electrodes. The mutual capacitance of each electrode pair has subtle and non-replicable differences, which are unique and unpredictable. The differential capacitance measurement method is adopted, that is, adjacent TX electrodes are applied with excitation signals of opposite phases, and reverse currents are generated on the RX electrodes, which effectively eliminates the influence of circuit device process deviations and ambient temperature drifts. A digital two-phase lock-in amplifier is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, realize digital signal processing, and minimize the influence of noise to generate a high-entropy key. Some professional terms are explained as follows: PUF: Short for physical unclonable functions, the most commonly used hardware security primitive (basic component), similar to human fingerprints, extracts information such as material or chip processing deviations to form information unique to a single entity, which is used in cryptographic applications such as root key protection or authentication.

[0018] Nano Composite Film: A multi-layer composite packaging structure composed of high dielectric materials, conductive shielding layer, and intelligent sensing layer. It is mainly used to improve the physical security of the chip and prevent reverse engineering attacks.

[0019] High-K Dielectric Material: A material with a relatively high dielectric constant, which can be used to form a packaging structure with resistance to FIB analysis and high capacitance density, thereby improving the chip protection ability.

[0020] Random Dielectric Property Composite Film: It refers to a composite film formed by randomly embedding one or more particles with different dielectric properties in a substrate. The microscopic structures such as the shape, size, volume fraction, orientation, and distribution of the heterogeneous particles will affect the dielectric properties of the composite film, presenting typical dielectric property texture features such as resistance and capacitance.

[0021] Challenge-Response Pair CRP: The information input to the PUF (such as a capacitor array) is called a challenge, and the information output from the PUF is called a response. The two are collectively referred to as a challenge-response pair.

[0022] Built-in Self Test (BIST): A technology that implants relevant functional circuits in a circuit during design to provide a self-test function, thereby reducing the dependence of device testing on automatic test equipment. BIST is a DFT (Design for Testability) technology that can be applied to almost all circuits and is therefore widely used in the semiconductor industry.

[0023] Trans-impedance amplifier (TIA): A circuit that converts a weak current signal into a voltage signal. It has a negative feedback resistor and can be simply regarded as an inverting amplifier.

[0024] Dual-phase lock-in amplifier: Designed to solve the problem that the phase difference of a lock-in amplifier affects the measurement accuracy, it is convenient for accurately extracting the phase of the input signal. Its basic structure includes two parallel lock-in amplifiers. After filtering, it can obtain an output signal and a phase difference value that are not affected by the phase difference.

[0025] In one embodiment, such as Figure 1As shown in the figure, a capacitance measurement device for a capacitance array in a chip is provided, including a microcontroller 11, a capacitance array 12 of a chip to be measured, a differential capacitance measurement module 13, and a frequency-domain signal processing module 14. The capacitance array 12 includes a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrodes and the receiving electrodes corresponds to a capacitance. The differential capacitance measurement module 13 inputs synchronous excitation signals with matching amplitudes and opposite phases to every two adjacent transmitting electrodes of the capacitance array 12, acquires the composite current signals generated on the receiving electrodes common to every two adjacent transmitting electrodes of the capacitance array 12, and converts them into measurement signals in voltage form. The frequency-domain signal processing module 14 performs a fast Fourier transform on the measurement signals after ADC sampling, and extracts the tolerance of every two capacitances of the capacitance array 12 as the characteristic parameters of the capacitance array 12. The microcontroller 11 is used to control the generation of the excitation signals of the differential capacitance measurement module 13, and generate the PUF identifier of the chip to which the capacitance array 12 belongs according to the characteristic parameters.

[0026] It can be understood that 16×16 capacitance networks (16 TX electrodes and 16 RX electrodes) are constructed on a printed circuit board through orthogonal wiring of the TOP (the top layer of the printed circuit board, that is, the component side) and BOTTOM (the bottom layer of the printed circuit board, opposite to the TOP layer), and the simplified diagram of the network is as Figure 2 shown.

[0027] For the convenience of explaining the measurement object of the detection board, a simplified 2×2 capacitance network model is taken as an example for illustration, as Figure 3 shown in the schematic diagram of the simplified 2×2 capacitance network model, which is composed of two orthogonal TX electrodes and RX electrodes. There are the following three capacitance-related parameters in the 2×2 capacitance network model: (1) Mutual capacitance C m . According to the principle of parallel-plate capacitance, there will be a capacitance at each intersection point between each orthogonal TX electrode and RX electrode, which is called mutual capacitance (denoted as C m ). For the convenience of distinction, the capacitance between the TX1 electrode and the RX1 electrode can be marked as C 1,1 , and so on. There are C 1,1 , C 2,1 , C 1,2 and C 2,2 four mutual capacitances in the simplified 2×2 capacitance network model. The subscript R of TX 1R and RX 1R represents redundancy or multiplexing.

[0028] (2) The tolerance ΔC between mutual capacitances. Due to the unpredictability and uncontrollability of the manufacturing process, there will be differences between every two capacitors. By obtaining these capacitance differences, they can be used as characteristic parameters of the chip. However, due to the very small capacitance values and various noise effects, the measurement of a single capacitor is difficult for subsequent processing. In this embodiment, the differential capacitance measurement method is adopted. The capacitance difference caused by the difference between every two mutual capacitances is defined as the tolerance ΔC. For an n×n capacitance network, there will be n 2 pieces of ΔC information. By extracting the information of n 2 pieces of ΔC through the measurement system, they can be used as the characteristic parameters of the chip.

[0029] (3) Equivalent capacitance Cs. Each electrode has an equivalent capacitance (denoted by Cs) to the grounded shield.

[0030] In summary, the 16×16 capacitance network provides a total of 128 tolerances ΔC. The measurement target of the packaged detection board is to measure ΔC, and the resolution design index is 1 fF. The detection principle is as follows: As Figure 4 shown, since the measurement circuit is essentially insensitive to parasitic resistors and capacitances, in this embodiment, the ΔC measurement is realized through two excitation signals with amplitude matching and 180° phase difference, which can resolve capacitance changes in the fF order of magnitude, and then combined with the corresponding digital signal processing chain to complete the precise digitization of the PUF.

[0031] The capacitance measurement device of the capacitance array in the above chip optimizes the design of the traditional capacitance measurement circuit, adopts the differential capacitance measurement technology based on the mutual capacitance of horizontal and vertical lines, processes and analyzes the tolerance between every two mutual capacitances to improve the ability to capture tiny capacitance changes. By applying excitation signals with opposite phases to adjacent transmitting electrodes, the capacitance difference is extracted using the current cancellation principle, effectively eliminating the influence of circuit device process deviations and environmental temperature drift. The differential capacitance measurement module 13 converts the composite current signal in the nA order of magnitude into a voltage, and combines high-pass and low-pass filtering to eliminate the DC offset to ensure the signal stability under high gain; the frequency-domain signal processing module 14 extracts the amplitude and phase of the excitation, converts the analog signal into a digital signal, minimizes the influence of noise to generate a high-entropy key, and the measurement results have high robustness and accuracy and strong anti-interference ability.

[0032] It should be noted that in addition to the control ability, the microcontroller 11 also needs to have a certain algorithm processing ability. The existing embedded SOC device XC7Z020 can be selected as the required microcontroller 11. As Figure 5 shown, its peripheral circuit mainly includes a power supply circuit, a clock circuit, a reset circuit, a loading unit, an external storage unit, a UART interface, a status indication and a temperature monitoring unit, etc. The microcontroller 11 with the required functions can be obtained by making adaptive configurations according to the above control and processing requirements.

[0033] In one embodiment, the differential capacitance measurement module 13 includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter. The dual-channel DAC circuit is sequentially connected to each transmitting electrode of the capacitance array 12 through the first low-pass filter and the fully differential amplifier. The input terminals of the junction field effect transistor transimpedance amplifier are respectively connected to each receiving electrode of the capacitance array 12, and the output terminal of the junction field effect transistor transimpedance amplifier is sequentially connected to the frequency domain signal processing module 14 through the high-pass filter, the AC amplifier, and the second low-pass filter. The dual-channel DAC circuit is used to generate synchronous excitation signals with amplitude matching and opposite phases.

[0034] It can be understood that in the differential capacitance measurement module 13, the high-frequency components in the output of the dual-channel DAC circuit are removed by a two-stage low-pass filter, and then a fully differential amplifier provides sufficient amplitude matching for the signal output by the DAC. The two signals output by the fully differential amplifier are respectively applied to the fixed electrodes TX1 and TX2 of the differential detection capacitance on the capacitance array, and then a composite current I is generated on the common electrode RX1 of TX1 and TX2. RX , using a JEFT-TIA circuit (i.e., a junction field effect transistor transimpedance amplifier) to automatically implement the measurement of current to voltage, and the composite current I RX After being converted into a voltage output signal, it is filtered and amplified by a high-pass filter and an AC amplifier, and then preprocessed and transmitted to the frequency domain signal processing module 14. Through the frequency domain signal processing module 14, the analog signal is converted into a digital signal. For the extracted digital signal, the amplitude and phase information can be extracted from the signal using the discrete Fourier transform and the bi-phase lock-in amplifier, so as to analyze the characteristic information △C of the 16×16 network according to the existing tolerance calculation algorithm.

[0035] Generation and preprocessing of dual-channel excitation signals: As Figure 6 shown, the dual-channel synchronous excitation signals can be implemented by a dual-channel DAC circuit (such as a 24-bit DAC device). This circuit is an audio stereo DAC with a PLL, 32 bits, and 384 kHz, and this DAC device can control the out-of-band noise at a relatively low level of 20 dB, thereby reducing EMI and aliasing in the downstream amplifier / ADC. Two synchronous excitation signals with amplitude matching and opposite phases are generated by the DAC device (amplitude imbalance or phase error will cause an offset in the extracted PUF data), and then the high-frequency components in the DAC output are removed by a two-stage low-pass filter.

[0036] The signal output by the low-pass filter cannot provide sufficient amplitude matching, so a fully differential amplifier is needed to amplify the excitation signal. The circuit schematic is as Figure 7As shown. By setting the values of resistor RG and resistor RF, the required signal amplitude can be obtained. Resistors RG and RF need to be selected as high-precision and low-temperature-drift resistors. Although the fully differential amplifier can provide sufficient amplitude matching, the imbalance at the differential output will affect the measurement. According to experience, it can be known that the imbalance of the TX signal is at least one order of magnitude smaller than △C / C m 1 ≈1 / 1000 = -60dB. Here, the fully differential amplifier THS4551 can be selected to achieve this. The output balance parameter of this fully differential amplifier is 85dB@VOUT = ±1V, ensuring sufficient signal quality for subsequent measurements. Among them, C m 1 is the capacitance value of a single mutual capacitance, VP and VN are differential input signals, VOCM is the common-mode voltage input, and VOUT+ and VOUT- are differential output signals.

[0037] nA (nanoampere)-level current-to-voltage processing: The two signals output by the fully differential amplifier are respectively applied to the fixed electrodes TX1 and TX2 corresponding to the differential detection capacitor, and then a composite current I RX is generated on the common electrode RX1 of TX1 and TX2. The amplitude of the composite current I RX is in the range of nA to sub-nA level. In this embodiment, a JEFT-TIA (junction field effect transistor transimpedance amplifier) circuit is designed to realize the measurement of current to voltage. Its circuit schematic diagram is as Figure 8 shown.

[0038] A composite current I RX with an amplitude of nA level is generated on the common electrode RX. To measure I RX , a high-gain and low-noise amplifier is required. This amplifier must meet the following three requirements: The first is low bias current. Excessive input bias current will shunt the weak measured current I RX and cause the measurement to be inaccurate. Therefore, the bias current of the operational amplifier should be less than or equal to the pA (picoampere) level. The second is low current noise and voltage noise. Since the input signal is current, the operational amplifier also needs to have low current noise and voltage noise. The third is high gain-bandwidth product, because the RX node has a high capacitive load, which will reduce the bandwidth of the amplifier.

[0039] Here, a specific circuit implementation is adopted based on the JFET-TIA circuit. Its entire functional unit consists of a high-gain-bandwidth product operational amplifier (IC1), a low-input-bias JFET (T1), and the remaining peripheral circuit (resistor and capacitor) components. The circuit implementation block diagram is as Figure 9As shown: Resistors R2 and R3 are used to set the DC operating point of the circuit. The feedback capacitor C1 is an NPO-type zero-drift capacitor. Resistor R1 is used to adjust the amplification gain so that the TIA has a gain amplitude of 0.0106 V / A when the excitation frequency ≤ 48 KHz.

[0040] Currents less than a few nA are amplified and converted into voltage by the JFET-TIA circuit, which can provide high gain with extremely low noise. According to Figure 9 the circuit diagram of, the relationship between the output voltage and the input current is deduced. When the junction field effect transistor works in the amplification region, the on-current i D Calculation formula: i D = I DSS × (V GS / V P ) 2 , it is calculated that the output voltage satisfies V OUT = 1.522 + i D × R1 in any case. Among them, I DSS is the saturation drain current, V GS is the gate-source voltage, V P is the pinch-off voltage, and R1 is the resistance value of resistor R1.

[0041] Voltage signal filtering and amplification: After the composite current I RX is converted into a voltage output signal, it is also necessary to pass through a first-order active high-pass filter to strip the DC component in the signal, and then feed the signal into a high-gain amplifier circuit (an AC amplifier with one-stage follower followed by two-stage amplification) to further amplify the signal to the dynamic range of the ADC in the frequency domain signal processing module 14. At the same time, to prevent aliasing during the digitization process, this AC amplifier needs to be implemented as an active first-order low-pass filter, as Figure 10 shown.

[0042] The interference of the first-stage amplification in the AC amplifier plays a major role in the interference of the entire AC amplifier. This is because as long as a slight interference voltage is introduced in the first stage, a relatively large interference voltage will be output in the subsequent stage amplification. Therefore, the first-stage amplification processing is particularly important. In this embodiment, the high-precision operational amplifier OPA189 is selected as the AC amplifier. This high-precision operational amplifier is a device with ultra-low noise, fast stability, and zero drift, providing rail-to-rail output. These functions and excellent AC performance, combined with an offset voltage of only 0.4 µV and a temperature drift of 0.005 µV / °C for the single-channel version, make OPA189 an ideal choice for precision instruments, signal measurement, and active filtering applications. The circuit composition of the mV-level signal AC amplifier is as Figure 11As shown, the specific circuit structure can be understood by referring to the existing circuit description in the same way, and will not be elaborated in this specification.

[0043] In one embodiment, the frequency-domain signal processing module 14 includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a bi-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to the differential capacitance measurement module 13 for ADC sampling of the measurement signal, and the discrete Fourier transform circuit and the bi-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller 11 calculates the tolerance using the amplitude and phase information.

[0044] It can be understood that due to the low output impedance characteristic of the low-pass filter, the signal after sampling preprocessing can be connected to the successive approximation register ADC chip, and the analog-to-digital signal conversion is realized through ADC conversion processing. ADC sampling needs to be synchronized with the DAC output, and the signal is oversampled to reduce noise. Considering factors such as front-end noise, bandwidth, settling time, signal-to-noise ratio, slew rate, spurious-free dynamic range (SFDR), input impedance, and sampling time, the successive approximation register ADC chip can select a low-noise and low-power high-speed 24-bit successive approximation register (SAR) ADC. Its simplified circuit block diagram is as Figure 12 shown, where 24-BIT SAMPLING ADC is the core of the 24-bit sampling ADC, responsible for converting the input analog signal into a 24-bit digital quantity; DIGITAL FILTER is a digital filter used to filter the original digital signal output by the ADC; CONTROL LOGIC is a control logic unit used to manage the working timing of the ADC (such as sampling start and conversion cycle), configure parameters (such as gain and sampling rate), and coordinate the interaction between the internal and external interfaces of the module. IN+ / IN- is the analog input interface, V DD is the digital power supply, REF is the reference voltage, CHAIN is the daisy chain / cascade enable interface, CNV is the conversion start interface, BUSY is the busy signal interface, SDO is the SPI data output interface, RDL / SDI is the SPI data input interface, SCK is the SPI clock interface, is the reference signal interface of the control logic unit.

[0045] For the extracted digital signal, a discrete Fourier transform circuit and a bi-phase lock-in amplifier are used to extract amplitude and phase information from the input signal, and the characteristic information of the 16×16 network is analyzed according to the existing tolerance calculation algorithm.

[0046] In some embodiments, according to the above parallel high-speed and high-precision measurement design of the capacitor array, the full-link block diagram is as Figure 13 shown. From Figure 13It can be seen that after FFT, the amplitude values of the frequency points of the excitation signal spectrum line satisfy: (N + K) × 6 - |S|dB = 20log(V AD ) - [20log(Vp~p) - T0 + T1 + A]. The range V AD of the analog-to-digital converter AD and the excitation signal Vp~p are both represented by the amplitude of the sine signal. It can be obtained that: T0 = (N + K) × 6 - |S|dB - 20log(V AD / Vp~p) + T1 + A where A is the driving gain of the analog-to-digital converter AD, the capacitance array attenuation value T0 represents the characteristics of the capacitance array (the actual capacitance value is proportional to T0), and the accuracy of T0 (which is also the capacitance limit measurement accuracy) is mainly determined by the FFT analysis bandwidth and the current noise of the current-to-voltage conversion (formed by JFET and operational amplifier). N is the resolution of the analog-to-digital converter AD, K is the bit width of the spectral data after FFT operation, T1 is the current-to-voltage gain, and S is the frequency point spectrum line of the excitation signal, representing the amplitude / phase distribution of the communication signal in the frequency domain. The circuit limit signal-to-noise ratio SNR is: SNR = 20log(I-in / I-Noise) where I-in is the output signal current of the capacitance array; I-Noise is the equivalent input current noise of the current-to-voltage conversion, and its value is the current noise within the bandwidth of a single FFT spectrum line, which is the combination of JFET current noise, current noise caused by the feedback loop resistance, and input current noise of the operational amplifier. From the above expressions, it can be seen that the key to achieving high-precision measurement is to control the current noise in the current-to-voltage conversion process and try to increase the output voltage amplitude of the DA. The circuit principles of the three parts of the excitation circuit, capacitance array, and current-to-voltage conversion are as Figure 14 shown.

[0047] Figure 14 where Vin+ and Vin- are the output signals of the differential DAC, C mn+ is the sum of the coupling capacitances of the mth TX+ signal line and the nth RX signal of the thin film, C mn- is the sum of the coupling capacitances of the mth TX- signal line and the nth RX signal of the thin film, C o is the sum of the parasitic capacitance of the RX signal and the input capacitance of the JFET tube, and R0 is the input resistance of the JFET. Since the input resistance of the JFET reaches several hundred MΩ, it can be ignored. Assume: C mn = (C mn+ + C mn- ) / 2, δ = (C mn+ - C mn- ) / C mn , and δ is approximately a real number.

[0048] V in= (V in+ + V in- ) / 2, Δ = (V in+ - V in- ) / V in , where Δ is a complex number.

[0049] When the current-to-voltage loop operates stably, the output signal current of the capacitor array is: I-in = j2πfVinC mn (Δ + δ) where f is the excitation signal frequency; δ is determined by the capacitor deviation (determined by the composite film dielectric texture information); Δ is a relatively fixed deviation amount.

[0050] It should be noted that the extraction of the random dielectric texture characteristics of the composite film is the core of the chip security packaging design and is the necessary data basis for designing a highly reliable PUF under wide temperature and wide voltage conditions. Therefore, how to achieve high-precision measurement of the random dielectric texture characteristics of the composite film is crucial. In this specification, the above-mentioned measurement scheme for random dielectric texture characteristics based on differential capacitance is adopted, and the capacitance values corresponding to the random dielectric texture characteristics of the composite film are in the fF order of magnitude (10 to 15 F), and it is necessary to simultaneously monitor the subtle changes of hundreds of capacitance values in the fF order of magnitude on the chip packaging size. To solve this problem, this specification breaks through the design technology of the capacitor array for measuring random dielectric texture characteristics and the parallel fast high-precision measurement technology of the fF-order capacitor array to identify the subtle changes of the random dielectric texture characteristics of the composite film and provide basic data support for the generation of reliable PUF root keys based on random dielectric characteristics.

[0051] In one embodiment, the capacitance measurement device of the capacitor array in the above chip further includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module. The input end of the transmitting electrode integrity detection module is respectively connected to each transmitting electrode of the capacitor array 12, the output end of the transmitting electrode integrity detection module is connected to the microcontroller 11, the input end of the receiving electrode integrity detection module is respectively connected to each receiving electrode of the capacitor array 12, the output end of the receiving electrode integrity detection module is connected to the microcontroller 11, the transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrodes of the capacitor array 12, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrodes of the capacitor array 12.

[0052] It can be understood that as Figure 15 shown, both the transmitting electrode integrity detection module and the receiving electrode integrity detection module can adopt a multiplexing unit (such as a multiplexer ADG706) to achieve the connection and selection of each corresponding electrode.

[0053] It can be understood that when applying the chip packaging process to analyze the cross-capacitance characteristics of flexible thin films: considering the advanced packaging process level, reliability, and safety protection requirements, a trace width of 10 μm and an insulation layer thickness of approximately 3 μm are selected. Therefore, each cross-coupled capacitor is about 100 μm, and the occupied area is about 400 μm 2 , calculating based on 128 cross-coupled capacitors formed by a single pair (TX+, TX-) and RX, the total is approximately 0.0512 mm 2 , according to the packaging materials and process, the sum of the capacitance values of the 64 cross-coupled capacitors formed by TX+ or TX- is approximately 1 to 2 pF, with a process deviation of about 10%. Under the conditions of Vin = 1 V and f = 24 kHz, I-in is approximately 15 nA. According to the current device level, I-Noise is generally not lower than 5 pA. When the FFT analysis measurement time is 10 ms, the SNR is 50 dB, about 8-bit effective values. Assuming that one capacitor is damaged among the 128 cross-coupled capacitors, exactly 8 bits are required, which cannot meet the high-reliability measurement requirements. Therefore, it is necessary to further improve the circuit detection sensitivity or enhance the thin film characteristic information.

[0054] Then, methods for improving the detection sensitivity are given: (a) increasing the amplitude of the DA output signal, which can achieve an output of 2 Vp~p according to the device capabilities; (b) the current packaging insulation material is PI, with a dielectric constant of about 2 to 3. If a new high-dielectric thin film material is used, the dielectric constant can be increased to between 20 and 30. Combining these two measures, with other measurement conditions unchanged, the SNR can be increased by about 26 dB, approximately increasing 4-bit effective values.

[0055] Next, the analysis of security application requirements is also given: Security application requirements include two aspects. One is whether the composite thin film can extract sufficient PUF effective information, and the other is the ultimate anti-intrusion detection ability, that is, the minimum punching size that can be detected when the composite thin film encounters an intrusion.

[0056] PUF effective information: According to the above analysis, a thin film with an area of 0.0512 mm 2 can output 8-bit effective information. There are nearly 20 measurement data within 1 mm 2 . Among the 8-bit effective information of each measurement result, including fixed deviations, it cannot be used for PUF data. Only the capacitance difference between TX+ and TX1 relative to RX can be used for PUF information generation. Estimated according to a 10% process deviation, a 10% fluctuation approximately corresponds to the lowest 2 to 3 bits of information in the 8-bit effective information. Therefore, within 1 mm 2 , approximately 40 to 60 bits of information can be output for PUF information generation, which can provide stable information data for realizing a PUF information output of 4 bit / mm 2 .

[0057] For the ultimate anti-intrusion detection ability, the integrity of the composite film can be detected through two approaches: (a) detecting the connectivity of the TX and RX lines; (b) detecting the offset of the capacitances between TX+, TX- and RX. In the above design, the single measurement result is the difference between the sums of 64 capacitances in two groups respectively. To achieve the detection ability for perforation detection at the 10-μm level (only one capacitance is damaged), the single measurement result needs to have at least an effective measurement accuracy exceeding 8 bits for detection. After increasing the DA amplitude and improving the material dielectric constant, the effective bits per point can be increased by 4 bits, but the false alarm probability is still relatively high. Signal processing techniques need to be combined, such as sparse signal detection, increasing the analysis time window, etc., to reduce the false alarm of detection.

[0058] From the above high-precision measurement and analysis, it can be seen that the core of the secure package includes: (1) the dielectric properties of the thin-film insulating material to increase the capacitance value without changing the spatial dimensions; (2) advanced signal processing techniques to reduce the false alarm rate of intrusion detection; (3) the devices required for the high-precision measurement circuit. Currently, for module-level packaging, general devices can be used to achieve high-precision measurement, but for chip-level secure packaging, through advanced packaging processes, the dies (chip bare chips) of the analog and integrated circuits required for measurement need to be packaged into chiplets in the form of chips.

[0059] All in all, by attaching a composite dielectric film with random microscopic properties to the surface of the chip bare chip, the Figure 15 random physical properties of the film can be extracted by using a high-precision differential capacitance measurement circuit. The specific implementation principle is as follows: The microcontroller 11 (i.e., the SOC uses XC7Z020) drives the dual-channel (dual-path) DAC to generate two synchronous excitation signals with matching amplitudes and opposite phases, and removes the high-frequency components in the DAC output through a two-stage low-pass filter. Then, a fully differential amplifier provides sufficient amplitude matching for the signals output by the DAC. The two signals output by the fully differential amplifier are respectively applied to the fixed electrodes TX1 and TX2 corresponding to the differential detection capacitance, and then a composite current I RX is generated on the common electrode of TX1 and TX2. The JFET-TIA circuit is used to realize the measurement of current-to-voltage conversion. After the current I RX is converted into a voltage output signal, it is filtered and amplified, and then transmitted to the ADC through a preprocessing circuit. The ADC realizes the conversion from analog signal to digital signal. For the extracted digital signal, a discrete Fourier transform circuit and a bi-phase lock-in amplifier are used to extract the amplitude and phase information from the RX signal, and the SOC analyzes the characteristic information of the 16×16 capacitance network according to the existing tolerance calculation algorithm.

[0060] The capacitance measurement device for the capacitor array in the above chip optimizes the traditional capacitance measurement circuit, adopts the differential capacitance measurement technology based on the mutual capacitance of horizontal and vertical lines, processes and analyzes the tolerance between every two mutual capacitances, so as to improve the ability to capture tiny capacitance changes. By applying excitation signals with opposite phases to adjacent TX electrodes, the capacitance difference ΔC is extracted by current cancellation, effectively eliminating the influence of circuit device process deviation and environmental temperature drift. The digital dual-phase lock-in amplifier is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, minimize the influence of noise and generate a high-entropy key. Using JFET-TIA (transimpedance amplifier), the RX current in the nA range is converted into voltage, and the DC offset is eliminated by combining high-pass and low-pass filters to ensure signal stability at high gain. The multiplexing unit can support the expansion of a 16×16 electrode network, balancing speed and area; the digital lock-in amplifier accelerates the operation through the FPU, reducing the calculation time of a capacitance node by about 25%.

[0061] In one embodiment, as Figure 16 shown, a capacitance measurement method for a capacitor array in a chip is provided, which may include the following steps: S10, constructing a capacitor array on the printed circuit board where the chip to be measured is located through orthogonal wiring on the top layer and the bottom layer; S12, inputting synchronous excitation signals with matching amplitudes and opposite phases to every two adjacent transmitting electrodes of the capacitor array through the differential capacitance measurement module, and obtaining the composite current signal generated on the common receiving electrode of every two adjacent transmitting electrodes and converting it into a measurement signal in voltage form; S14, performing a fast Fourier transform on the measurement signal after ADC sampling through the frequency-domain signal processing module, and extracting the tolerance between every two capacitors of the capacitor array as the characteristic parameter of the capacitor array; the characteristic parameter is used to generate the PUF identifier of the chip to which the capacitor array belongs.

[0062] The capacitance measurement method for the capacitor array in the above chip optimizes the design of the traditional capacitance measurement circuit, adopts the differential capacitance measurement technology based on the mutual capacitance of horizontal and vertical lines, processes and analyzes the tolerance between every two mutual capacitances, so as to improve the ability to capture tiny capacitance changes. By applying excitations with opposite phases to adjacent transmitting electrodes, the capacitance difference is extracted using the principle of current cancellation, effectively eliminating the influence of circuit device process deviation and environmental temperature drift. The differential capacitance measurement module is used to convert the composite current signal in the nA range into voltage, and the DC offset is eliminated by combining high-pass and low-pass filtering to ensure signal stability at high gain; the frequency-domain signal processing module is used to extract the amplitude and phase of the excitation, convert the analog signal into a digital signal, minimize the influence of noise, generate a high-entropy key, and the measurement result has high robustness and accuracy and strong anti-interference ability.

[0063] In one embodiment, the differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field-effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is sequentially connected to each transmitting electrode of the capacitance array through the first low-pass filter and the fully differential amplifier. The input terminals of the junction field-effect transistor transimpedance amplifier are respectively connected to each receiving electrode of the capacitance array. The output terminal of the junction field-effect transistor transimpedance amplifier is sequentially connected to the frequency-domain signal processing module through the high-pass filter, the AC amplifier, and the second low-pass filter. The dual-channel DAC circuit is used to generate synchronous excitation signals with amplitude matching and opposite phases.

[0064] In one embodiment, the frequency-domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a bi-phase lock-in amplifier connected in sequence. The input terminal of the successive approximation register ADC chip is connected to the differential capacitance measurement module for ADC sampling of the measurement signal. The discrete Fourier transform circuit and the bi-phase lock-in amplifier are used to extract amplitude and phase information from the sampled measurement signal through fast Fourier transform; the microcontroller calculates the tolerance using the amplitude and phase information.

[0065] For the specific limitations on the capacitance measurement method of the capacitance array in the above chip, reference can be made to the corresponding limitations in the embodiments of the capacitance measurement device of the capacitance array in the chip in the foregoing text, which will not be elaborated herein.

[0066] It should be understood that although the above steps Figure 16 in the flow are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the above flow Figure 16 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0067] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, abbreviated as RDRAM), and interface dynamic random access memory (DRDRAM), etc.

[0068] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0069] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and all belong to the protection scope of the present invention.

Claims

1. A capacitance measurement device for a capacitance array in a chip, characterized in that, It includes a microcontroller, a capacitance array of the chip under test, a differential capacitance measurement module, and a frequency-domain signal processing module; the capacitance array includes a plurality of orthogonal transmitting electrodes and receiving electrodes, and each intersection point between the transmitting electrode and the receiving electrode corresponds to a capacitance; The differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to every two adjacent transmitting electrodes of the capacitance array respectively, obtains the composite current signal generated on the receiving electrode common to every two adjacent transmitting electrodes of the capacitance array and converts it into a measurement signal in voltage form. The frequency-domain signal processing module performs fast Fourier transform on the measurement signal after ADC sampling, extracts the tolerance of every two capacitances of the capacitance array from the measurement signal as the characteristic parameter of the capacitance array. The microcontroller is used to control the generation of the excitation signal of the differential capacitance measurement module and generate the PUF identifier of the chip to which the capacitance array belongs according to the characteristic parameter.

2. The capacitance measurement device for the capacitance array in the chip according to claim 1, wherein The differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field-effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is sequentially connected to each transmitting electrode of the capacitance array through the first low-pass filter and the fully differential amplifier. The input ends of the junction field-effect transistor transimpedance amplifier are respectively connected to each receiving electrode of the capacitance array. The output end of the junction field-effect transistor transimpedance amplifier is sequentially connected to the frequency-domain signal processing module through the high-pass filter, the AC amplifier, and the second low-pass filter. The dual-channel DAC circuit is used to generate synchronous excitation signals with matching amplitudes and opposite phases.

3. The capacitance measurement device for a capacitance array in the chip according to claim 1 or 2, characterized in that, The frequency-domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a bi-phase lock-in amplifier connected in sequence. The input end of the successive approximation register ADC chip is connected to the differential capacitance measurement module and is used to perform ADC sampling on the measurement signal. The discrete Fourier transform circuit and the bi-phase lock-in amplifier are used to extract the amplitude and phase information from the sampled measurement signal through fast Fourier transform. The microcontroller calculates the tolerance using the amplitude and phase information.

4. The capacitance measurement device for the capacitance array in the chip according to claim 3, characterized in that, It also includes a transmitting electrode integrity detection module and a receiving electrode integrity detection module. The input ends of the transmitting electrode integrity detection module are respectively connected to each transmitting electrode of the capacitance array, and the output end of the transmitting electrode integrity detection module is connected to the microcontroller. The input ends of the receiving electrode integrity detection module are respectively connected to each receiving electrode of the capacitance array, and the output end of the receiving electrode integrity detection module is connected to the microcontroller. The transmitting electrode integrity detection module is used to detect the integrity of the transmitting electrodes of the capacitance array, and the receiving electrode integrity detection module is used to detect the integrity of the receiving electrodes of the capacitance array.

5. A method for measuring the capacitance of a capacitance array in a chip, characterized in that, It includes steps: Construct a capacitance array on the printed circuit board where the chip under test is located through orthogonal wiring on the top layer and the bottom layer; The differential capacitance measurement module inputs synchronous excitation signals with matching amplitudes and opposite phases to every two adjacent transmitting electrodes of the capacitance array respectively, and obtains the composite current signal generated on the receiving electrode common to every two adjacent transmitting electrodes and converts it into a measurement signal in voltage form; After the measurement signal is sampled by the ADC in the frequency-domain signal processing module, a fast Fourier transform is performed to extract the tolerance between every two capacitors in the capacitor array from the measurement signal as the characteristic parameter of the capacitor array; the characteristic parameter is used to generate the PUF identifier of the chip to which the capacitor array belongs.

6. The capacitance measurement method of the capacitance array in the chip according to claim 5, characterized in that, The differential capacitance measurement module includes a dual-channel DAC circuit, a first low-pass filter, a fully differential amplifier, a junction field-effect transistor transimpedance amplifier, a high-pass filter, an AC amplifier, and a second low-pass filter; The dual-channel DAC circuit is sequentially connected to each emitter electrode of the capacitor array through the first low-pass filter and the fully differential amplifier. The input terminals of the junction field-effect transistor transimpedance amplifier are respectively connected to each receiving electrode of the capacitor array. The output terminal of the junction field-effect transistor transimpedance amplifier is sequentially connected to the frequency-domain signal processing module through the high-pass filter, the AC amplifier, and the second low-pass filter. The dual-channel DAC circuit is used to generate synchronous excitation signals with amplitude matching and opposite phases.

7. The method for measuring capacitance of a capacitance array in a chip according to claim 5 or 6, characterized in that, The frequency-domain signal processing module includes a successive approximation register ADC chip, a discrete Fourier transform circuit, and a bi-phase lock-in amplifier connected in sequence. The input terminal of the successive approximation register ADC chip is connected to the differential capacitance measurement module for ADC sampling of the measurement signal. The discrete Fourier transform circuit and the bi-phase lock-in amplifier are used to extract the amplitude and phase information from the sampled measurement signal through a fast Fourier transform; the tolerance is calculated by the microcontroller using the amplitude and phase information.

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