Memory access verification method and system based on DPU, electronic equipment and computer storage medium

Abstract

The embodiment of the invention provides a memory access verification method and system based on a DPU, electronic equipment and a computer storage medium. The memory access verification method comprises the following steps that: simulation equipment copies transmission data received from a DPU (Data Processing Unit) to a memory of an operating system where an equipment driver is located through direct memory access, and writes a descriptor index in descriptor information and a data length of the transmission data into a completion buffer area of the equipment driver, triggering the operating system to generate a first interrupt operation; the device driver obtains the descriptor index and the data length from the completion buffer area based on the first interrupt operation, and obtains a storage address in the descriptor information based on the descriptor index, and reading the transmission data from a memory of the operating system based on the data length and the storage address, and sending the transmission data to a kernel of the operating system.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a method and system for verifying memory access based on a DPU, an electronic device, and a computer storage medium. Background Art

[0002] With the rapid development of computer technologies, PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) has gradually become an important interface standard for high-speed data transmission in modern computer systems. PCIE devices (such as DPU devices, Data Processing Unit, a data processing unit or a dedicated data processor) usually use DMA (Direct Memory Access, direct memory access technology) to transfer data with the host. As an efficient data transfer method, DMA can bypass the CPU (Central Processing Unit) and directly transfer data between the memory and external devices, greatly improving the system performance. Therefore, the verification of the DMA function of PCIE devices is also particularly important.

[0003] In the related art, due to the complexity and hardware dependence of the DMA mechanism, it is often necessary to construct a real hardware environment during the verification process, that is, to use a traditional RTL (Register Transfer Level) hardware verification solution to verify the DMA function of PCIE devices. However, the hardware verification solution results in a high verification cost and a low verification efficiency. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method and system for verifying memory access based on a DPU, an electronic device, and a computer storage medium to solve or alleviate the above technical problems.

[0005] According to the first aspect of the embodiments of the present invention, there is provided a method for verifying memory access based on a DPU, including: copying, via a direct memory access by a simulation device, the transmission data received from the DPU to the memory of the operating system where the device driver is located; writing, by the simulation device, the descriptor index in the descriptor information and the data length of the transmission data into the completion buffer of the device driver, and triggering the operating system to generate a first interrupt operation; obtaining, by the device driver based on the first interrupt operation, the descriptor index and the data length from the completion buffer, and obtaining the storage address in the descriptor information based on the descriptor index; reading, by the device driver, the transmission data from the memory of the operating system based on the data length and the storage address, and sending the transmission data to the kernel of the operating system.

[0006] In another implementation manner of the present invention, copying, via a direct memory access, the transmission data received from the DPU to the memory of the operating system where the device driver is located includes: obtaining the cache address and cache depth of the descriptor cache ring based on the descriptor index, where the cache address at least includes the address of the descriptor cache ring and the address of the data buffer corresponding to the descriptor cache ring, and the cache depth indicates the storage capacity of the data buffer; writing the transmission data into the data buffer based on the cache address and the cache depth; copying, via a direct memory access, the transmission data written into the data buffer to the memory of the operating system where the device driver is located.

[0007] In another implementation manner of the present invention, obtaining the storage address of the transmission data based on the descriptor index includes: obtaining the address of the corresponding data buffer from the descriptor cache ring based on the descriptor index; determining the address of the data buffer as the storage address of the transmission data.

[0008] In another implementation manner of the present invention, the method further includes: obtaining, by the device driver, the storage address of the transmission data sent by the kernel of the operating system; writing, by the device driver, the storage address of the transmission data and the data length into the descriptor cache ring, and configuring the obtained descriptor index into the descriptor register of the simulation device; obtaining, by the simulation device based on the descriptor index in the descriptor register, the storage address and the data length of the transmission data; moving, by the simulation device based on the storage address and the data length, the transmission data in the memory of the operating system to the simulation device for sending to the DPU.

[0009] In another implementation of the present invention, the method further includes: writing the descriptor index into the completion buffer through the simulation device, triggering the operating system to generate a second interrupt operation; and releasing the storage space of the transmitted data in the data buffer by the device driver according to the second interrupt operation.

[0010] In another implementation of the present invention, the method further includes: obtaining the cache address and cache depth of the descriptor cache ring by the device driver; configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the simulation device by the device driver; and obtaining the cache address and cache depth of the completion buffer by the device driver and configuring them into the completion cache register of the simulation device.

[0011] In another implementation of the present invention, configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the simulation device includes: obtaining the cache address and cache depth of the data buffer corresponding to the descriptor cache ring; writing the cache address and cache depth of the data buffer into the descriptor cache ring to obtain an assembled descriptor cache ring; and configuring the cache address and cache depth of the assembled descriptor cache ring into the descriptor register of the simulation device.

[0012] According to a second aspect of the embodiments of the present invention, there is provided a memory access verification system based on a DPU, including: a simulation device that copies transmitted data received from the DPU to the memory of the operating system where the device driver is located through direct memory access, writes the descriptor index and the data length of the transmitted data in the descriptor information into the completion buffer of the device driver, and triggers the operating system to generate a first interrupt operation; and a device driver that obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, obtains the storage address in the descriptor information based on the descriptor index, reads the transmitted data from the memory of the operating system based on the data length and the storage address, and sends the transmitted data to the kernel of the operating system.

[0013] According to a third aspect of the embodiments of the present invention, there is provided an electronic device, including: a processor, a memory, a communication interface, and a communication bus, where the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to virtualize the simulation device and the device driver and perform operations corresponding to the method according to the first aspect.

[0014] According to a fourth aspect of the embodiments of the present invention, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, it realizes virtualization of an analog device and a device driver, and performs operations corresponding to the method according to the first aspect.

[0015] In the solution of the embodiments of the present invention, the analog device copies the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access; the analog device writes the descriptor index and the data length of the transmission data in the descriptor information to the completion buffer of the device driver, and triggers the operating system to generate a first interrupt operation; the device driver obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, and obtains the storage address in the descriptor information based on the descriptor index; the device driver reads the transmission data from the memory of the operating system based on the data length and the storage address, and sends the transmission data to the kernel of the operating system. That is to say, software virtualization of the analog device and the device driver can be realized, and direct memory access is verified through the data access mechanism between the software-virtualized analog device and the device driver, reducing the verification cost and improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a flowchart of a memory access verification method according to some embodiments of the present invention.

[0018] Figure 2 For Figure 1 Some examples of the embodiments of the memory access verification method are schematic block diagrams.

[0019] Figure 3 For Figure 1 Some examples of the embodiments of the memory access verification method are step flowcharts.

[0020] Figure 4 For Figure 1 The step flowchart of the initialization process of the memory access verification process of the embodiments.

[0021] Figure 5 It is a structural block diagram of a memory access verification system according to other embodiments of the present invention.

[0022] Figure 6A structural block diagram of an electronic device according to some other embodiments of the present invention. Detailed implementation manners

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the embodiments of the present invention.

[0024] The following further illustrates the specific implementation of the embodiments of the present invention in conjunction with the embodiments and accompanying drawings of the present invention.

[0025] Figure 1 A memory access verification method according to some embodiments of the present invention is shown. Figure 1 The DPU-based memory access verification method includes:

[0026] S110: Copy the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access through a simulation device.

[0027] S120: Write the descriptor index and the data length of the transmission data in the descriptor information into the completion buffer of the device driver through a simulation device, and trigger the operating system to generate a first interrupt operation.

[0028] S130: Obtain the descriptor index and the data length from the completion buffer based on the first interrupt operation through the device driver, and obtain the storage address in the descriptor information based on the descriptor index.

[0029] S140: Read the transmission data from the memory of the operating system based on the data length and the storage address through the device driver, and send the transmission data to the kernel of the operating system.

[0030] In the solution of the embodiment of the present invention, the emulation device copies the transmission data received from the DPU to the memory of the operating system where the device driver is located through direct memory access; the emulation device writes the descriptor index and the data length of the transmission data in the descriptor information into the completion buffer of the device driver and triggers the operating system to generate a first interrupt operation; the device driver obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, and obtains the storage address in the descriptor information based on the descriptor index; the device driver reads the transmission data from the memory of the operating system based on the data length and the storage address and sends the transmission data to the kernel of the operating system. That is to say, software virtualization of the emulation device and the device driver can be realized, and direct memory access is verified through the data access mechanism between the software virtualized emulation device and the device driver, reducing the verification cost and improving the verification efficiency.

[0031] In some embodiments, as Figure 2 shown, during the data sending process, the transmission data is sent from the system kernel (for example, the linux kernel eth interface) to the sending module of the device driver to be sent to the DMA sending module of the emulation device, and the DMA sending module sends it to the external network interface. During the data receiving process, the emulation device receives the transmission data from an external network interface such as a DPU, gives it to the DMA receiving module to be sent to the receiving module of the device driver, and the receiving module further sends the transmission data to the system kernel. That is to say, the sending module of the device driver communicates with the DMA sending module of the emulation device through the data buffer based on the descriptor cache ring, and the receiving module of the device driver communicates with the DMA receiving module of the emulation device based on the data buffer of the descriptor cache ring.

[0032] In other embodiments, in order to copy the transmission data received from the DPU to the memory of the operating system where the device driver is located through direct memory access, the cache address and cache depth of the descriptor cache ring can be obtained based on the descriptor index, and then, based on the cache address and cache depth, the transmission data is written into the data buffer, and then, the transmission data written in the data buffer is copied to the memory of the operating system where the device driver is located through direct memory access. It should be understood that the cache address includes at least the address of the descriptor cache ring and the address of the data buffer corresponding to the descriptor cache ring, and the cache depth indicates the storage capacity of the data buffer;

[0033] Specifically, as an example of obtaining the storage address of the transmission data based on the descriptor index, the address of the corresponding data buffer can be obtained from the descriptor cache ring based on the descriptor index, and then, the address of the data buffer is determined as the storage address of the transmission data.

[0034] In the memory access verification method, the descriptor index can also be written into the completion buffer through a simulated device, triggering the operating system to generate a second interrupt operation. Then, according to the second interrupt operation, the device driver releases the storage space for the transmitted data in the data buffer.

[0035] Figure 3 For Figure 1 the step flowchart of the memory access verification method of some examples of the embodiment.

[0036] Step S310: The PCIE device side simulated by QEMU receives data from an external NIC. That is to say, the PCIe device simulated by QEMU (usually a virtual network interface card) simulates the process of receiving data from an external network interface card (NIC). Generally speaking, it usually involves simulating the reception of network traffic. QEMU listens for packets on the virtual network interface and prepares to pass the packet to the virtual machine.

[0037] Step S320: The simulated device obtains descriptor information according to the cache index idx of the descriptor. That is to say, the simulated PCIe device uses the index (idx) in the descriptor ring (vring) to find the corresponding descriptor. The descriptor contains information such as the physical address (dma_addr) and data length (len) of the data buffer. The index points to a specific location in the Guest physical address space, and the simulated device determines which memory location to write the received data to through the index.

[0038] Step S330: The simulated device writes the received data into the dma_addr address in the descriptor, and copies the data from the device side to the memory of Linux. That is to say, the simulated device directly writes the data received from the external NIC into the memory area corresponding to the Guest physical address (dma_addr) specified by the descriptor. This process usually involves a DMA (Direct Memory Access) operation, which allows data to be directly transferred from the network interface card to the Guest's memory without the intervention of the CPU. Without loss of generality, the cache address and cache depth of the descriptor cache ring can be obtained based on the descriptor index. Then, based on the cache address and cache depth, the transmitted data is written into the data buffer, and then, through direct memory access, the transmitted data written into the data buffer is copied to the memory of the operating system where the device driver is located. Further, as an example of obtaining the storage address of the transmitted data based on the descriptor index, the address of the corresponding data buffer can be obtained from the descriptor cache ring based on the descriptor index, and then, the address of the data buffer is determined as the storage address of the transmitted data.

[0039] Step S340: The emulated device writes information such as the length len of the data and the descriptor index idx into the completion buffer buff of the linux driver. That is to say, after the data is written into the memory, the emulated device updates the Used Ring, which is a ring for recording the descriptors that have been processed. The emulated device puts information such as the data length (len) and the descriptor index (idx) into the UsedRing so that the Linux driver can know which data has been processed. Without loss of generality,

[0040] Step S350: The emulated device triggers a hardware interrupt based on the data and the completion buffer information. That is to say, after updating the Used Ring, the emulated device triggers a hardware interrupt to notify the Linux driver. The interrupt notifies the driver that new data has arrived and has been written into the Guest's memory.

[0041] Step S360: The linux driver obtains the completion buffer buff information based on the interrupt to get the descriptor index idx, the data length len, etc. That is to say, the Linux driver responds to the hardware interrupt and checks the Used Ring to obtain the new data information. The driver reads the entries in the Used Ring to obtain the descriptor index (idx) and the data length (len), which inform the driver which data buffers contain the newly received data.

[0042] Step S370: The linux driver obtains information such as the index, address, and length of the data cache buff based on the descriptor index idx. That is to say, the Linux driver uses the descriptor index (idx) to find the corresponding descriptor, thereby obtaining the detailed information of the data cache buffer, including its address and length in the Guest physical address space. This information is used to determine the specific location of the data in the memory.

[0043] Step S380: The linux driver reads the data and assembles the corresponding upper-layer interface data according to the address and length information of the data. That is to say, the driver reads the data from the Guest's memory according to the obtained data address and length information. Then, the driver assembles the data into a format that can be processed by the upper-layer network interface according to the requirements of the network protocol stack.

[0044] Step S390: The linux driver passes the corresponding received data to the linux kernel eth interface to complete the data reception. That is to say, the Linux driver passes the assembled data to the network subsystem of the Linux kernel, usually through the ethernet interface. Thus, the data completes the reception process from the emulated PCIe device to the Linux kernel and can be further processed, such as routed, filtered, or passed to an application.

[0045] Optionally, during the data sending process of the memory access verification method, the storage address of the transmitted data is obtained from the kernel of the operating system through the device driver. For example, the linux kernel eth interface passes the data to be sent, data, to the linux driver. That is to say, when the network stack (eth interface) of the Linux kernel is ready to send data, it passes the data (data) to the driver responsible for the network device. This step is the start of the interaction between the network stack and the driver, and the driver is responsible for passing the data from the kernel space to the network device. Then, the linux driver obtains the physical address dma_addr of the transmitted data data. That is to say, the Linux driver needs to move the data from the kernel space to the memory area directly accessible by DMA (Direct Memory Access). To this end, it first obtains the physical address (dma_addr) of the data. This address is the location of the data in the Guest physical address space, and the DMA engine will use this address to transmit the data.

[0046] Furthermore, the storage address and data length of the transmitted data are written into the descriptor cache ring through the device driver, and the obtained descriptor index is configured into the descriptor register of the emulated device. For example, the linux driver assembles descriptor information based on the physical address dma_addr and length information of the data. That is to say, the driver uses the physical address (dma_addr) and data length of the data to assemble the descriptor. The descriptor contains detailed information about the data buffer, such as the physical address, length, and possibly control flags, which inform the DMA engine how to transmit the data. Then, the linux driver writes the descriptor information of the data into the descriptor cache ring and obtains the cache index idx. That is to say, the assembled descriptor is added to the descriptor cache ring, which is a circular buffer used to manage the descriptors to be sent and the sent descriptors. The driver obtains an index (idx) when adding the descriptor, which is used for subsequent tracking and processing. Then, the linux driver configures the index idx of the descriptor cache ring into the corresponding register of the PCIE device. That is to say, the driver writes the index (idx) of the descriptor cache ring into a specific register of the PCIe device, usually the notification register. This operation notifies the PCIe device (emulated device) that there is a new descriptor available and that the DMA transfer can start.

[0047] Further, the simulation device obtains the storage address and data length of the transmission data based on the descriptor index in the descriptor register. For example, the simulation device senses the software operation based on the register write operation. That is, the simulation device (such as the PCIe device emulated by QEMU) monitors the registers of the PCIe device. When it detects that the register is written, it knows that the driver has added a new descriptor and can start processing the descriptor. Then, the simulation device obtains the descriptor value in the descriptor cache ring according to the idx value written to the register. That is, the simulation device uses the index (idx) read from the register to obtain the corresponding descriptor from the descriptor cache ring. This descriptor contains the detailed information of the transmitted data. Then, the simulation device obtains information such as the address and length of the transmitted data according to the descriptor. That is, the simulation device extracts the physical address and length information of the transmitted data from the descriptor. This information is used for DMA transmission, and the simulation device will use this information to determine where to obtain the data.

[0048] Further, based on the storage address and data length, the simulation device moves the transmission data in the memory of the operating system to the simulation device to be sent to the DPU. For example, the simulation device moves the data content from the linux memory to the device according to the data address and length information, and writes the cache index idx back to the completion cache buff. That is, the simulation device uses DMA to transfer data from the memory of Linux (Guest physical address space) to the memory of the simulation device. After the transfer is completed, the simulation device writes the cache index (idx) and possibly other status information to the completion cache buff, which is usually the UsedRing, to notify the driver which descriptors have been processed. Then, the simulation device triggers a hardware interrupt according to the data and completion cache information. The linux driver obtains the completion cache buff information according to the interrupt, gets the descriptor index idx, and then releases the data data space. That is, once the data transfer is completed, the simulation device triggers a hardware interrupt to notify the Linux driver. The driver responds to the interrupt and reads information from the completion cache buff (Used Ring), including the descriptor index (idx). The driver uses this index to determine which data has been sent and can safely release the memory space occupied by the data. Then, the simulation device sends the data through an external NIC (for example, configured in the DPU). That is, the simulation device finally sends the received data through an external network interface card (NIC). This step involves transferring the data from the memory of the simulation device to the actual network device and then sending it through the network to the destination.

[0049] The following will be combined with Figure 4 Describe in detail Figure 1Flowchart of the steps of the initialization process of the memory access verification process of the embodiment.

[0050] Step S410: The Linux driver starts running and initializes the rxdma resources. That is, the Linux driver starts execution and initializes the Receive DMA (rxDMA) resources. This process typically includes setting up the DMA controller, configuring the DMA channels, and requesting DMA services, etc. Initialization is necessary because it prepares for subsequent data transfers, ensuring that the DMA engine can correctly transfer data from the Network Interface Card (NIC) to memory.

[0051] Step S420: The Linux driver applies for descriptor cache ring space, obtains the physical address and cache ring depth value; according to the cache ring depth information, applies for a data cache buff, and obtains information such as the physical address and size of the buff to assemble descriptors and add them to the descriptor cache ring. That is, the Linux driver applies for a memory space to store the descriptor cache ring, which is used to manage the descriptors for data transfer. The driver obtains the physical address and depth value of the ring (i.e., the number of descriptors that can be stored in the ring). Then, according to the depth information of the ring, the driver applies for the corresponding data cache buff and obtains the physical address and size of the buff. This information is used to assemble the descriptors and add them to the descriptor cache ring so that the DMA engine can access them.

[0052] Step S430: The Linux driver configures the physical address and depth value of the descriptor cache ring space into the corresponding registers of the PCIE device. That is, the Linux driver configures the physical address and depth value of the descriptor cache ring into the corresponding registers of the PCIe device. Since the PCIe device needs to know where to obtain the descriptors and how many descriptors are available, the configuration of the registers allows the PCIe device to correctly access and manage the DMA transfer.

[0053] Step S440: The Linux driver applies for data completion cache buff space, obtains the physical address and cache buff depth value. That is, the Linux driver applies for a memory space to store the data completion cache buff, which is used to store the data after the DMA transfer is completed. The driver obtains the physical address and depth value of the buff, and this information is crucial for subsequent data processing and cache management.

[0054] Step S450: The Linux driver configures the physical address and depth value of the data completion buffer buff space into the corresponding registers of the PCIE device. That is, the Linux driver configures the physical address and depth value of the data completion buffer buff into the corresponding registers of the PCIe device. Thus, when the DMA transfer is completed, the PCIe device can know where to write the data and can manage the data buff. The configuration of this register is a key step in the DMA transfer and data processing process.

[0055] Without loss of generality, the cache address and cache depth of the descriptor cache ring can be obtained through the device driver. Then, the cache address and cache depth of the descriptor cache ring are configured into the descriptor register of the analog device through the device driver. Then, the cache address and cache depth of the completion buffer are obtained through the device driver and configured into the completion cache register of the analog device.

[0056] Specifically, as an example of configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the analog device, the cache address and cache depth of the data buffer corresponding to the descriptor cache ring can be obtained. Then, the cache address and cache depth of the data buffer are written into the descriptor cache ring to obtain the assembled descriptor cache ring. Then, the cache address and cache depth of the assembled descriptor cache ring are configured into the descriptor register of the analog device.

[0057] The following will be combined with Figure 5 Describe a memory access verification system according to some other embodiments of the present invention. The memory access verification system includes:

[0058] An analog device 510 that copies the transmission data received from the DPU to the memory of the operating system where the device driver is located through direct memory access, writes the descriptor index in the descriptor information and the data length of the transmission data into the completion buffer of the device driver, and triggers the operating system to generate a first interrupt operation;

[0059] A device driver 520 that obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, obtains the storage address in the descriptor information based on the descriptor index, reads the transmission data from the memory of the operating system based on the data length and the storage address, and sends the transmission data to the kernel of the operating system.

[0060] In the solution of the embodiment of the present invention, the simulation device copies the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access; the simulation device writes the descriptor index and the data length of the transmission data in the descriptor information into the completion buffer of the device driver, and triggers the operating system to generate a first interrupt operation; the device driver obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, and obtains the storage address in the descriptor information based on the descriptor index; the device driver reads the transmission data from the memory of the operating system based on the data length and the storage address, and sends the transmission data to the kernel of the operating system. That is to say, it is possible to realize the software virtualization of the simulation device and the device driver, and verify the direct memory access through the data access mechanism between the software-virtualized simulation device and the device driver, reducing the verification cost and improving the verification efficiency.

[0061] In other embodiments, copying the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access includes: obtaining the cache address and cache depth of the descriptor cache ring based on the descriptor index, where the cache address at least includes the address of the descriptor cache ring and the address of the data buffer corresponding to the descriptor cache ring, and the cache depth indicates the storage capacity of the data buffer; writing the transmission data into the data buffer based on the cache address and the cache depth; copying the transmission data written into the data buffer to the memory of the operating system where the device driver is located via direct memory access.

[0062] In other embodiments, obtaining the storage address of the transmission data based on the descriptor index includes: obtaining the address of the corresponding data buffer from the descriptor cache ring based on the descriptor index; determining the address of the data buffer as the storage address of the transmission data.

[0063] In other embodiments, the method further includes: obtaining, by the device driver, the storage address of the transmission data sent by the kernel of the operating system; writing, by the device driver, the storage address of the transmission data and the data length into the descriptor cache ring, and configuring the obtained descriptor index into the descriptor register of the simulation device; obtaining, by the simulation device, the storage address and the data length of the transmission data based on the descriptor index in the descriptor register; moving, by the simulation device, the transmission data in the memory of the operating system to the simulation device based on the storage address and the data length for sending to the DPU.

[0064] In some other embodiments, the method further includes: writing the descriptor index into the completion buffer through the simulation device, triggering the operating system to generate a second interrupt operation; and releasing the storage space of the transmitted data in the data buffer by the device driver according to the second interrupt operation.

[0065] In some other embodiments, the method further includes: obtaining the cache address and cache depth of the descriptor cache ring by the device driver; configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the simulation device by the device driver; and obtaining the cache address and cache depth of the completion buffer by the device driver and configuring them into the completion cache register of the simulation device.

[0066] In some other embodiments, configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the simulation device includes: obtaining the cache address and cache depth of the data buffer corresponding to the descriptor cache ring; writing the cache address and cache depth of the data buffer into the descriptor cache ring to obtain an assembled descriptor cache ring; and configuring the cache address and cache depth of the assembled descriptor cache ring into the descriptor register of the simulation device.

[0067] The memory access verification system of this embodiment is used to implement the corresponding memory access verification methods in the foregoing multiple method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here. In addition, the function implementation of each module in the memory access verification system of this embodiment can refer to the description of the corresponding part in the foregoing method embodiments, which will not be elaborated here either.

[0068] Figure 6 It is a structural block diagram of an electronic device according to an embodiment of the present invention. The specific implementation of the electronic device in the specific embodiments of the present invention is not limited.

[0069] As Figure 6 shown, the electronic device 600 may include: a processor 602, a memory 603, a communication interface 604, and a communication bus 605. The processor 602, the memory 603, and the communication interface 604 complete communication with each other through the communication bus 605; the memory 603 is used to store at least one executable instruction, and the executable instruction causes the processor 602 to perform the operations corresponding to the memory access verification method in any of the foregoing embodiments.

[0070] The processor 602 may be a central processing unit (CPU), or a specific application integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. One or more processors included in the intelligent device may be of the same type of processor, such as one or more CPUs; or may be of different types of processors, such as one or more CPUs and one or more ASICs.

[0071] The memory 603 is used to store programs, which may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0072] An electronic device according to an embodiment of the present invention

[0073] The embodiment of the present invention also provides a computer storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the memory access verification system in any of the above embodiments.

[0074] It should be noted that, according to the needs of implementation, each component / step described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0075] The method according to the embodiments of the present invention described above can be implemented in hardware, firmware, or be implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or be implemented as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component (such as RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, it implements the memory access verification method described herein. In addition, when a general-purpose computer accesses the code for implementing the memory access verification method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the memory access verification method shown herein.

[0076] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present invention.

[0077] The above embodiments are only used to illustrate the embodiments of the present invention, rather than to limit the embodiments of the present invention. Those of ordinary skill in the relevant technical field can also make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention. The patent protection scope of the embodiments of the present invention should be defined by the claims. The systems, devices or modules illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions.

Claims

1. A memory access verification method based on DPU, characterized in that Including: Copying the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access by means of an emulation device; Writing the descriptor index in the descriptor information and the data length of the transmission data into the completion buffer of the device driver by means of the emulation device, and triggering the operating system to generate a first interrupt operation; Obtaining the descriptor index and the data length from the completion buffer by the device driver based on the first interrupt operation, and obtaining the storage address in the descriptor information based on the descriptor index; Reading the transmission data from the memory of the operating system by the device driver based on the data length and the storage address, and sending the transmission data to the kernel of the operating system.

2. The method for verifying memory access based on DPU according to claim 1, wherein Copying the transmission data received from the DPU to the memory of the operating system where the device driver is located via direct memory access, including: Obtaining the cache address and cache depth of the descriptor cache ring based on the descriptor index, where the cache address at least includes the address of the descriptor cache ring and the address of the data buffer corresponding to the descriptor cache ring, and the cache depth indicates the storage capacity of the data buffer; Writing the transmission data into the data buffer based on the cache address and the cache depth; Copying the transmission data written into the data buffer to the memory of the operating system where the device driver is located via direct memory access.

3. The method for verifying memory access based on DPU according to claim 2, wherein Obtaining the storage address of the transmission data based on the descriptor index, including: Obtaining the address of the corresponding data buffer from the descriptor cache ring based on the descriptor index; Determining the address of the data buffer as the storage address of the transmission data.

4. The method for verifying memory access based on DPU according to claim 1, wherein The method further includes: Obtaining the storage address of the transmission data sent by the kernel of the operating system by the device driver; Writing the storage address of the transmission data and the data length into the descriptor cache ring by the device driver, and configuring the obtained descriptor index into the descriptor register of the emulation device; Obtaining the storage address and the data length of the transmission data by the emulation device based on the descriptor index in the descriptor register; Moving the transmission data in the memory of the operating system to the emulation device based on the storage address and the data length by the emulation device for sending to the DPU.

5. The method for verifying memory access based on DPU according to claim 4, wherein The method further includes: Writing the descriptor index into the completion buffer by the emulation device, triggering the operating system to generate a second interrupt operation; Releasing the storage space of the transmission data in the data buffer by the device driver according to the second interrupt operation.

6. The method for verifying memory access based on DPU according to claim 4, wherein The method further includes: Obtaining the cache address and cache depth of the descriptor cache ring by the device driver; Configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the emulation device by the device driver; Obtaining the cache address and cache depth of the completion buffer by the device driver, and configuring them into the completion cache register of the emulation device.

7. The method for verifying memory access based on DPU according to claim 6, wherein Configuring the cache address and cache depth of the descriptor cache ring into the descriptor register of the simulation device includes: Obtaining the cache address and cache depth of the data buffer corresponding to the descriptor cache ring; Writing the cache address and cache depth of the data buffer into the descriptor cache ring to obtain an assembled descriptor cache ring; Configuring the cache address and cache depth of the assembled descriptor cache ring into the descriptor register of the simulation device.

8. A memory access verification system based on DPU, characterized in that, Including: The simulation device copies the transmission data received from the DPU to the memory of the operating system where the device driver is located through direct memory access, and writes the descriptor index in the descriptor information and the data length of the transmission data into the completion buffer of the device driver, and triggers the operating system to generate a first interrupt operation; The device driver obtains the descriptor index and the data length from the completion buffer based on the first interrupt operation, obtains the storage address in the descriptor information based on the descriptor index, reads the transmission data from the memory of the operating system based on the data length and the storage address, and sends the transmission data to the kernel of the operating system.

9. An electronic device, characterized in that, Including: A processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to virtualize the simulation device and the device driver, and perform operations corresponding to the method described in any one of claims 1-7.

10. A computer storage medium, on which a computer program is stored, characterized in that, The program virtualizes the simulation device and the device driver by the processor, and when executed, implements the method described in any one of claims 1-7.

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