Synchronization circuit suitable for various synchronization signals

Abstract

The invention relates to the technical field of synchronous signal processing, and discloses a synchronous circuit suitable for various synchronous signals, which comprises a sensor provided with a signal output end for outputting the synchronous signals; the first differential chip is provided with a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is connected with the signal output end of the sensor, the first signal output end is connected with the second signal input end and is connected with a programmable resistor in series, and the second signal output end is connected with the processing equipment; the processing chip is provided with a signal input end and a signal output end, the signal input end is connected with the first signal output end, and the signal output end is connected with the second signal input end. When a synchronization strategy between the systems is changed, real-time adjustment of system hardware can be achieved only by adjusting the programmable resistor, corresponding hardware in the system does not need to be replaced, processing is fast and convenient, and the use cost of the hardware can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronization signal processing, and in particular to a synchronization circuit applicable to multiple synchronization signals. Background Art

[0002] In the field of communication, there will be problems regarding the mutual requirement for time synchronization between different embedded systems. In a specific synchronization circuit, such as in the FPGA field, once the synchronization strategy between different systems changes, for example, the type of the synchronization signal changes and the synchronization signal is not shared between the two systems, it is very difficult for the corresponding hardware measures in the system to make real-time adjustments, and it is necessary to replace the corresponding hardware in the system, which is time-consuming, laborious, and costly. Summary of the Invention

[0003] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0004] A synchronization circuit applicable to multiple synchronization signals, comprising: a sensor: the sensor is used to detect information, the sensor is provided with a signal output end for outputting a synchronization signal, and the signal output end is connected to a first differential chip;

[0005] First differential chip: It is provided with a first signal input terminal, a second signal input terminal, a first signal output terminal and a second signal output terminal. The first signal input terminal is connected to the signal output terminal of the sensor to receive the synchronization signal transmitted by the sensor. The synchronization signal output by the sensor is divided into SYNi+ and SYNi- and transmitted to the first differential chip. SYNi+ and SYNi- are composed of two signals with equal amplitudes and opposite phases. When the signal is interfered by external noise during transmission, the noise usually affects both signal lines simultaneously (referred to as common-mode noise). Since the noise acts on both lines simultaneously, information can be extracted by calculating the difference between the two signals (positive phase - negative phase), which can cancel the noise. In addition, the current directions of the two signal lines are opposite, and the generated electromagnetic fields cancel each other out, thereby reducing the electromagnetic radiation (EMI) to the outside world. At the same time, the influence of external electromagnetic interference on the two lines is also symmetrical, further reducing signal distortion, reducing attenuation and distortion of the signal during transmission, and improving signal integrity, especially in high-speed data transmission; The first signal output terminal is connected to the second signal input terminal, and a programmable resistor is also connected in series between the first signal output terminal and the second signal input terminal. The programmable resistor adjusts its resistance value based on the type of synchronization signal, and is used to adjust whether the first signal output terminal and the second signal input terminal are connected. If the type of synchronization signal is compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to connect the first signal output terminal and the second signal input terminal. If the type of synchronization signal is not compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to disconnect the first signal output terminal and the second signal input terminal. The second signal output terminal is connected to the processing device; When the synchronization strategy between systems changes, only by adjusting the programmable resistor can the real-time adjustment of the system hardware be achieved without replacing the corresponding hardware in the system. The processing is fast and convenient, and can effectively reduce the usage cost of the hardware.

[0006] Processing chip: The processing chip is used for data calculation and timing judgment. The processing chip is provided with a signal input terminal and a signal output terminal. The signal input terminal is connected to the first signal output terminal of the first differential chip to receive the synchronization signal, and the signal output terminal is connected to the second signal input terminal of the first differential chip to transmit the processed synchronization signal.

[0007] Furthermore, a second differential chip is further included. The second differential chip is a multi-channel differential chip and is connected to the processing chip. In actual use, the synchronization signal often occurs between multiple circuit boards. A single differential signal cannot meet the requirements between multiple circuit boards at the same time. The second differential chip is used to convert a single differential signal into multiple differential signals, thereby realizing the rapid transmission of differential signals between multiple circuit boards.

[0008] Furthermore, the model of the processing chip is STM32F4.

[0009] Further, the model of the first differential chip is SIT490E.

[0010] Further, the model of the second differential chip is CAM26C31, and it is 4-channel differential.

[0011] Further, the processing chip is also connected to a storage chip. The storage chip can share the read and write operations of the flash, reduce the burden on the built-in Flash of the processing chip, thereby improving the overall stability of the system; and the storage chip has a higher read and write speed or a larger cache, which can better process the writing or reading of a large amount of data, and reduce the delay or stuttering generated by the system due to storage operations.

[0012] Advantages of the present invention:

[0013] 1. The synchronization signals output by the sensor are divided into SYNi+ and SYNi- and sent to the first differential chip. SYNi+ and SYNi- are composed of two signals with equal amplitudes and opposite phases. When the signal is interfered by external noise during transmission, the noise usually affects both signal lines simultaneously (referred to as common-mode noise). Since the noise acts on both lines simultaneously, the information can be extracted by calculating the difference between the two signals (positive phase - negative phase), and the noise can be canceled.

[0014] 2. When the synchronization strategy between systems changes, only by adjusting the programmable resistor can the real-time adjustment of the system hardware be realized, without replacing the corresponding hardware in the system. The processing is quick and convenient, and the use cost of the hardware can be effectively reduced.

[0015] 3. The storage chip can share the read and write operations of the flash, reduce the burden on the built-in Flash of the processing chip, thereby improving the overall stability of the system; and the storage chip has a higher read and write speed or a larger cache, which can better process the writing or reading of a large amount of data, and reduce the delay or stuttering generated by the system due to storage operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with the present application, and are used together with the specification to explain the principles of the present invention.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a connection schematic diagram of Embodiment 1 of the present invention;

[0019] Figure 2 Circuit diagram of the first differential chip in Embodiment 1 of the present invention;

[0020] Figure 3 Circuit diagram of the second differential chip of the present invention;

[0021] Figure 4 Circuit diagram of the first differential chip in Embodiment 2 of the present invention;

[0022] Figure 5 Test result diagram during storage;

[0023] Figure 6 Schematic connection diagram of Embodiment 4 of the present invention. Detailed implementation manners

[0024] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0026] Embodiment 1:

[0027] As Figure 1 and Figure 2As shown, a synchronization circuit applicable to multiple synchronization signals includes a sensor: The sensor is used to detect information and output a synchronization signal. The sensor is provided with a signal output terminal for outputting the synchronization signal. The signal output terminal is connected to a first differential chip. The synchronization signal output by the sensor is divided into SYNi+ and SYNi- and sent to the first differential chip. SYNi+ and SYNi- are composed of two signals with equal amplitudes and opposite phases. When the signal is affected by external noise during transmission, the noise usually affects both signal lines simultaneously (referred to as common-mode noise). Since the noise acts on both lines simultaneously, the information can be extracted by calculating the difference between the two signals (positive phase - negative phase), which can cancel the noise. In addition, the current directions of the two signal lines are opposite, and the generated electromagnetic fields cancel each other out, thereby reducing the electromagnetic radiation (EMI) to the outside world. At the same time, the influence of external electromagnetic interference on the two lines is also symmetric, further reducing signal distortion, reducing the attenuation and distortion of the signal during transmission, and improving signal integrity, especially in high-speed data transmission.

[0028] The first differential chip: The first differential chip uses SIT490E and is provided with a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal. As Figure 2 shown, the first signal input terminal includes a SYNi+ input pin and a SYNi- input pin. The two pins are electrically connected to the signal output terminal of the sensor respectively and are used to receive the synchronization signal sent by the sensor;

[0029] During use, there are two situations: the subsequent processing device can directly use the synchronization signal sent by the sensor (that is, the synchronization signal of the sensor is adapted to the subsequent processing device) and cannot use the synchronization signal of the sensor; Therefore, in order to achieve the ability to meet the above two situations through only one circuit structure, in the present invention, the first signal output terminal of the first differential chip is connected to the second signal input terminal, and a programmable resistor is also connected in series between the first signal output terminal and the second signal input terminal. By adjusting the resistance value of the programmable resistor to meet the use of the two situations, when the synchronization strategy between systems changes, only by adjusting the programmable resistor can the real-time adjustment of the system hardware be achieved without replacing the corresponding hardware in the system. The processing is fast and convenient, and can effectively reduce the hardware usage cost.

[0030] The specific usage method is as follows: The programmable resistor adjusts its resistance value based on the type of the synchronization signal, and is used to adjust whether the first signal output terminal is connected to the second signal input terminal. If the type of the synchronization signal is compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to connect the first signal output terminal to the second signal input terminal, that is, the programmable resistor is adjusted to a relatively small resistance value to ensure that the synchronization signal current can flow through the programmable resistor (R1). After the synchronization signal current flows through the programmable resistor, it is re-input into the first differential chip from the second signal input terminal, and then output from the second signal output terminal in the form of SYNo+ and SYNo- signals after voltage stabilization, and the second signal output terminal is connected to the processing device. If the type of the synchronization signal is not compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to disconnect the first signal output terminal from the second signal input terminal, that is, the programmable resistor is adjusted to a relatively large resistance value to form an open circuit state, ensuring that the synchronization signal current cannot flow through the programmable resistor. The synchronization signal is sent to the processing chip through SYNi_ARM for data calculation and adaptation to the subsequent processing device.

[0031] Processing chip: The model of the processing chip is STM32F4, which is used for data calculation and timing judgment. The processing chip is provided with a signal input terminal and a signal output terminal. The signal input terminal is connected to the first signal output terminal of the first differential chip. When the synchronization signal transmitted by the sensor is not compatible with the subsequent device, the signal input terminal of the processing chip is used to receive the synchronization signal. After receiving the synchronization signal, the processing chip processes the synchronization signal to ensure compatibility with the subsequent processing device. The signal output terminal of the processing chip is connected to the second signal input terminal of the first differential chip for transmitting the processed synchronization signal, that is, the processed synchronization signal of the processing chip is transmitted to the first differential chip through SYNo_ARM and then transmitted to the subsequent device through the first differential chip.

[0032] Embodiment 2:

[0033] In fields with high processing precision requirements, such as the field of image processing, since the resistance value of the programmable resistor cannot be adjusted to infinity (i.e., a completely open circuit state), there will still be a very small number of currents flowing to the programmable resistor, which will cause certain information loss and reduce the accuracy. As Figure 4 shown, a welding point can be reserved between the first signal output terminal and the second signal input terminal, that is, the first signal output terminal and the second signal input terminal are in a completely open circuit state. When in use, it can be considered whether to weld a suitable resistor at the welding point according to the actual situation.

[0034] Embodiment 3:

[0035] The processing chip is also connected to a second differential chip, which is a multi-channel differential chip of model CAM26C31. In actual use, synchronization signals often occur between multiple circuit boards. A single differential signal cannot meet the requirements between multiple circuit boards at the same time. The second differential chip is used to split one differential signal into multiple signals, so as to realize the fast transmission of differential signals between multiple circuit boards. In the present invention, as Figure 3 shown, the second differential chip of model CAM26C31 is divided into 4 channels of differential. The single-line signal pins of the output signals are AIN, BIN, CIN, and DIN respectively. At the same time, the processing chip can also be connected to multiple second differential chips simultaneously to meet the circuit boards with more requirements.

[0036] Embodiment 4:

[0037] Due to the underlying framework limitation of the processing chip STM32, the program initial code and the Flash section are on the same functional block, which leads to a pause phenomenon in the program when writing to the Flash. And this pause phenomenon is manifested in the storage area allocation, as Figure 5 shown, when storing in the Flash, when erasing a sector of 16KB in size, the system delay is 0.2s. The larger the sector storage space, the higher the delay. The existing solution is to store the flash and place the program code in two different areas respectively. Since the default routine during the framework operation is that the flash storage area and the program running read value area are the same area, at this time, the program code needs to be mapped and stored in a non-flash storage area, and the storage space layout needs to be manually sorted out, which reduces the stability and scalability of the system. In the present invention, as Figure 6 shown, the processing chip is also connected to a storage chip, and the model of the storage chip is a storage chip adapted to STM32F4 such as MT29F4G08 and AT25DF161. The storage chip can share the read and write operations of the flash, reduce the burden on the built-in Flash of the processing chip, thereby improving the overall stability of the system; and the storage chip has a higher read and write speed or a larger cache, which can better handle the writing or reading of a large amount of data, and reduce the delay or jitter generated by the system due to storage operations; in addition, the storage chip also supports RAID and data backup functions, which can provide additional data protection for the system and prevent data loss caused by the damage of the built-in Flash. By externally connecting a storage chip, the system can implement a modular design of the storage module, which is convenient for upgrading or replacement. For example, when a larger capacity or higher performance is required, only the externally connected storage chip needs to be replaced without modifying the entire system hardware.

[0038] (1) Unless otherwise defined, in the embodiments and drawings of the present disclosure, the same reference numerals represent the same meaning.

[0039] (2)In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0040] (3)For clarity, in the accompanying drawings used to describe the embodiments of the present disclosure, components or regions are enlarged. It can be understood that when an element is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0041] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A synchronization circuit applicable to multiple synchronization signals, characterized in that: It includes a sensor: The sensor is used to detect information. The sensor is provided with a signal output terminal for outputting a synchronization signal, and the signal output terminal is connected to a first differential chip; The first differential chip: It is provided with a first signal input terminal, a second signal input terminal, a first signal output terminal and a second signal output terminal. The first signal input terminal is connected to the signal output terminal of the sensor for receiving the synchronization signal transmitted by the sensor; the first signal output terminal is connected to the second signal input terminal, and a programmable resistor is also connected in series between the first signal output terminal and the second signal input terminal. The programmable resistor adjusts the resistance value based on the type of the synchronization signal, and is used to adjust whether the first signal output terminal and the second signal input terminal are connected. If the type of the synchronization signal is compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to connect the first signal output terminal and the second signal input terminal. If the type of the synchronization signal is not compatible with the subsequent processing device, the resistance value of the programmable resistor is adjusted to disconnect the first signal output terminal and the second signal input terminal. The second signal output terminal is connected to the processing device; The processing chip: The processing chip is used for data calculation and timing judgment. The processing chip is provided with a signal input terminal and a signal output terminal. The signal input terminal is connected to the first signal output terminal of the first differential chip for receiving the synchronization signal, and the signal output terminal is connected to the second signal input terminal of the first differential chip for transmitting the processed synchronization signal.

2. The synchronization circuit applicable to multiple synchronization signals according to claim 1, wherein: It further includes a second differential chip, and the second differential chip is a multi-channel differential chip and is connected to the processing chip.

3. The synchronization circuit applicable to multiple synchronization signals according to claim 2, wherein: The model of the processing chip is STM32F4.

4. The synchronization circuit applicable to multiple synchronization signals according to claim 2, wherein: The model of the first differential chip is SIT490E.

5. The synchronization circuit applicable to multiple synchronization signals according to claim 4, characterized in that: The model of the second differential chip is CAM26C31.

6. A synchronization circuit applicable to multiple synchronization signals according to any one of claims 1-5, characterized in that: The processing chip is further connected to a storage chip.

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