Chip, electronic equipment and method for processing interruption between chip particles

Abstract

The invention relates to a chip, electronic equipment and an interrupt processing method between chip particles, and belongs to the field of electronic circuits. The chip comprises at least two core particles, and each core particle comprises a main control module, an interrupt forwarding module and a transmission port; the main control module is connected with the interrupt forwarding module, the interrupt forwarding module is connected with the transmission port, and each core grain is connected with other core grains through the transmission port; the interrupt forwarding module is configured to forward the interrupt information from other core grains to the main control module or forward the interrupt information from the main control module to other core grains through the transmission port; and the main control module is configured to send the interrupt information to the interrupt forwarding module and perform interrupt processing on the interrupt information sent by the interrupt forwarding module. The chip provided by the invention supports a cross-core interrupt transmission and processing mode, and the cross-core interrupt processing mode is adopted, so that the interrupt processing efficiency of a multi-core system can be improved, and the power consumption of the whole chip is better reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and particularly relates to a chip, an electronic device, and an interrupt processing method between chiplets. Background Art

[0002] Currently, various application scenarios have increasing demands for high computing power, low latency, low power consumption, high bandwidth, etc. However, the time cycle from design to mass production of conventional System on Chip (SoC) chips is relatively long, and the design complexity and area cost are also increasing. To solve the above contradictions, Chiplet technology has emerged.

[0003] Chiplet technology decouples chip performance from chip process. At the same time, 2.5D, 3D and other packaging technologies have emerged. These packaging technologies can improve the interconnection density, enhance chip performance, shorten the R & D cycle, and reduce system power consumption and chip cost. Multiple die (chiplets) in Chiplet technology need to transmit interrupt transactions to each other. How to improve the interrupt transaction processing between multiple die is a technical problem. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a chip, an electronic device, and an interrupt processing method between chiplets to improve the transmission and processing efficiency of interrupts.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, an embodiment of this application provides a chip, including: at least two die, each die including: a main control module, an interrupt forwarding module, and a transmission port; the main control module is connected to the interrupt forwarding module, the interrupt forwarding module is connected to the transmission port, and each die is connected to other die through the transmission port; the interrupt forwarding module is configured to forward interrupt information from other die to the main control module, or forward interrupt information from the main control module to other die through the transmission port; the main control module is configured to send interrupt information to the interrupt forwarding module and perform interrupt processing on the interrupt information sent by the interrupt forwarding module.

[0007] In the above embodiment, through the cooperation of the main control module, the interrupt forwarding module and the transmission port in each chip, an efficient interrupt transmission and processing link is realized, which can efficiently realize the interrupt transaction forwarding and interrupt processing. Specifically, the chip of the above structure is adopted, so that the interrupt can be transmitted and processed across chips. The use of the cross-chip interrupt processing method can improve the interrupt processing efficiency of the multi-chip system and better reduce the power consumption of the entire chip. For example, when one of the chips is busy, the interrupt information generated by it can be sent to the idle chip for processing, thereby improving efficiency; at the same time, because the chip supports the cross-chip interrupt processing method, it supports that some chips can be in low power or sleep state, thereby reducing the power consumption of the entire chip.

[0008] In combination with a possible implementation manner of the first aspect embodiment, the main control module is specifically configured to: preprocess multiple interrupt signals from the core particle, and send the interrupt information obtained after preprocessing to the interrupt forwarding module; wherein the interrupt information includes the transition edge and interrupt flag of the interrupt signal.

[0009] In the above embodiment, when the main control module sends interrupt information to the interrupt forwarding module, it first pre-processes the interrupt signal, and then sends the interrupt information obtained after pre-processing to the interrupt forwarding module. By pre-processing the interrupt signal and converting it into interrupt information, it is transmitted, which can improve the transmission efficiency.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the main control module is specifically configured to: collect the jump edge and interrupt flag of each interrupt signal from the core particle to obtain the interrupt information corresponding to each interrupt signal; group the interrupt information from the same source end within a period of time, and package multiple interrupt information of the same group and send them to the interrupt forwarding module.

[0011] In the above embodiment, by collecting the jump edge and interrupt flag of the interrupt signal, the interrupt signal can be quickly converted into interrupt information, and then the interrupts are grouped according to the source end, and multiple interrupt information of the same group are packaged and sent, which can improve the transmission and processing efficiency of the interrupts. For example, when the number of interrupts is large, it is difficult to transmit all the interrupt information at one time. The interrupt information is grouped (divided into G0~Gn groups) for transmission, such as G0~Gn, and then G0~Gn are transmitted in time-sharing, which can improve the transmission efficiency.

[0012] In a possible implementation manner combining with the embodiments of the first aspect, the main control module includes: a processing unit and an arbitration unit; the processing unit is configured to collect the rising edge and interruption identifier of each interruption signal from the die, obtain the interruption information corresponding to each interruption signal, and divide the interruption information from the same source end within a period of time into a group, and pack multiple pieces of interruption information in the same group to obtain an interruption information packet; the arbitration unit is configured to send multiple interruption information packets to the interruption forwarding module in a certain order.

[0013] In the above embodiment, the processing unit is used to convert the interruption signal into interruption information, then group the interruptions according to the source end, and send multiple pieces of interruption information in the same group; the arbitration unit arbitrates the sending order of multiple interruption information packets and sends them to the interruption forwarding module in a certain order. By adopting the cooperation mode of the processing unit + arbitration unit, the forwarding efficiency of the interruption is improved.

[0014] In a possible implementation manner combining with the embodiments of the first aspect, the main control module is specifically configured to: convert the interruption information sent by the interruption forwarding module into a pulse interruption, and perform interruption processing on the pulse interruption.

[0015] In the above embodiment, when the main control module performs interruption processing on the interruption information sent by the interruption forwarding module, it first converts the interruption information sent by the interruption forwarding module into a pulse interruption, and then performs interruption processing on the pulse interruption. This can ensure that each pulse interruption corresponding to the interruption information is correctly processed and can also improve the efficiency.

[0016] In a possible implementation manner combining with the embodiments of the first aspect, each die further includes: a register bus control module, and the register bus control module is connected to the main control module and the transmission port; the main control module is configured to perform read and write access to the register through the register bus control module to cooperate in completing the interruption processing.

[0017] In the above embodiment, since the read and write access to the register is involved in the interruption processing process, by adding a register bus control module, the main control module, the register bus control module, the interruption forwarding module and the transmission port on different dies form an efficient interruption transmission and processing link, realizing the forwarding or reception of the interruption information between dies and the interruption processing. Thus, the main control module can perform read and write access to the register through the register bus control module to cooperate in completing the interruption processing.

[0018] In a possible implementation manner combining the embodiments of the first aspect, the at least two die chips include: a main die chip and a slave die chip; the slave die chip is configured to collect the rising edge and interrupt identifier of each interrupt signal from the slave die chip, obtain the interrupt information corresponding to each interrupt signal; and group the interrupt information from the same source end within a period of time, and pack and send the multiple interrupt information in the same group to the main die chip; the main die chip is configured to parse the interrupt information packet from the slave die chip, convert the parsed interrupt information into a pulse interrupt, and perform interrupt processing on the pulse interrupt; and during the interrupt processing, initiate read and write requests for the registers of the slave die chip, and forward the read and write requests to the slave die chip; the slave die chip is further configured to respond to the read and write requests to perform read and write access on the registers of the slave die chip to cooperate in completing the interrupt processing.

[0019] In the above embodiment, when the chip includes a main die chip and a slave die chip, when the slave die chip processes interrupts across die chips, it first collects the rising edge and interrupt identifier of each interrupt signal that needs to be processed across die chips to obtain the interrupt information corresponding to each interrupt signal, and then performs cross-die-chip transmission of the interrupt information. When the main die chip processes the interrupts, it first converts the received interrupt information into a pulse interrupt, and then performs interrupt processing on the pulse interrupt. During the interrupt processing, the main die chip can initiate read and write requests for the registers of the slave die chip to cooperate in completing the interrupt processing, which can improve the transmission and processing efficiency. Moreover, in this way, the slave die chip can be in a low-power or sleep state, thereby reducing the power consumption of the entire chip.

[0020] In a second aspect, an embodiment of the present application further provides an electronic device, including a chip provided in any possible implementation manner of the above first aspect embodiment.

[0021] In a third aspect, an embodiment of the present application further provides an interrupt processing method between die chips, which is applied to a chip. The chip includes at least two die chips, and the at least two die chips include a main die chip and a slave die chip. The method includes: the slave die chip collects the rising edge and interrupt identifier of each interrupt signal from the slave die chip, obtains the interrupt information corresponding to each interrupt signal, and sends each interrupt information to the main die chip, where each interrupt information includes the rising edge and interrupt identifier of the interrupt signal; the main die chip converts the received interrupt information into a pulse interrupt, and performs interrupt processing on the pulse interrupt.

[0022] In a possible implementation manner combining the embodiments of the third aspect, the method further includes: during the process of the main die chip performing interrupt processing on the pulse interrupt, initiating read and write requests for the registers of the slave die chip, and forwarding the read and write requests to the slave die chip; the slave die chip responds to the read and write requests to perform read and write access on the registers of the slave die chip to cooperate in completing the interrupt processing.

[0023] The beneficial effects of the embodiments of the third aspect above can refer to the beneficial effects of the corresponding solutions in the embodiments of the first aspect above.

[0024] Other features and advantages of the present application will be described in the subsequent specification. The objectives and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written specification and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. As shown in the accompanying drawings, the above-mentioned and other objectives, features, and advantages of the present application will become clearer.

[0026] Figure 1 Shows a schematic structural diagram of a chip provided by an embodiment of the present application.

[0027] Figure 2 Shows a schematic principle diagram of the main control module and the IG module when a transmission interruption occurs provided by an embodiment of the present application.

[0028] Figure 3 Shows a schematic principle diagram of the main control module and the IG module when a reception interruption occurs provided by an embodiment of the present application.

[0029] Figure 4 Shows a schematic structural diagram of another chip provided by an embodiment of the present application.

[0030] Figure 5 Shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0031] Figure 6 Shows a schematic flowchart of an inter-die interruption processing method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, but cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0033] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0034] Furthermore, the term "and / or" in the present application is only a relational term describing the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "connection" may be a direct connection or an indirect connection through an intermediate medium.

[0036] In order to improve the interrupt transaction processing between multiple dielets under Chiplet technology, the embodiments of the present application provide an interrupt processing method between dielets. When processing an interrupt across dielets, first collect the edge transitions and interrupt identifiers of each interrupt signal that needs to be processed across dielets to obtain the interrupt information corresponding to each interrupt signal, and then perform cross-dielet transmission on the interrupt information. When processing, first convert the received interrupt information into a pulse interrupt, and then perform interrupt processing on the pulse interrupt, which can improve the transmission and processing efficiency. At the same time, through the cooperation of the main control module, interrupt forwarding module and transmission port in each dielet, an efficient interrupt transmission and processing link is realized, which can efficiently forward and process interrupt transactions.

[0037] Among them, Chiplet technology (chiplet technology) is a modular chip design method. By splitting a complex chip into multiple independent functional modules and then integrating them into the same system through advanced packaging technology. The chip under Chiplet technology includes multiple dielets, and each dielet can implement a specific function. In some application scenarios, each dielet can be a small chip. At this time, the chip can be regarded as composed of multiple small chips that implement specific functions and can be integrated through semiconductor technology.

[0038] The following is combined with Figure 1A description is given of the chip provided by the embodiments of the present application. The chip includes at least two dies, and each die may include a main control module, an interrupt forwarding module (Interrupt Generate, IG), and a transmission port. The main control module is connected to the interrupt forwarding module, the interrupt forwarding module is connected to the transmission port, and each die is connected to other dies through the transmission port. Figure 1 In Figure 1 , int_s represents intr_send, that is, the interrupt sending interface; int_r represents intr_receive, that is, the interrupt receiving interface.

[0039] Figure 1 Only the case of including 2 dies is shown. The chip provided by the embodiments of the present application may include more than 2 dies. Different dies can be connected and communicate through the transmission port, and the Figure 1 chip shown with only 2 dies cannot be regarded as the only implementation manner of the present application.

[0040] The transmission port in the present application may be a D2D (Die to Die) port, which is responsible for information transmission and communication between dies. The D2D port uses the UCIe (Universal Chiplet Interconnect express) bus protocol to forward and transmit the data sent by the interrupt forwarding module and the like.

[0041] The interrupt forwarding module is mainly responsible for forwarding interrupt information. For example, the interrupt forwarding module is configured to forward interrupt information from other dies to the main control module, or forward interrupt information from the main control module to other dies through the transmission port. The interrupt forwarding module may include a forwarder or a forwarding circuit for information forwarding.

[0042] The main control module is responsible for collecting, preprocessing, and forwarding interrupt signals, supports interrupt processing, and may include a processing unit (which may include a central processing unit (CPU) core, that is, a CPU core), registers, a memory, etc. inside. For example, the main control module is configured to send interrupt information to the interrupt forwarding module and perform interrupt processing on the interrupt information sent by the interrupt forwarding module.

[0043] With the die having the above structure, interrupts can be efficiently transmitted and processed across dies. By adopting the cross-die interrupt processing method, the interrupt processing efficiency of the multi-die system can be improved, and the power consumption of the entire chip can be better reduced. For example, when one of the dies is busy, the interrupt information generated by it can be sent to the idle die for processing, thereby improving the efficiency; at the same time, since the chip supports the cross-die interrupt processing method and supports some dies to be in a low-power or sleep state, the power consumption of the entire chip is reduced.

[0044] Interrupt is an important mechanism in a computer system. During the execution of a normal program, due to the occurrence of certain events, the current program needs to be temporarily suspended, and the program execution is transferred to the interrupt service program to serve the temporarily occurring events. After the execution of the interrupt program is completed, it returns to the normal program and continues to run.

[0045] In some possible implementation manners, when the main control module sends interrupt information to the interrupt forwarding module, it is specifically configured to: preprocess multiple interrupt signals from the chiplet, and send the interrupt information obtained after preprocessing to the interrupt forwarding module.

[0046] Among them, the interrupt information includes the edge transition of the interrupt signal and the interrupt identifier. The edge transition of the interrupt signal can be the edge transition when changing from level 0 to level 1, or the edge transition when changing from level 1 to level 0. The interrupt identifier is used to identify the source of the interrupt, and the interrupt identifier can be the identifier of the source end that generates the interrupt signal.

[0047] The main control module is responsible for receiving interrupt signals, supporting pulse or level interrupts, such as receiving interrupt signals from modules such as UART (Universal Asynchronous Receiver Transmitter), DMA (Direct Memory Access), and PMU (Power Management Unit).

[0048] When the main control module preprocesses the received interrupt signals, in one possible implementation manner, it can be to collect the edge transition and the interrupt identifier of each interrupt signal from the chiplet to obtain the interrupt information corresponding to each interrupt signal. That is, in this way, the preprocessor can convert the interrupt signal into interrupt information. In another possible implementation manner, after obtaining the interrupt information corresponding to each interrupt signal, the interrupt information from the same source end within a period of time (configurable) can also be divided into a group, and multiple interrupt information in the same group can be packed. That is, in this way, the preprocessor can include converting the interrupt signal into interrupt information, interrupt grouping, and packing.

[0049] In some possible implementation manners, the main control module is specifically configured to: collect the edge transition and the interrupt identifier of each interrupt signal from the chiplet to obtain the interrupt information corresponding to each interrupt signal; divide the interrupt information from the same source end within a period of time into a group, and pack and send multiple interrupt information in the same group to the interrupt forwarding module. Since there are multiple interrupt information packets, when sending multiple interrupt information packets to the interrupt forwarding module, the multiple interrupt information packets can be sent to the interrupt forwarding module in a certain order (such as the priority of the source end).

[0050] Whether the interrupts come from the same source end can be determined according to the interrupt identifier in the interrupt information. If the interrupt identifiers in two interrupt information are the same, the two interrupts come from the same source end.

[0051] The interrupt signal can be a pulse or level interrupt. When the main control module pre-processes the received interrupt signal, whether it is a pulse or level interrupt, it will collect the transition edge of the interrupt signal, and then package the interrupt information including the transition edge and interrupt flag and send it to the interrupt forwarding module.

[0052] In a possible implementation, the main control module includes: a processing unit and an arbitration unit. The processing unit is configured to collect the transition edge and interrupt flag of each interrupt signal from the core particle, obtain the interrupt information corresponding to each interrupt signal, and group the interrupt information from the same source end within a period of time into a group, and package multiple interrupt information of the same group to obtain an interrupt information packet. The arbitration unit is configured to send the multiple interrupt information packets to the interrupt forwarding module in a certain order.

[0053] The schematic diagram when sending an interrupt is as follows Figure 2 As shown in the figure, no matter it is a pulse or level interrupt, the processing unit will collect the jumping edge of the interrupt signal (intr), and then group the interrupt information including the jumping edge and interrupt flag according to the source end (such as UART, DMA, PMU, etc.) to obtain groups such as G0, G1, G2...Gn, and then package multiple interrupt information of the same group and send them to the arbitration unit (i.e. Figure 2 INTR ARBT in which INTR represents interrupt), the arbitration unit sends multiple interrupt information packets to the IG module in a certain order.

[0054] Among them, when the number of interruptions is small, such as when the number of interruptions is less than the first threshold (configurable), the interruption information does not need to be grouped; when the number of interruptions is large, such as when the number of interruptions is greater than the second threshold (configurable), it is difficult to transmit all the interruption information at one time, so the interruption information is grouped and transmitted, which can be divided into G0~Gn, and then G0~Gn are transmitted in time, which can improve the transmission efficiency.

[0055] In one implementation mode, the processing unit is also configured to determine whether to group the interruption information based on the number of interruption information within a period of time. If the interruption information does not need to be grouped, each interruption information is directly sent to the interruption forwarding module. If the interruption information needs to be grouped, the interruption information from the same source end within a period of time is grouped together, and multiple interruption information of the same group are packaged and then sent to the interruption forwarding module.

[0056] When the main control module performs interrupt processing on the interrupt information sent by the interrupt forwarding module, it is specifically configured to: convert the interrupt information sent by the interrupt forwarding module into a pulse interrupt, and perform interrupt processing on the pulse interrupt. If the interrupt information sent by the interrupt forwarding module is an interrupt information packet (including multiple interrupt information from the same source), the main control module will first parse the interrupt information packet, convert the parsed interrupt information into a pulse interrupt, and then perform interrupt processing on the pulse interrupt.

[0057] Among them, after converting the interrupt information into a pulse interrupt, the interrupt nature of the interrupt source will not be changed. For example, if the interrupt source is a level interrupt, the level nature will not be changed. Therefore, during the process of clearing the interrupt in the interrupt processing, if the interrupt source is a level interrupt, it is necessary to ensure that the interrupt level of the interrupt source is cleared. Therefore, during the interrupt processing, it is necessary to initiate read and write access to the interrupt clear register to cooperate with the completion of the interrupt processing.

[0058] In a possible implementation manner, the principle of the main control module receiving interrupt information from the IG module can be as Figure 3 shown. The receiver in the main control module ( Figure 3 INTR RCV in it, where RCV represents the receiver) sequentially receives each interrupt information packet G0 to Gn from the IG module, and then sends it to the processing unit in the main control module. The processing unit parses it, converts the parsed interrupt information into a pulse interrupt (pulse), and then performs interrupt processing on the pulse interrupt. By grouping the interrupt information and forwarding it sequentially through the arbiter, and receiving it sequentially according to the grouping situation during reception, the transmission processing in the case of a large number of interrupt signals is realized.

[0059] In some possible implementation manners, as Figure 4 shown, each die further includes: a register bus control module (Register Bus Control, RBC), and the register bus control module is connected to the main control module and a transmission port. The main control module is configured to perform read and write access to the register through the register bus control module to cooperate with the completion of the interrupt processing.

[0060] Among them, the RBC module is mainly responsible for the access communication of the register. The main control module can implement register read and write through the RBC module, and here it mainly cooperates with the main control module to complete the interrupt processing. The RBC module is the core hardware module in the computer system for managing the data interaction between the register and the bus. It is responsible for coordinating the access of components such as the CPU, peripherals, and memory to the shared bus resources to ensure efficient and reliable data transmission.

[0061] Figure 4In this context, "req" represents "register request", which is a request to read or write a register, and "ret" represents "response return", which is the returned response, such as the data read. The main control module, RBC module, IG module, and D2D port on different die chips form an efficient interrupt transmission and processing link, enabling the forwarding or reception of interrupt information between die chips and interrupt processing.

[0062] In some possible implementations, in addition to the above-mentioned processing unit, arbiter, and receiver, the main control module may further include registers, memories, etc. The processing unit realizes register reading and writing through the RBC module. The registers here include but are not limited to the clear interrupt register and the interrupt status register.

[0063] The interrupt status register can be used to record the status of interrupt requests that have been triggered but not yet processed in the current system. When an interrupt event occurs, the hardware will automatically set the corresponding status bit of the interrupt to 1 (indicating that the interrupt is pending). The processing unit determines which interrupts need to be processed by reading this register.

[0064] The clear interrupt register is used to explicitly clear the corresponding bits in the interrupt status register, informing the hardware that "this interrupt has been processed", thereby allowing subsequent interrupt requests to be triggered again. The main function of the clear interrupt register is to clear the interrupt status.

[0065] The two die chips on both sides of the D2D port can work independently. The working modes of the two die chips on both sides of the D2D port can be the master-slave die chip mode. At this time, the two die chips are the master die chip (Master Die) and the slave die chip (Slave Die) respectively. Among them, the main control module of the slave die chip can enter the working state or the sleep state. Among them, the main control module in the sleep state is not responsible for the specific processing of interrupts and needs to forward the generated interrupts to the master die chip for specific processing.

[0066] In some possible implementation manners, the above-mentioned at least two die chips may include: a master die chip and a slave die chip. Among them, assuming that the main control module of the slave die chip enters the sleep state, the slave die chip can be configured to collect the rising edge and interrupt identifier of each interrupt signal from the slave die chip to obtain the interrupt information corresponding to each interrupt signal; and divide the interrupt information from the same source within a period of time into a group, and pack the multiple interrupt information in the same group and send it to the master die chip. For example, the main control module in the slave die chip collects the rising edge and interrupt identifier of each interrupt signal from the slave die chip to obtain the interrupt information corresponding to each interrupt signal and divides the interrupt information from the same source within a period of time into a group, and packs the multiple interrupt information in the same group and sends it to the IG module in the slave die chip. The IG module will send the interrupt information packed by the main control module to the master die chip through the D2D port.

[0067] The main die is configured to parse the interrupt information packet from the slave die, convert the parsed interrupt information into a pulse interrupt, and perform interrupt processing on the pulse interrupt. For example, the IG module in the main die receives the interrupt information packet sent by the slave die through the D2D port, and forwards the interrupt information packet to the main control module of the main die. The main control module of the main die parses the interrupt information packet, converts the parsed interrupt information into a pulse interrupt, and performs interrupt processing on the pulse interrupt.

[0068] During the interrupt processing, the main die can initiate read and write requests for the registers of the slave die and forward the read and write requests to the slave die. For example, the main control module in the main die enters the corresponding interrupt service routine according to the interrupt identifier of the pulse interrupt for interrupt processing, initiates read and write requests for the registers of the slave die, and then sends the read and write requests to the RBC module of the main die. The RBC module then forwards the read and write requests to the RBC module of the slave die through the D2D port.

[0069] The slave die is also configured to respond to the read and write requests to perform read and write access to the registers of the slave die to cooperate with the completion of interrupt processing. For example, the RBC module of the slave die receives the read and write requests and then issues them to the corresponding registers inside the main control module, such as the clear interrupt register, the interrupt status register, etc., to complete the interrupt processing.

[0070] The above-mentioned chip can be, but is not limited to, a processor, which can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit, a Multimedia Application Processor (MAP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. Or the processor can also be any conventional processor, etc.

[0071] The embodiment of the present application also provides an electronic device, which includes the above-mentioned chip. When the chip is a processor, in a possible implementation manner, as Figure 5 shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor.

[0072] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to receive and transmit data. The memory is used to store computer programs, and the processor is used to execute software function modules or computer programs stored in the memory.

[0073] The memory can be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0074] Among them, the above-mentioned electronic devices include, but are not limited to, mobile phones, tablets, computers, network devices, servers, etc.

[0075] The embodiment of the present application also provides an inter-die interruption processing method, which is applied to the above-mentioned chip. The chip includes at least two dies, and the at least two dies include a master die and a slave die. The principle of the method provided by the embodiment of the present application will be described below in combination with Figure 6 to illustrate the principle of the method provided by the embodiment of the present application.

[0076] S1: The slave die collects the edge transitions and interruption identifiers of each interruption signal from the slave die, obtains the interruption information corresponding to each interruption signal, and sends each interruption information to the master die.

[0077] It can be that the main control module in the slave die collects the edge transitions and interruption identifiers of each interruption signal from the slave die, obtains the interruption information corresponding to each interruption signal, and then sends the interruption information to the IG module in the slave die. The IG module will send the interruption information sent by the main control module to the master die through the D2D port.

[0078] In some possible embodiments, when the dielet sends each interrupt message to the master dielet, it may first group the interrupt messages from the same source within a period of time, pack multiple interrupt messages in the same group, and then send them to the master dielet. For example, the main control module in the dielet first groups the interrupt messages from the same source within a period of time, packs multiple interrupt messages in the same group, and then sends them to the IG module in the dielet. The IG module will send the interrupt messages packed by the main control module to the master dielet through the D2D port.

[0079] S2: The master dielet converts the received interrupt messages into pulse interrupts and performs interrupt processing on the pulse interrupts.

[0080] In a possible embodiment, the IG module in the master dielet may receive the interrupt messages sent by the dielet through the D2D port, then convert the received interrupt messages into pulse interrupts, and perform interrupt processing on the pulse interrupts.

[0081] In a possible embodiment, if the dielet sends the interrupt messages in groups and packs them when sending each interrupt message to the master dielet, the IG module in the master dielet may receive the interrupt message packet sent by the dielet through the D2D port, forward the interrupt message packet to the main control module of the master dielet, the main control module of the master dielet parses the interrupt message packet, converts the parsed interrupt messages into pulse interrupts, and performs interrupt processing on the pulse interrupts.

[0082] In some possible embodiments, the method further includes: during the process of the master dielet performing interrupt processing on the pulse interrupts, initiating read and write requests for the registers of the dielet and forwarding the read and write requests to the dielet; the dielet responds to the read and write requests to perform read and write access to the registers of the dielet to cooperate with the completion of interrupt processing. For example, the main control module in the master dielet enters the corresponding interrupt service program according to the interrupt identifier of the pulse interrupt to perform interrupt processing, initiates read and write requests for the registers of the dielet, and then sends the read and write requests to the RBC module of the master dielet. The RBC module of the master dielet forwards the read and write requests to the RBC module of the dielet through the D2D port. The RBC module of the dielet receives the read and write requests and then issues them to the corresponding registers inside the main control module, such as the interrupt clear register, the interrupt status register, etc., to complete the interrupt processing.

[0083] The solution provided by the method embodiment has the same implementation principle and the same technical effects as those of the foregoing chip embodiment. For the sake of brief description, for the parts not mentioned in the method embodiment, reference may be made to the corresponding content in the foregoing chip embodiment.

[0084] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0085] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0086] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that, Comprising: At least two die chips, each die chip comprising: a main control module, an interrupt forwarding module, and a transmission port; the main control module is connected to the interrupt forwarding module, the interrupt forwarding module is connected to the transmission port, and each die chip is connected to other die chips through the transmission port; The interrupt forwarding module is configured to forward interrupt information from other die chips to the main control module, or forward interrupt information from the main control module to other die chips through the transmission port; The main control module is configured to send interrupt information to the interrupt forwarding module and perform interrupt processing on the interrupt information sent from the interrupt forwarding module.

2. The chip according to claim 1, wherein The main control module is specifically configured to: preprocess a plurality of interrupt signals from the die chip and send the interrupt information obtained after preprocessing to the interrupt forwarding module; wherein the interrupt information includes the transition edge of the interrupt signal and the interrupt identifier.

3. The chip according to claim 2, wherein The main control module is specifically configured to: Collect the transition edge and interrupt identifier of each interrupt signal from the die chip to obtain the interrupt information corresponding to each interrupt signal; Group the interrupt information from the same source end within a period of time, and pack and send multiple interrupt information in the same group to the interrupt forwarding module.

4. The chip according to claim 3, wherein The main control module includes: A processing unit configured to collect the transition edge and interrupt identifier of each interrupt signal from the die chip to obtain the interrupt information corresponding to each interrupt signal, and group the interrupt information from the same source end within a period of time, and pack multiple interrupt information in the same group to obtain an interrupt information packet; An arbitration unit configured to send multiple interrupt information packets to the interrupt forwarding module in a certain order.

5. The chip according to any one of claims 1-4, characterized in that, The main control module is specifically configured to: Convert the interrupt information sent from the interrupt forwarding module into a pulse interrupt and perform interrupt processing on the pulse interrupt.

6. The chip according to claim 4, wherein Each die chip further includes: a register bus control module, and the register bus control module is connected to the main control module and the transmission port; The main control module is configured to perform read and write access to the register through the register bus control module to cooperate with the completion of interrupt processing.

7. The chip according to claim 6, characterized in that, The at least two die chips include: a main die chip and a slave die chip; The slave die chip is configured to collect the transition edge and interrupt identifier of each interrupt signal from the slave die chip to obtain the interrupt information corresponding to each interrupt signal; and group the interrupt information from the same source end within a period of time, and pack and send multiple interrupt information in the same group to the main die chip; The main die chip is configured to parse the interrupt information packet from the slave die chip, convert the parsed interrupt information into a pulse interrupt, and perform interrupt processing on the pulse interrupt; and during the interrupt processing, initiate read and write requests for the registers of the slave die chip and forward the read and write requests to the slave die chip; The slave die chip is further configured to respond to the read and write requests to perform read and write access to the registers of the slave die chip to cooperate with the completion of interrupt processing.

8. An electronic device, characterized in that, Comprising the chip according to any one of claims 1-7.

9. An interruption handling method between dies, characterized in that, Applied to a chip, the chip includes at least two dielets, the at least two dielets include a master dielet and a slave dielet, and the method includes: The slave dielet collects the edge transitions and interrupt identifiers of each interrupt signal from the slave dielet, obtains the interrupt information corresponding to each interrupt signal, and sends each interrupt information to the master dielet, where each interrupt information includes the edge transition of the interrupt signal and the interrupt identifier; The master dielet converts the received interrupt information into a pulse interrupt and performs interrupt processing on the pulse interrupt.

10. The method according to claim 9, wherein The method further includes: During the process of performing interrupt processing on the pulse interrupt, the master dielet initiates read and write requests for the registers of the slave dielet and forwards the read and write requests to the slave dielet; The slave dielet responds to the read and write requests to perform read and write access to the registers of the slave dielet to cooperate with the completion of interrupt processing.

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