Data transmission method, system and device, electronic equipment and computer storage medium

Abstract

The embodiment of the invention discloses a data transmission method, system and device, electronic equipment and a computer storage medium, the method is applied to a DMA controller, and the method comprises the following steps: receiving at least one DMA descriptor sent by a processor; determining an executable state of the DMA descriptor according to an execution trigger flag bit in the DMA descriptor; and in response to the executable state being executable, triggering execution of data transmission corresponding to the DMA descriptor, and changing the execution triggering flag bit in the DMA descriptor. Wherein the execution trigger flag bit is used for representing a dependency relationship between at least one piece of data transmission corresponding to the DMA descriptor. Therefore, the DMA controller judges whether the corresponding DMA descriptor can be executed or not according to the execution trigger flag bit in the DMA descriptor, so that data transmission with a dependency relationship can be quickly realized, resources occupied by the processor can be reduced, and the use efficiency of the processor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to a data transmission method, system, device, electronic device, and computer storage medium. Background Art

[0002] Direct Memory Access (DMA) is a function provided by some computer bus architectures, which enables data to be transferred between an attached device (such as a hard disk) and computer memory. The computer main control unit (including processors such as CPU and MCU) only needs to issue a corresponding data transmission task to the DMA controller, thereby releasing the processor resources for other tasks.

[0003] The existing direct memory access process between chips is usually as follows: The source chip sends a request to the destination chip to inquire whether the destination chip is ready to receive data. After the destination chip replies that it is ready, the processor of the source chip issues a DMA descriptor (i.e., a transmission DMA descriptor) to the DMA work queue to the DMA controller, and the DMA controller calls the DMA engine to perform the corresponding data transfer. When the destination chip is not ready to receive, the processor waits until the destination chip is ready. That is to say, in the prior art, it is necessary for the processor to determine whether the DMA descriptor can be executed. If it can be executed, the DMA descriptor is added to the DMA work queue; if it cannot be executed, it waits until it can be executed before operating. This will cause a relatively large occupation of processor resources and also affect the processor's emission of other instruction streams, ultimately resulting in low processor utilization efficiency. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a data transmission method, system, device, electronic device, and computer storage medium to reduce the occupied resources of the processor and improve the processor utilization efficiency.

[0005] In a first aspect, an embodiment of the present invention aims to provide a data transmission method, which is applied to a DMA controller. The method includes:

[0006] Receiving at least one DMA descriptor sent by a processor, where the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to represent the dependency relationship between at least one data transfer corresponding to the DMA descriptor;

[0007] Determining the executable state of the DMA descriptor according to the execution trigger flag bit;

[0008] In response to the executable state being executable, triggering the execution of the data transfer corresponding to the DMA descriptor and changing the execution trigger flag bit in the DMA descriptor.

[0009] Furthermore, the execution trigger flag bit includes a first flag bit and a second flag bit. The first flag bit is used to represent the trigger parameter of the data transmission corresponding to the DMA descriptor, and the second flag bit is used to represent other data transmissions on which the data transmission corresponding to the DMA descriptor depends;

[0010] Determining the executable state of the DMA descriptor according to the execution trigger flag bit includes:

[0011] In response to the values on the first flag bit and the second flag bit satisfying a preset condition, determining that the executable state of the DMA descriptor is executable;

[0012] In response to the values on the first flag bit and the second flag bit not satisfying the preset condition, determining that the executable state of the DMA descriptor is not executable;

[0013] Changing the execution trigger flag bit in the DMA descriptor includes: incrementing the value on the first flag bit by 1.

[0014] Furthermore, the preset condition is that the value on the first flag bit is equal to the value on the second flag bit, or the preset condition is that the value on the first flag bit is greater than or equal to the value on the second flag bit.

[0015] Furthermore, the DMA descriptor further includes a third flag bit, and the third flag bit is used to represent the trigger mode of the data transmission corresponding to the DMA descriptor;

[0016] Wherein, the trigger mode at least includes: triggering the data transmission corresponding to other DMA descriptors after the data transmission corresponding to the DMA descriptor is triggered, and triggering the data transmission corresponding to other DMA descriptors after the data transmission corresponding to the DMA descriptor is completed.

[0017] Furthermore, the DMA descriptor further includes a fourth flag bit, and the fourth flag bit is used to represent the process state of the data transmission corresponding to the DMA descriptor.

[0018] Furthermore, the DMA descriptor further includes a fifth flag bit, and the fifth flag bit is used to represent whether to synchronize the process state of the data transmission corresponding to the DMA descriptor to the destination side of the data transmission corresponding to the DMA descriptor.

[0019] Furthermore, the DMA descriptor further includes a sixth flag bit, and the sixth flag bit is used to represent other data transmissions on which the data transmission on the destination side depends.

[0020] Further, the DMA descriptor further includes a seventh flag bit, which is used to indicate whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the source side of the data transfer corresponding to the DMA descriptor.

[0021] In a second aspect, an embodiment of the present invention aims to provide a data transfer system, the system includes:

[0022] A processor, configured to generate and send at least one DMA descriptor;

[0023] A DMA controller, configured to receive at least one DMA descriptor sent by the processor, the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to indicate the dependency relationship between at least one data transfer corresponding to the DMA descriptor; determine the executable state of the DMA descriptor according to the execution trigger flag bit; in response to the executable state being executable, trigger the execution of the data transfer corresponding to the DMA descriptor, and change the execution trigger flag bit in the DMA descriptor;

[0024] A source chip, configured to send the transmission data corresponding to the at least one DMA descriptor;

[0025] A destination chip, configured to receive the transmission data sent by the source chip.

[0026] In a third aspect, an embodiment of the present invention aims to provide a data transfer device, which is applied to a DMA controller, and the device includes:

[0027] A receiving unit, configured to receive at least one DMA descriptor sent by the processor, the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to indicate the dependency relationship between at least one data transfer corresponding to the DMA descriptor;

[0028] A judging unit, configured to determine the executable state of the DMA descriptor according to the execution trigger flag bit;

[0029] A transmission unit, configured to, in response to the executable state being executable, trigger the execution of the data transfer corresponding to the DMA descriptor, and change the execution trigger flag bit in the DMA descriptor.

[0030] In a fourth aspect, an embodiment of the present invention aims to provide an electronic device, including a memory and a DMA controller, the memory is used to store one or more computer program instructions, wherein, the one or more computer program instructions are executed by the DMA controller to implement the method described in any one of the above.

[0031] Fifth aspect, embodiments of the present invention aim to provide a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method steps described in any of the above are implemented.

[0032] The technical solution of the embodiments of the present invention receives a DMA descriptor sent by a processor through a DMA controller, determines the executable state of the DMA descriptor according to the execution trigger flag bit in the DMA descriptor, and in response to the executable state being that the DMA descriptor is executable, executes the data transmission corresponding to the DMA descriptor. Thus, while implementing the corresponding data transmission by executing the DMA descriptor, by judging whether the corresponding DMA descriptor is executable according to the execution trigger flag bit in the DMA descriptor through the DMA controller, the occupied resources of the processor can be reduced, and the usage efficiency of the processor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0034] Figure 1 is a schematic diagram of the data transmission system according to the embodiments of the present invention;

[0035] Figure 2 is a flowchart of the data transmission method according to the embodiments of the present invention;

[0036] Figure 3 is a schematic diagram of the DMA descriptor according to the embodiments of the present invention;

[0037] Figure 4 is a schematic diagram of the data transmission process according to the embodiments of the present invention;

[0038] Figure 5 is another schematic diagram of the DMA descriptor according to the embodiments of the present invention;

[0039] Figure 6 is a schematic diagram of the data transmission device according to the embodiments of the present invention;

[0040] Figure 7 is a schematic diagram of the electronic device according to the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, elements and circuits are not described in detail.

[0042] In addition, those of ordinary skill in the art should understand that the accompanying drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0043] Unless the context clearly requires otherwise, words such as "including", "comprising" and the like in the entire application document shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0044] In the description of this application, it should be understood that terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0045] The DMA (Direct Memory Access) technology, through the cooperation of the processor and the DMA controller, enables the data in the source chip to be directly transmitted to the destination chip, with fast data transmission speed and high data transmission efficiency. However, in the existing process of data transmission implemented by the DMA technology, the processor needs to determine whether the DMA descriptor can be executed. If it can be executed, the DMA descriptor is added to the DMA work queue; if it cannot be executed, it waits until it can be executed before operating. This will cause a relatively large consumption of processor resources and also affect the processor's emission of other instruction streams, ultimately resulting in low processor utilization efficiency. In view of this, the embodiments of the present invention aim to provide a data transmission method to reduce the occupied resources of the processor and improve the processor utilization efficiency during the data transmission process based on the DMA technology.

[0046] Figure 1 It is a schematic diagram of the data transmission system according to the embodiments of the present invention. As Figure 1 shown, the data transmission system in this embodiment includes a processor 1, a DMA controller 2, a source chip 3 (i.e., the source side of the data transmission corresponding to a DMA descriptor) and a destination chip 4 (i.e., the destination side of the data transmission corresponding to a DMA descriptor). Optionally, the processor 1 and the DMA controller 2 in this embodiment can be integrally arranged on the source chip 3 or the destination chip 4, or can be separately arranged at positions outside the source chip 3 and the destination chip 4, and no limitation is imposed here.

[0047] Before transmitting the data in the source chip 3 to the destination chip 4, the processor 1 first generates a DMA descriptor corresponding to the current data transmission (also known as data transfer) task. The processor 1 sends the DMA descriptor to the DMA controller 2, and the DMA controller 2 determines whether the DMA descriptor is executable. After determining that the DMA descriptor is executable, the DMA engine is called to send the data to be transmitted corresponding to the DMA descriptor in the source chip 3 to the destination chip 4, realizing the data transmission between the source chip 3 and the destination chip 4.

[0048] It should be noted that in a system, when performing DMA transfer between a source chip and a destination chip, the same DMA descriptors are set on the source side and the destination side. Different parameters in the DMA descriptors are used to characterize the dependency relationship of the data to be transferred, and it is ensured that the settings of the DMA descriptors on both sides are consistent. Specifically, for the same data transfer process, the DMA descriptors on the source side and the destination side need to contain the same information, such as parameters like source address, destination address, transfer length, transfer direction, etc. On the source side, the DMA descriptor needs to be written into the DMA controller and the DMA operation starts; on the destination chip side, the same DMA descriptor needs to be set and wait for the arrival of the DMA operation completion signal.

[0049] Optionally, in the DMA controller of this embodiment, multiple DMA descriptors can be stored simultaneously in the form of a queue to form a DMA descriptor queue. At the same time, a threshold is set for the number of DMA descriptors in the DMA descriptor queue. When the number of DMA descriptors to be executed exceeds the threshold, the DMA descriptors exceeding the threshold need to wait until there is an empty position in the DMA descriptor queue before they can be added, so as to avoid slow data transfer process caused by too many DMA descriptors and affect the data transfer efficiency. When the number of DMA descriptors is greater than the number of DMA descriptors that can be accommodated in the descriptor queue or the storage space is insufficient due to other reasons, the DMA descriptors can be continuously stored in other storage areas (such as DDR / HBM) in the source chip to ensure the data transfer efficiency between the source chip and the destination chip. Further, the storage space corresponding to the DMA descriptor queue in the DMA controller can be recycled. In this embodiment, after the data transfer process corresponding to the current DMA descriptor ends, the DMA descriptor will be cleared from the DMA descriptor queue to provide conditions for new DMA descriptors to be added to the DMA descriptor queue in a timely manner.

[0050] The technical solution of this embodiment generates a DMA descriptor corresponding to a data transfer task through a processor and sends the DMA descriptor to the DMA descriptor queue in the DMA controller. The DMA controller judges each DMA descriptor to determine the executable state of the DMA descriptor, and transfers the data in the source chip to the destination chip after determining that the DMA descriptor is executable, realizing the data transfer between the source chip and the destination chip. Thus, while implementing the corresponding data transfer by executing the DMA descriptor, the DMA controller is used to replace the processor in the prior art to judge whether the DMA descriptor is executable, which can reduce the resource occupation of the processor and improve the usage efficiency of the processor.

[0051] Figure 2 is the flowchart of the data transfer method of the embodiment of the present invention. As Figure 2As shown in the figure, the data transmission method in this embodiment is applied to a DMA controller and includes the following steps.

[0052] In step S100, receive at least one DMA descriptor sent by the processor.

[0053] In this embodiment, the descriptor is a DMA descriptor (also known as a transfer DMA descriptor, Direct Memory Access Descriptor), which is used to describe various parameters and control information of the data transmission corresponding to the DMA operation, including basic parameters such as the destination address (including the address of the destination chip), the source address (including the address of the source chip), the data type, and the transfer shape (e.g., transfer length, transfer direction).

[0054] Furthermore, in addition to the above basic parameters, the DMA descriptor in this embodiment further includes an execution trigger flag bit. Among them, the execution trigger flag bit is used to characterize the dependency relationship between at least one data transmission corresponding to the DMA descriptor, that is, the dependency relationship between data transmissions is the dependency relationship between DMA descriptors. For example, DMA descriptor - 1 is used to implement the transmission of data A, DMA descriptor - 2 is used to implement the transmission of data B, DMA descriptor - 3 is used to implement the transmission of data C, and data A and data B can only be transmitted after the transmission of data C is completed. Then the transmission of data A depends on the transmission of data C, that is, DMA descriptor - 1 depends on DMA descriptor - 3, and the transmission of data B depends on the transmission of data C, that is, DMA descriptor - 2 depends on DMA descriptor - 3.

[0055] In this embodiment, the software can set the execution trigger flag bit of each DMA descriptor corresponding to the data transmission according to the dependency relationship between data transmissions. Then the processor sends the DMA descriptor to the DMA, so that the DMA controller automatically completes the data transmission operation according to the information of the DMA descriptor and sends an interrupt signal indicating the completion of the transmission to the processor after the data transmission is completed.

[0056] In step S200, determine the executable state of the DMA descriptor according to the execution trigger flag bit.

[0057] In this embodiment, the DMA controller determines the executable state of the DMA descriptor according to the execution trigger flag bit of the DMA descriptor to judge when to perform data transmission. Each data transmission is implemented based on a DMA descriptor. If the data on which a certain data depends has been transmitted, the transmission of this data can be performed, that is, when m data are received, n data can be sent.

[0058] Optionally, the execution trigger flag bits in this embodiment include a first flag bit (send_enable_addr) and a second flag bit (send_enable_golden). Among them, the first flag bit is used to represent the trigger parameter for the data transmission corresponding to the DMA descriptor, and the second flag bit is used to represent other data transmissions on which the data transmission corresponding to the DMA descriptor depends.

[0059] Further, in this embodiment, the executable state of the DMA descriptor is determined according to the first flag bit and the second flag bit. Correspondingly, in this embodiment, determining the executable state of the DMA descriptor according to the execution trigger flag bits includes: in response to the values on the first flag bit and the second flag bit satisfying a preset condition, determining that the executable state of the DMA descriptor is executable; in response to the values on the first flag bit and the second flag bit not satisfying the preset condition, determining that the executable state of the DMA descriptor is not executable.

[0060] In an alternative implementation, the preset condition in this embodiment is that the value on the first flag bit is equal to the value on the second flag bit. Correspondingly, the DMA controller determines that the executable state of the corresponding DMA descriptor is executable in response to the value on the first flag bit being equal to the value on the second flag bit. Further, in this embodiment, after the data transmission corresponding to the current descriptor is completed, other data that has a dependency relationship with the data corresponding to the current descriptor will be triggered in sequence. Thus, in this embodiment, the executable state of the DMA descriptor is determined by judging whether the values on the first flag bit and the second flag bit are the same, and when the corresponding values of the first flag bit and the second flag bit are the same, the data transmission from the source chip to the destination chip is triggered.

[0061] In another alternative implementation, the preset condition in this embodiment is that the value on the first flag bit is greater than or equal to the value on the second flag bit. Correspondingly, the DMA controller determines that the executable state of the DMA descriptor is executable in response to the value on the first flag bit being greater than or equal to the value on the second flag bit. Further, in this embodiment, after the data transmission corresponding to the current descriptor is completed, other data that has a dependency relationship with the data corresponding to the current descriptor can be triggered simultaneously.

[0062] In step S300, trigger the execution of the data transmission corresponding to the DMA descriptor and change the execution trigger flag bits in the DMA descriptor.

[0063] In this embodiment, after determining that the DMA descriptor is executable, trigger the data transmission corresponding to the DMA descriptor, and by executing the data transmission corresponding to the DMA descriptor, realize the data transmission from the source chip to the destination chip.

[0064] Further, in this embodiment, after triggering the data transfer corresponding to the DMA descriptor, for data transfers with dependencies, the execution trigger flag bit in the DMA descriptor is changed. Changing the execution trigger flag bit in the DMA descriptor indicates that the data transfer corresponding to the current DMA descriptor is completed, and the data transfer dependent on this transfer can be triggered for execution.

[0065] Optionally, changing the execution trigger flag bit in the DMA descriptor in this embodiment includes: incrementing the value of the first flag bit by 1. Wherein, incrementing the value of the first flag bit by 1 indicates that the data transfer corresponding to the DMA descriptor is completed, and further data transfers dependent on the data transfer corresponding to this DMA descriptor can be triggered for execution. Further, multiple data transfers dependent on this DMA descriptor can be triggered separately or simultaneously, and the setting of the triggering method can be determined according to the preset conditions corresponding to the executable state of the DMA descriptor.

[0066] Taking three DMA descriptors with the values of the first flag bit being 6, 7, and 8 respectively, which are dependent on the data transfer corresponding to the descriptor with the value of the first flag bit being 5 as an example, in an alternative implementation, when the preset condition is that the value of the first flag bit is equal to the value of the second flag bit, in this embodiment, after the data transfer corresponding to the descriptor with the value of the first flag bit being 5 is completed, incrementing the value of the first flag bit by 1 triggers the data transfer corresponding to the descriptor with the value of the first flag bit being 6; then incrementing the value of the first flag bit by 1 triggers the data transfer corresponding to the descriptor with the value of the first flag bit being 7 (at this time, after 6 is triggered, 7 is triggered next, and the data corresponding to 6 and 7 can be transferred in parallel); incrementing the value of the first flag bit by 1 triggers the data transfer corresponding to the descriptor with the value of the first flag bit being 8.

[0067] Further, in this embodiment, it is possible to determine whether to trigger a data transfer before sending or after sending. That is, determining whether to trigger the transfer of data 6, 7, and 8 can occur before or after the sending of data 5 corresponding to the descriptor with the value of the first flag bit being 5. At the same time, the triggering operation in this embodiment is sequential triggering, but the data transfer can be parallel transfer.

[0068] In another alternative implementation, when the preset condition is that the value of the first flag bit is greater than or equal to the value of the second flag bit, in this embodiment, after the data transfer corresponding to the descriptor with the value of the first flag bit being 5 is completed, incrementing the value of the first flag bit by 1 can simultaneously trigger the data transfers corresponding to 6, 7, and 8. At the same time, the data transfers corresponding to data 6, 7, and 8 can be transferred in parallel to improve the data transfer efficiency.

[0069] The technical solution of the embodiment of the present invention receives the DMA descriptor sent by the processor through the DMA controller, determines the executable state of the DMA descriptor according to the execution trigger flag bit in the DMA descriptor, and in response to the executable state being that the DMA descriptor is executable, executes the data transfer corresponding to the DMA descriptor. Thus, while implementing the corresponding data transfer by executing the DMA descriptor, the DMA controller determines whether the corresponding DMA descriptor is executable according to the execution trigger flag bit in the DMA descriptor, avoiding the processor from judging the executable state of the DMA descriptor, which can reduce the occupied resources of the processor and improve the usage efficiency of the processor. It should be noted that the above example in this embodiment is described by taking the data transfer process corresponding to one DMA descriptor as an example. However, in the actual DMA data transfer process, the DMA descriptor queue on the DMA controller side usually includes at least one DMA descriptor. In this embodiment, the executable states of each DMA descriptor can be respectively judged, and the corresponding data transfer process is executed when the DMA descriptor is executable.

[0070] Optionally, to save the DMA descriptor queue space in the DMA controller, in this embodiment, while one DMA descriptor corresponds to one first flag bit, the first flag bits of different DMA descriptors can be represented by the same value, which can save register resources while enabling parallel processing of the data transfers corresponding to multiple DMA descriptors.

[0071] Further, when one first flag bit corresponds to multiple DMA descriptors, the second flag bits corresponding to each DMA descriptor are preferably represented by different numerical values, so as to identify different DMA descriptors through one first flag bit value, save the DMA descriptor queue space in the DMA controller, and be able to distinguish each DMA descriptor through different second flag bits, thereby facilitating the processing of the data transfers corresponding to each DMA descriptor and improving the overall data transfer efficiency of the DMA descriptor queue.

[0072] Further, the address range corresponding to the first flag bit in this embodiment and the DMA descriptor queue of the data to be transferred are stored in the physical memory close to the DMA controller, which can further shorten the time required for data transfer and improve the data transfer efficiency.

[0073] Optionally, to facilitate understanding of the execution trigger flag bit in the DMA descriptor, in this embodiment, a schematic diagram of the DMA descriptor is shown in Figure 3. As Figure 3As shown, the first flag bit (send_enable_addr) in this embodiment is used to represent the trigger parameter for the data transmission corresponding to the DMA descriptor, and the corresponding bit width is 32 bits. The second flag bit (send_enable_golden) is used to represent other data transmissions on which the data transmission corresponding to the DMA descriptor depends, including data transmissions that depend on sending or receiving. The value on the second flag bit is set according to the number of data transmissions that depend on sending or receiving, and the corresponding bit width is 16 bits. The executable state of the corresponding DMA descriptor is determined by judging whether the values on the first flag bit and the second flag bit are the same.

[0074] Optionally, in this embodiment, the setting methods of the first flag bit and the second flag bit are illustrated by the following examples. For example, assume that the source chip A needs to send data 1, data 2, data 3, data 4, data 5, and data 6 to the destination chip B. However, data 4 can only be sent after data 1 and data 2 have both been sent; data 5 can only be sent after data 6 has been sent; data 1, data 2, data 3, and data 6 do not depend on other data transmissions for sending and can be sent directly. That is, data 4 has a dependency relationship with data 1 and data 2, data 5 has a dependency relationship with data 6, and there is no dependency relationship among data 1, data 2, data 3, and data 6. Therefore, the values on the first flag bit send_enable_addr corresponding to data 1, data 2, and data 4 can be set to be the same, and the initial value is set to 0. The value on the second flag bit send_enable_golden corresponding to data 4 is set to 2; after data 1 is sent, the parameter send_enable_addr of data 1, data 2, and data 4 is incremented by 1, and after data 2 is sent, the parameter send_enable_addr of data 1, data 2, and data 4 is incremented by 1. After both data 1 and data 2 are sent, the value of send_enable_addr is 2, which is equal to the value of send_enable_golden of data 4, which is 2. At this time, data 4 can be sent. The values on the first flag bit send_enable_addr corresponding to data 5 and data 6 are set to be the same, and the initial values are both set to 0. The second flag bit send_enable_golden corresponding to data 5 (the number of data transmissions that data 5 depends on for sending is 1) is set to 1, and the send_enable_golden of data 6 (data 6 does not depend on other data transmissions for sending) is set to 0; the send_enable_golden of data 3 is set to 0.

[0075] For ease of understanding, in this embodiment, the upper value operation of the first flag bit (i.e., changing the first flag bit in the DMA descriptor execution trigger flag bit) is described in combination with different scenarios. For example, when the processing mode of triggering one transmission after one reception is adopted, assuming that the second flag bit send_enable_golden for one transmission is 1, then after this one reception is completed (i.e., the destination chip receives the data corresponding to the current DMA descriptor transmitted from the source chip), the first flag bit send_enable_addr will be incremented by 1 (the initial value is 0). At this time, the values of send_enable_golden and send_enable_addr are equal, triggering this transmission.

[0076] For another example, when the processing mode of triggering one transmission after N receptions is adopted, assuming that the value of send_enable_golden for one transmission is N, then each time a reception is completed, the value of send_enable_addr will be incremented by 1 (the initial value is 0). When N receptions are all completed, the value of send_enable_addr becomes N. In this way, the values of send_enable_golden and send_enable_addr are equal, triggering this transmission.

[0077] For yet another example, when the working mode of triggering M transmissions after N receptions is adopted, assuming that the values of send_enable_golden for M transmissions are N + 1, N + 2, N + 3,..., N + M - 1 respectively. The send_enable_addr for M transmissions is the same address. When N receptions are all completed, the value of send_enable_addr will become N. When the value of send_enable_addr is equal to N, the first transmission is triggered, and at the same time, the value of send_enable_addr is incremented by 1 to become N + 1. When the value of send_enable_addr is equal to N + 1, the second transmission is triggered, and at the same time, the value of send_enable_addr is incremented by 1 to become N + 2, and so on, until the (M - 1)-th transmission is triggered, and at the same time, the value of send_enable_addr is incremented by 1 to become N + M - 1. When the value of send_enable_addr is equal to N + M - 1, the M-th transmission is triggered, and at the same time, the value of send_enable_addr is cleared to zero.

[0078] Furthermore, while the DMA descriptor in this embodiment includes the first flag bit and the second flag bit among the above-mentioned execution trigger flag bits, it also includes a third flag bit (send_enable_op). The third flag bit is used to characterize the triggering mode of the data transmission corresponding to the DMA descriptor. Among them, the triggering mode at least includes: triggering the data transmission corresponding to other DMA descriptors after the data transmission corresponding to the DMA descriptor is triggered, and triggering the data transmission corresponding to other DMA descriptors after the data transmission corresponding to the DMA descriptor is completed.

[0079] Specifically, the corresponding bit width of the third flag bit is 4 bits, and the corresponding values are the first value 0 and non-first values 1, 2, and 3. When the third flag bit is 0, the data transmission corresponding to the corresponding DMA descriptor is directly triggered. When the third flag bit is 1, after triggering the data transmission of the current DMA descriptor, the first flag bit in the current DMA descriptor is reset or cleared. At this time, there are no other DMA descriptors or other DMA descriptors with dependencies after the execution of the current DMA descriptor is completed. When the third flag bit is 2, after triggering the data transmission of the data corresponding to the current DMA descriptor, the first flag bit is first incremented (that is, the value on the send_enable_addr of the source chip is incremented by 1) to trigger the data transmission corresponding to other DMA descriptors, and then the data transmission of the data corresponding to the current DMA descriptor is started. That is, other DMA descriptors are triggered after the current DMA descriptor is triggered. When the third flag bit is 3, after the current DMA descriptor is triggered and the data transmission of the data corresponding to the current DMA descriptor is completed, the first flag bit of the current DMA descriptor is then incremented (that is, the value on the send_enable_addr of the source chip is incremented by 1).

[0080] Furthermore, the DMA descriptor in this embodiment also includes a fourth flag bit (trans_op_type). The fourth flag bit is used to characterize the process state of the data transmission corresponding to the DMA descriptor. Specifically, the corresponding bit width of the fourth flag bit in this embodiment is 1 bit, and the corresponding values are the first value 0 and the non-first value 1. When the fourth flag bit is the first value 0, this DMA data transmission is enabled, that is, the data transmission corresponding to the current DMA descriptor is enabled, and the process state of the data transmission corresponding to the current DMA descriptor is the start of transmission. When the fourth flag bit is the non-first value 1, this DMA data transmission is prohibited, that is, the data transmission corresponding to the current DMA descriptor is prohibited, and the process state of the data transmission corresponding to the current DMA descriptor is the end of transmission.

[0081] Further, the DMA descriptor in this embodiment further includes a fifth flag bit dst_op_type, which is used to indicate whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor. Specifically, the corresponding bit width of the fifth flag in this embodiment is 1 bit, and the corresponding values are the first value 0 and a non-first value 1. When the fifth flag bit is the first value 0, no operation is performed, that is, the process state of the data transfer corresponding to the DMA descriptor is not synchronized to the destination side of the data transfer corresponding to the DMA descriptor. When the fifth flag bit is the non-first value 1, the process state of the data transfer corresponding to the DMA descriptor is synchronized to the destination side of the data transfer corresponding to the DMA descriptor.

[0082] Further, the DMA descriptor in this embodiment further includes a sixth flag bit dst_enable_addr, which is used to indicate other data transfers on which the data transfer on the destination side depends, and the corresponding bit width is 32 bits. By performing an increment operation on the sixth flag bit, the process state of the data transfer corresponding to the DMA descriptor is synchronized to the destination side of the data transfer corresponding to the DMA descriptor. Specifically, when the value of the fifth flag bit is 1, the increment operation is implemented by adding 1 to the value on the sixth flag bit dst_enable_addr, so as to synchronize the process state of the data transfer corresponding to the current DMA descriptor to the destination side of the corresponding data transfer, thereby triggering the destination chip to perform a look-up table operation after receiving the data transmitted by the source chip, and acting as the source chip to transmit data to other chips, thereby realizing the data transfer from the source chip to the destination chip and from the destination chip to other chips.

[0083] Further, after the data transfer corresponding to the current DMA descriptor is completed, in this embodiment, by setting the enable address of the destination chip, the destination chip, after receiving the data transmitted by the source chip, uses the enable address as the start address to transmit data outward, thereby realizing the data transfer from the source chip to the destination chip and then from the destination chip to other chips, enabling the data transfer to play a greater role and improving the data usage efficiency.

[0084] It should be noted that the respective flag bits in this embodiment are set to implement DMA data transfer, and the bit widths of the respective flag bits and the representation contents corresponding to different values can be adjusted according to the actual usage scenario. At the same time, when the fourth flag bit indicates the prohibition of the data transfer corresponding to the current DMA descriptor in this embodiment, it does not prevent the judgment and execution of the third flag bit and the fifth flag bit.

[0085] Figure 4 is a schematic diagram of the data transfer process of the embodiment of the present invention. As Figure 4 shown, in this embodiment, the data transfer corresponding to each DMA descriptor in the DMA descriptor queue is realized through the following steps.

[0086] In step S401, traverse the DMA work queue to the current DMA descriptor.

[0087] In this embodiment, there is at least one DMA descriptor corresponding to the data to be transmitted. Each DMA descriptor forms a DMA work queue, and the DMA descriptor corresponding to the current data to be transmitted is determined by traversing the DMA work queue.

[0088] In step S402, determine whether the third flag bit is the first value.

[0089] In this embodiment, when it is determined that the third flag bit of the current DMA descriptor is the first value 0, step S407 is executed; when it is determined that the third flag bit of the current DMA descriptor is not the first value 0 (i.e., 1, 2, or 3), step S403 is executed.

[0090] In step S403, determine whether the first flag bit and the second flag bit are the same.

[0091] In this embodiment, when the first flag bit and the second flag bit of the current DMA descriptor are the same, it indicates that the executable state corresponding to the current DMA descriptor is executable, and steps S405, S406, or S407 are continued to be executed; when the first flag bit and the second flag bit of the current DMA descriptor are different, it indicates that the executable state corresponding to the current DMA descriptor is not executable, and step S404 is continued to be executed.

[0092] In step S404, continue to traverse the DMA work queue.

[0093] In this embodiment, when the current DMA descriptor is not executable, the data corresponding to the current DMA descriptor cannot be transmitted. Then, continue to traverse the DMA work queue to determine other DMA descriptors, and transmit the data corresponding to other executable DMA descriptors to avoid the impact of the non - transmission of the data corresponding to the current DMA descriptor on other data transmissions, thereby improving the overall data transmission efficiency.

[0094] In step S405, when the value of the third flag bit is 1, reset or clear the value of the first flag bit of the current DMA descriptor.

[0095] In this embodiment, when the current DMA descriptor is triggered and the value of the third flag bit is 1, reset or clear the value of the first flag bit on the current DMA descriptor. Optionally, when the initial value of the first flag bit is 0, the corresponding reset operation is to modify the value of the first flag bit to 0.

[0096] In step S406, when the value of the third flag bit is 2, increment the value of the first flag bit of the current DMA descriptor by 1.

[0097] In this embodiment, after the data transfer corresponding to the current DMA descriptor is triggered and the value on the third flag bit is 2, the value on the first flag bit of the current DMA descriptor is incremented by 1, so as to trigger the data transfer corresponding to the next DMA descriptor after the data transfer corresponding to the current DMA descriptor is triggered.

[0098] Optionally, in this embodiment, after incrementing the first DMA descriptor by 1 each time, a corresponding table lookup operation is triggered to determine whether there are other executable DMA descriptors in the DMA descriptor queue through table lookup, so that after the data transfer corresponding to the current DMA descriptor is completed, the data transfer corresponding to the executable DMA descriptor can be processed in a timely manner, which can accelerate the processing process of the DMA descriptors in the DMA descriptor queue and improve the overall data transfer efficiency.

[0099] In step S407, an enabling judgment is made on the data transfer process status corresponding to the current DMA descriptor.

[0100] In this embodiment, when the value on the fourth flag bit of the current DMA descriptor is the first value 0 (at this time, the value on the third flag bit can be 0, 1, 2, or 3), it indicates that the data transfer process status corresponding to the current DMA descriptor is the enabling state, and this data transfer is enabled, and step S408 is continued to be executed; when the value on the fourth flag bit of the current DMA descriptor is not the first value 1, it indicates that the data transfer process status corresponding to the current DMA descriptor is the disabled state, then this data transfer is prohibited, and step S409 is continued to be executed.

[0101] In step S408, the DMA data transfer of the current DMA descriptor is executed.

[0102] In this embodiment, based on the DMA technology, the data corresponding to the current DMA descriptor of the source chip is transferred to the destination chip.

[0103] In step S409, the DMA data transfer is completed.

[0104] In this embodiment, after all the data corresponding to the current DMA descriptor is transferred from the source chip to the destination chip, or after the data corresponding to the current DMA descriptor is prohibited from being transferred, it is determined that the DMA data transfer is completed.

[0105] In step S410, an increment operation is performed on the first flag bit of the current DMA descriptor.

[0106] In this embodiment, when the value on the third flag bit of the current DMA descriptor is 3, the value on the first flag bit of the current DMA descriptor is incremented by 1, so as to trigger the data transfer corresponding to the next DMA descriptor after the data transfer corresponding to the current DMA descriptor is completed.

[0107] It should be understood that after the first flag bit of the current DMA descriptor in this embodiment changes, it can continue to be used as the DMA descriptor for other data, and the data transfer is only related to the execution trigger flag bit and other parameters in the DMA descriptor.

[0108] In step S411, it is judged whether to synchronize the process state of the data transfer of the current DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor.

[0109] In this embodiment, it is determined whether to synchronize the process state of the data transfer corresponding to the current DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor according to the value on the fifth flag bit. When the value on the fifth flag bit is the first value 0, the process state of the data transfer corresponding to the DMA descriptor is not synchronized to the destination side of the data transfer corresponding to the DMA descriptor, and step S413 is continued to be executed. When the fifth flag bit is not the first value 1, the process state of the data transfer corresponding to the DMA descriptor is synchronized to the destination side of the data transfer corresponding to the DMA descriptor, and step S412 is continued to be executed.

[0110] In step S412, the sixth flag bit of the current DMA descriptor is modified to synchronize the data transfer process state to the destination side.

[0111] In this embodiment, when the fifth flag bit represents that the process state of the data transfer corresponding to the DMA descriptor is synchronized to the destination side of the data transfer corresponding to the DMA descriptor, after the data transfer corresponding to the current DMA descriptor is completed, the sixth flag bit in the current DMA descriptor is modified and set.

[0112] Specifically, the corresponding increment operation is implemented by adding 1 to the sixth flag bit (dst_enable_addr), so as to synchronize the process state of the data transfer corresponding to the current DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor, thereby triggering the destination chip to perform a look-up table operation after receiving the data transmitted by the source chip, and acting as the source chip to transmit data to other chips, thereby realizing the data transfer from the source chip to the destination chip and from the destination chip to other chips.

[0113] Furthermore, in this embodiment, by setting the enable address on the destination chip side, after the destination chip receives the data corresponding to the current DMA descriptor transmitted by the source chip, the enable address is used as the start address to transmit the transmission data corresponding to the current DMA descriptor outward.

[0114] In step S413, the DMA work queue is traversed again.

[0115] In this embodiment, after the data transfer corresponding to the current DMA descriptor is completed, the DMA work sequence is traversed again to determine other DMA descriptors in the DMA descriptor queue by traversal, and then the data transfer corresponding to other DMA descriptors is executed, so that the data transfer corresponding to the DMA descriptors in the DMA descriptor queue can be processed in a timely manner, thereby accelerating the processing process of the DMA descriptors in the DMA descriptor queue and improving the overall data transfer efficiency.

[0116] After the technical solution of this embodiment traverses the DMA work queue to the current DMA descriptor, the executable state of the current DMA descriptor is determined by the first flag bit and the second flag bit in the DMA descriptor. After the current DMA descriptor is executable, the data transfer corresponding to the current DMA descriptor is enabled and judged by the fourth flag bit, and the data transfer corresponding to the current DMA descriptor is executed to realize the transfer of the data to be transferred from the source chip to the destination chip. At the same time, in this embodiment, after the data transfer corresponding to the DMA descriptor is completed, the process state of the data transfer corresponding to the DMA descriptor is synchronized to the destination side of the data transfer corresponding to the DMA descriptor by modifying the sixth flag bit, so that after the destination chip receives the data corresponding to the current DMA descriptor transmitted by the source chip, the set enable address is used as the start address to transmit the data corresponding to the current DMA descriptor outward, thereby realizing the data transfer from the source chip to the destination chip and from the destination chip to other chips, and improving the utilization efficiency of the data transfer corresponding to the DMA descriptor.

[0117] Figure 5 is another schematic diagram of the DMA descriptor of the embodiment of the present invention. As Figure 5 shown, on the basis of the basic parameters of the DMA descriptor in this embodiment (including the destination address (including the address of the destination chip), the source address (including the address of the source chip), the data type, the transfer shape (such as the transfer length, the transfer direction), etc.), the first flag bit to the seventh flag bit are newly added.

[0118] Optionally, as Figure 5As shown, the first flag bit (send_enable_addr) in this embodiment is used to represent the trigger parameter for the data transfer corresponding to the DMA descriptor, and the corresponding bit width is 32 bits. The second flag bit (send_enable_golden) is used to represent other data transfers on which the data transfer corresponding to the DMA descriptor depends, and the corresponding bit width is 16 bits. When determining the executable state of the DMA descriptor according to the first flag bit and the second flag bit, the corresponding preset condition is that the value on the first flag bit is greater than or equal to the value on the second flag bit (i.e., send_enable_addr≥send_enable_golden). That is, in this embodiment, the executable state of the corresponding DMA descriptor is determined by judging whether the value on the first flag bit is greater than or equal to the value on the second flag bit. When the value on the first flag bit is greater than or equal to the value on the second flag bit, the executable state of the corresponding DMA descriptor is determined to be executable. When the value on the first flag bit is less than the value on the second flag bit, the executable state of the corresponding DMA descriptor is determined to be non-executable. Thus, in this embodiment, through the setting method of greater than or equal to, the data transfers corresponding to different DMA descriptors can be processed in parallel, which is beneficial to further improving the data transfer efficiency.

[0119] Further, the third flag bit (send_enable_op) in this embodiment is used to represent the trigger mode of the data transfer corresponding to the DMA descriptor, the corresponding bit width is 1 bit, and the corresponding values are the first value 0 and the non-first value 1. When the third flag bit is 0, the data transfer of the current DMA descriptor is directly triggered. When the third flag bit is not 0 (i.e., 1), the data transfer corresponding to other DMA descriptors is triggered after the current DMA descriptor is triggered.

[0120] Further, the fourth flag bit (trans_op_type) in this embodiment is used to represent the process state of the data transfer corresponding to the DMA descriptor, the corresponding bit width is 1 bit, and the corresponding values are the first value 0 and the non-first value 1. When the fourth flag bit is the first value 0, the current DMA data transfer is enabled, that is, the data transfer corresponding to the current DMA descriptor is enabled. When the fourth flag bit is the non-first value 1, the current DMA data transfer is prohibited, that is, the data transfer corresponding to the current DMA descriptor is prohibited, and at the same time, it is regarded that the data transfer has been completed when the DMA data transfer is triggered.

[0121] Further, the fifth flag bit (dst_op_type) in this embodiment is used to indicate whether to synchronize the process status of the data transmission corresponding to the DMA descriptor to the destination side of the data transmission corresponding to the DMA descriptor. The corresponding bit width is 1 bit, and the corresponding values are the first value 0 and the non-first value 1. When the fifth flag bit is the first value 0, no operation is performed, that is, the process status of the data transmission corresponding to the DMA descriptor is not synchronized to the destination side of the data transmission corresponding to the DMA descriptor. When the fifth flag bit is the non-first value 1, it is used to indicate that the process status of the data transmission corresponding to the DMA descriptor is synchronized to the destination side of the data transmission corresponding to the DMA descriptor.

[0122] Further, the sixth flag bit (dst_enable_addr) in this embodiment is used to indicate other data transmissions on which the data transmission on the destination side depends, and the corresponding bit width is 32 bits. Specifically, after the data transmission corresponding to the current DMA descriptor is completed, in this embodiment, by incrementing the value on the sixth flag bit by 1, the process status of the data transmission corresponding to the DMA descriptor is synchronized to the destination side of the data transmission corresponding to the DMA descriptor, thereby triggering the destination chip to perform a look-up table operation after receiving the data transmitted by the source chip, and acting as the source chip to transmit data to other chips, thereby realizing the data transmission from the source chip to the destination chip and from the destination chip to other chips.

[0123] At the same time, after the sixth flag bit changes, in this embodiment, by setting the enable address of the destination chip, when the destination chip receives the data transmitted by the source chip, the enable address is used as the start address to transmit data outward, thereby realizing the data transmission from the source chip to the destination chip and then from the destination chip to other chips, enabling the data transmission to play a greater role and improving the data usage efficiency.

[0124] Furthermore, the DMA descriptor in this embodiment further includes a seventh flag bit (src_op_type), which is used to indicate whether to synchronize the process state of the data transmission corresponding to the DMA descriptor to the source side of the data transmission corresponding to the DMA descriptor. Specifically, the corresponding bit width of the seventh flag in this embodiment is 1 bit, and the corresponding values are the first value 0 and a non-first value 1. When the seventh flag bit is 0, the process state of the data transmission corresponding to the DMA descriptor is not synchronized to the source side of the data transmission corresponding to the DMA descriptor. At this time, the value on the first flag bit is reset or cleared, and the timing can be before / during / after the data transmission (that is, the reset or clearing of the first flag bit of the source chip can be before, during, or after the data transmission process of the current DMA descriptor). When the third flag bit is 1, the process state of the data transmission corresponding to the DMA descriptor is synchronized to the source side of the data transmission corresponding to the DMA descriptor. Specifically, after the data transmission corresponding to the current DMA descriptor is completed, the first flag bit is incremented (that is, the value on the send_enable_addr of the source chip is incremented by 1). And, after the increment operation is completed, a receive completion event is sent to the source chip to trigger the source chip to perform a look-up table operation, thereby triggering the triggering of the data transmission corresponding to other DMA descriptors.

[0125] It should be noted that the various flag bits in this embodiment are set to implement DMA data transmission, and the bit widths of the various flag bits and the representation contents corresponding to different values can be adjusted according to the actual usage scenario.

[0126] Figure 6 is a schematic diagram of the data transmission device according to an embodiment of the present invention. As Figure 6 shown, the data transmission device in this embodiment is applied to a DMA controller and includes a receiving unit 11, a judging unit 12, and a transmitting unit 13. Among them, the receiving unit 11 is used to receive the DMA descriptor sent by the processor, and the DMA descriptor includes an execution trigger flag bit. The judging unit 12 is used to determine the executable state of the DMA descriptor according to the execution trigger flag bit. The transmitting unit 13 is used to execute the data transmission corresponding to the DMA descriptor in response to the executable state indicating that the DMA descriptor is executable.

[0127] Optionally, the execution trigger flag bits in this embodiment include a first flag bit and a second flag bit. The first flag bit is used to represent the trigger parameter of the data transfer corresponding to the DMA descriptor, and the second flag bit is used to represent other data transfers on which the data transfer corresponding to the DMA descriptor depends. Further, the determination unit 12 is further configured to determine that the executable state of the DMA descriptor is executable in response to the values on the first flag bit and the second flag bit satisfying a preset condition; and determine that the executable state of the DMA descriptor is non-executable in response to the values on the first flag bit and the second flag bit not satisfying the preset condition. The transmission unit 13 is further configured to increment the value on the first flag bit to change the execution trigger flag bits in the DMA descriptor. Wherein, the preset condition is that the value on the first flag bit is equal to the value on the second flag bit, or the preset condition is that the value on the first flag bit is greater than or equal to the value on the second flag bit.

[0128] Optionally, the DMA descriptor in this embodiment further includes a third flag bit, and the third flag bit is used to represent the trigger mode of the data transfer corresponding to the DMA descriptor. Wherein, the trigger mode at least includes: triggering the data transfer corresponding to other DMA descriptors after the data transfer corresponding to the DMA descriptor is triggered, and triggering the data transfer corresponding to other DMA descriptors after the data transfer corresponding to the DMA descriptor is completed.

[0129] Optionally, the DMA descriptor in this embodiment further includes a fourth flag bit, and the fourth flag bit is used to represent the process state of the data transfer corresponding to the DMA descriptor.

[0130] Optionally, the DMA descriptor in this embodiment further includes a fifth flag bit, and the fifth flag bit is used to represent whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor.

[0131] Optionally, the DMA descriptor in this embodiment further includes a sixth flag bit, and the sixth flag bit is used to represent other data transfers on which the data transfer on the destination side depends.

[0132] Optionally, the DMA descriptor in this embodiment further includes a seventh flag bit, and the seventh flag bit is used to represent whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the source side of the data transfer corresponding to the DMA descriptor in this embodiment optionally.

[0133] Figure 7 is a schematic diagram of the electronic device according to the embodiment of the present invention. As Figure 7 shown, Figure 7The electronic device shown is a general address query device, which includes a general computer hardware structure, and at least includes a DMA controller 71 and a memory 72. A communication connection is established between the DMA controller 71 and the memory 72. The memory 72 is adapted to store instructions or programs executable by the DMA controller 71. The DMA controller 71 can be an independent microprocessor or a set of one or more microprocessors. Thus, by executing the instructions stored in the memory 72, the DMA controller 71 executes the method flow of the embodiment of the present invention as described above to implement the processing of data and the control of other devices.

[0134] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a device (equipment), or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be implemented as a computer program product on one or more computer-readable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0135] The present application is described with reference to the flowcharts of methods, devices (equipment), and computer program products according to the embodiments of the present application. It should be understood that each process in the flowchart can be implemented by computer program instructions.

[0136] These computer program instructions can be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, and the instruction device implements the process Figure 1 specified functions in one process or multiple processes.

[0137] These computer program instructions can also be provided to the processor of a general computer, a special computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices produce a device for implementing the Figure 1 specified functions in one process or multiple processes.

[0138] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, and the computer-readable program is used for a computer to execute the above-mentioned partial or all method embodiments.

[0139] That is, those skilled in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by specifying relevant hardware through a program. The program is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0140] The foregoing are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data transmission method, applied to a DMA controller, characterized in that, The method includes: Receiving at least one DMA descriptor sent by a processor, where the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to characterize the dependency relationship between at least one data transfer corresponding to the DMA descriptor; Determining the executable state of the DMA descriptor according to the execution trigger flag bit; In response to the executable state being executable, triggering the execution of the data transfer corresponding to the DMA descriptor and changing the execution trigger flag bit in the DMA descriptor.

2. The method according to claim 1, characterized in that, The execution trigger flag bit includes a first flag bit and a second flag bit. The first flag bit is used to characterize the trigger parameter of the data transfer corresponding to the DMA descriptor, and the second flag bit is used to characterize other data transfers on which the data transfer corresponding to the DMA descriptor depends; The determining the executable state of the DMA descriptor according to the execution trigger flag bit includes: In response to the values on the first flag bit and the second flag bit satisfying a preset condition, determining that the executable state of the DMA descriptor is executable; In response to the values on the first flag bit and the second flag bit not satisfying the preset condition, determining that the executable state of the DMA descriptor is non-executable; The changing the execution trigger flag bit in the DMA descriptor includes: incrementing the value on the first flag bit by 1.

3. The method according to claim 2, characterized in that, The preset condition is that the value on the first flag bit is equal to the value on the second flag bit, or the preset condition is that the value on the first flag bit is greater than or equal to the value on the second flag bit.

4. The method according to any one of claims 1 to 3, characterized in that, The DMA descriptor further includes a third flag bit, and the third flag bit is used to characterize the trigger mode of the data transfer corresponding to the DMA descriptor; Wherein, the trigger mode at least includes: triggering the data transfer corresponding to other DMA descriptors after the data transfer corresponding to the DMA descriptor is triggered, and triggering the data transfer corresponding to other DMA descriptors after the data transfer corresponding to the DMA descriptor is completed.

5. The method according to any one of claims 1-4, characterized in that, The DMA descriptor further includes a fourth flag bit, and the fourth flag bit is used to characterize the process state of the data transfer corresponding to the DMA descriptor.

6. The method according to claim 5, characterized in that The DMA descriptor further includes a fifth flag bit, and the fifth flag bit is used to characterize whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the destination side of the data transfer corresponding to the DMA descriptor.

7. The method according to claim 6, characterized in that, The DMA descriptor further includes a sixth flag bit, and the sixth flag bit is used to characterize other data transfers on which the data transfer on the destination side depends.

8. The method according to claim 5, wherein The DMA descriptor further includes a seventh flag bit, and the seventh flag bit is used to characterize whether to synchronize the process state of the data transfer corresponding to the DMA descriptor to the source side of the data transfer corresponding to the DMA descriptor.

9. A data transmission system, characterized in that, The system includes: A processor configured to generate and send at least one DMA descriptor; A DMA controller, configured to receive at least one DMA descriptor sent by a processor, where the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to characterize the dependency relationship between at least one data transfer corresponding to the DMA descriptor; determine the executable state of the DMA descriptor according to the execution trigger flag bit; in response to the executable state being executable, trigger the execution of the data transfer corresponding to the DMA descriptor, and change the execution trigger flag bit in the DMA descriptor; A source chip, configured to send the transfer data corresponding to the at least one DMA descriptor; A destination chip, configured to receive the transfer data sent by the source chip.

10. A data transmission device, applied to a DMA controller, characterized in that The apparatus includes: A receiving unit, configured to receive at least one DMA descriptor sent by a processor, where the DMA descriptor includes an execution trigger flag bit; wherein, the execution trigger flag bit is used to characterize the dependency relationship between at least one data transfer corresponding to the DMA descriptor; A judging unit, configured to determine the executable state of the DMA descriptor according to the execution trigger flag bit; A transmitting unit, configured to, in response to the executable state being executable, trigger the execution of the data transfer corresponding to the DMA descriptor, and change the execution trigger flag bit in the DMA descriptor.

11. An electronic device, comprising a memory and a DMA controller, characterized in that, The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the DMA controller to implement the method according to any one of claims 1-8.

12. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method steps according to any one of claims 1-8 are implemented.

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