DMA device, method of operating same, and electronic device including same

Abstract

A direct memory access (DMA) device includes: a controller; a read request issuing circuit that issues a read request based on the issuing capability and stores an issuing time of the read request; a read buffer temporarily storing read data corresponding to the read request and storing an arrival time of the read data; and a read buffer management circuit that, in order to count a current time, calculates an average bus delay based on an issue time of a read request when read data is received from the memory device, and outputs the read request to the accelerator when the read data stored in the read buffer is output to the accelerator. An average buffer dwell time is calculated based on the arrival time of the read data. The read request issuing circuit adjusts an issuing capability based on the average bus delay and the average buffer dwell time, and issues a read request based on the adjusted issuing capability.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0008282, filed with the Korean Intellectual Property Office on January 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the inventive concept relate to a direct memory access (DMA) device that reads data for operating an accelerator from a memory device. Background art

[0004] Direct memory access (DMA) refers to accessing a memory device from a peripheral device included in an electronic device without going through a central processing unit (CPU). That is, a DMA device can access the memory device according to DMA without going through the CPU. For example, a DMA device can read data for operating a device (e.g., an accelerator that performs operations such as security processing, image processing, and digital signal processing) from the memory device and provide the data to the device. Summary of the invention

[0005] Embodiments of the inventive concept provide a direct memory access (DMA) device with improved performance.

[0006] According to an embodiment of the inventive concept, a DMA device that reads data for operating an accelerator from a memory device includes: a controller configured to control the operation of the DMA device; a read - request issuing circuit configured to issue a read request based on an issue ability and store an issue time of the read request; a read buffer configured to temporarily store read data corresponding to the read request and store an arrival time of the read data; and a read - buffer management circuit configured to count a current time, calculate an average bus latency based on the issue time of the read request when read data is received from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator. The read - request issuing circuit is configured to adjust the issue ability based on the average bus latency and the average buffer residence time and issue a read request based on the adjusted issue ability.

[0007] According to an embodiment of the inventive concept, a method of operating a DMA device for reading data for accelerator operation from a memory device includes: issuing a read request by a read request issuing circuit based on an issuing ability, storing an issuing time of the read request in the read request issuing circuit, receiving read data corresponding to the read request by a read buffer, temporarily storing the read data corresponding to the read request in the read buffer, and storing an arrival time of the read data in the read buffer. The method further includes: calculating an average bus latency by a read buffer management circuit based on the issuing time of the read request, calculating an average buffer residence time by the read buffer management circuit based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator, adjusting the issuing ability by the read request issuing circuit based on the average bus latency and the average buffer residence time, and issuing a read request by the read request issuing circuit based on the adjusted issuing ability.

[0008] According to an embodiment of the inventive concept, an electronic device includes a memory device configured to store data, an accelerator configured to operate based on the data stored in the memory device, and a DMA device configured to read data for operation of the accelerator from the memory device. The DMA device includes: a controller configured to control the operation of the DMA device; a read request issuing circuit configured to issue a read request based on an issuing ability and store an issuing time of the read request; a read buffer configured to temporarily store read data corresponding to the read request and store an arrival time of the read data; and a read buffer management circuit configured to count a current time, calculate an average bus latency based on the issuing time of the read request when read data is received from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator. The read request issuing circuit is configured to adjust the issuing ability based on the average bus latency and the average buffer residence time, and issue a read request based on the adjusted issuing ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an electronic device according to an embodiment;

[0011] Figure 2 is a block diagram illustrating a direct memory access (DMA) device according to an embodiment;

[0012] Figure 3 is a diagram illustrating an operation according to a read request of a DMA device according to an embodiment;

[0013] Figure 4 is a diagram showing an operation of receiving read data according to a DMA device according to an embodiment;

[0014] Figure 5 is a diagram showing an operation of calculating an average bus latency by a DMA device according to an embodiment;

[0015] Figure 6 is a diagram showing an operation of calculating an average buffer residence time by a DMA device according to an embodiment;

[0016] Figure 7 is a diagram showing an operation of adjusting an issue ability by a DMA device according to an embodiment;

[0017] Figure 8 is a flowchart showing a method of operating a DMA device according to an embodiment;

[0018] Figure 9 is a flowchart showing a method of adjusting an issue ability by a DMA device based on an average bus latency according to an embodiment; and

[0019] Figure 10 is a flowchart showing a method of adjusting an issue ability by a DMA device based on an average buffer residence time according to an embodiment. DETAILED DESCRIPTION

[0020] Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Throughout the drawings, like reference numerals may refer to like elements.

[0021] Embodiments of the inventive concept may improve the performance of a direct memory access (DMA) device that provides data required for correct operation to a peripheral device.

[0022] It should be understood that terms such as "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an embodiment may be described as a "second" element in another embodiment.

[0023] It should be understood that descriptions of features or aspects within each embodiment are generally considered available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0024] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0025] Figure 1 is a block diagram showing an electronic device according to an embodiment.

[0026] Reference Figure 1 According to an embodiment, the electronic device 10 may include a central processing unit (CPU) 100, a memory device 200, an accelerator 300 (also referred to as an accelerator circuit), a direct memory access (DMA) device 400, and a system bus 500.

[0027] In an embodiment, the electronic device 10 may include any one of a smart phone, a tablet personal computer (PC), a smart television (TV), a mobile phone, a personal digital assistant (PDA), a laptop computer, a media player, a micro server, a global positioning system (GPS) device, an e-book terminal, a digital broadcast terminal, a navigation device, a self-service terminal, a Moving Picture Experts Group (MPEG) layer-3 (MP3) player, a digital camera, a home appliance, and a mobile or non-mobile computing device, but is not limited thereto. Additionally, the electronic device 10 may include a wearable device having data processing capabilities, such as, for example, a watch, glasses, a headband, or a ring, but is not limited thereto. According to an embodiment, the electronic device 10 may include all types of devices that operate based on an operating system (OS) by using a processor.

[0028] The CPU 100 may control all operations of the electronic device 10. That is, the CPU 100 may control the operations of all devices included in the electronic device 10. In an embodiment of the inventive concept, the CPU 100 may include an application processor (AP).

[0029] The memory device 200 may store data for the electronic device 10. The memory device 200 may include a memory controller 210 and a memory 220.

[0030] The memory controller 210 may control the operation of the memory 220. The memory controller 210 may cause the memory 220 to read data stored in the memory 220 in response to a read request received through the system bus 500. The memory controller 210 may control the memory 220 such that data is programmed into the memory 220 in response to a programming request received through the system bus 500. The memory controller 210 may control the memory 220 such that data stored in the memory 220 is deleted in response to an erase request received through the system bus 500.

[0031] The memory 220 may store data. In an embodiment, the memory 220 may include a dynamic random access memory (DRAM). However, embodiments of the inventive concept are not limited thereto. For example, in an embodiment, the memory 220 may include another type of volatile memory device, such as a static random access memory (SRAM), or may include a non-volatile memory device, such as a flash memory.

[0032] The accelerator 300 (also referred to as an accelerator circuit) can operate based on data stored in the memory device 200. The accelerator 300 can perform various types of operations based on the data stored in the memory device 200. For example, the accelerator 300 can perform various types of operations related to security processing, image processing, digital signal processing, etc. The accelerator 300 can read the data stored in the memory device 200 through the DMA device 400.

[0033] The DMA device 400 can read the data for operating the accelerator 300 from the memory device 200. The DMA device 400 can send a read request to the memory device 200 through the system bus 500. In this case, the read request sent by the DMA device 400 can be multiple outstanding requests for requesting to read multiple pieces of data at a time.

[0034] In an embodiment, the DMA device 400 can calculate the average bus latency and the average buffer residence time, adjust the issue ability based on the average bus latency and the average buffer residence time, and issue a read request based on the adjusted issue ability. In this case, the average bus latency can indicate the time taken from the time when the read request is sent through the system bus 500 to the time when the read data is received. The average buffer residence time can indicate the time taken from the time when the read data is received to the time when the received read data is output to the accelerator 300. The issue ability can indicate the number of pieces of data read from the memory device 200 through one read request. The following refers to Figure 2 Describe the more detailed structure and operation of the DMA device 400.

[0035] The system bus 500 can be used as a data transmission path between the CPU 100, the memory device 200, the accelerator 300, and the DMA device 400.

[0036] Figure 2 is a block diagram showing a DMA device according to an embodiment.

[0037] Refer to Figure 2 According to an embodiment, the DMA device 400 can include a controller 410 (also referred to as a controller circuit), a read request issue circuit 420, a read buffer 430 (also referred to as a read buffer circuit), and a read buffer management circuit 440. In addition, the DMA device 400 can also include an accelerator interface 450 and a bus interface 460.

[0038] The controller 410 may control all operations of the DMA device 400. In an embodiment, the controller 410 may set an initial value of the issue ability based on the size of the read buffer 430. For example, the controller 410 may set the initial value of the issue ability to read the same number of data items as the size of the read buffer 430 through a read request.

[0039] The read request issuing circuit 420 may issue a read request based on the issue ability and store the issue time of the read request. In addition, the read request issuing circuit 420 may adjust the issue ability based on the average bus latency and the average buffer residence time. The read request issuing circuit 420 may include a request table 421, an issue schedule table 422, and an issue ability calculation circuit 423.

[0040] The request table 421 may store the read requests issued by the read request issuing circuit 420. The request table 421 may store information about the issued read requests, such as, for example, the index of the read request.

[0041] The issue schedule table 422 may store the issue times corresponding to the read requests stored in the request table 421. When a read request is issued, the issue schedule table 422 may receive the current time from a timer 441 included in the read buffer management circuit 440. Next, the issue schedule table 422 may store the current time received from the timer 441 as the issue time of the read request. Thus, the issue schedule table 422 may store the time when the read request is issued as the issue time of the read request.

[0042] When a notification of the arrival of read data is received, the issue schedule table 422 may output the generation time of the read request corresponding to the received read data to the read buffer management circuit 440. The issue time of the read request output to the read buffer management circuit 440 may be used to calculate the average bus latency, as described below.

[0043] The issue ability calculation circuit 423 may adjust the issue ability based on the average bus latency and the average buffer residence time.

[0044] In an embodiment, as described below, the issue ability calculation circuit 423 may adjust the issue ability based on the average bus latency calculated by the average bus latency calculation circuit 442 of the read buffer management circuit 440. In this case, the issue ability calculation circuit 423 may adjust the issue ability in proportion to the average bus latency. For example, when the average bus latency increases, the issue ability calculation circuit 423 may increase the issue ability to prefetch data for the proper operation of the accelerator 300 from the memory device 200. On the contrary, when the average bus latency decreases, it is not necessary to prefetch data for the proper operation of the accelerator 300 from the memory device 200, and thus, the issue ability calculation circuit 423 may decrease the issue ability.

[0045] In an embodiment, the issue ability calculation circuit 423 may adjust the issue ability based on the average buffer residence time calculated by the average buffer residence time calculation circuit 443 of the read buffer management circuit 440 as described below. In this case, the average buffer residence time calculation circuit 443 may adjust the issue ability inversely proportional to the average buffer residence time. For example, when the average buffer residence time increases, the data processing of the accelerator 300 is delayed, and thus, the issue ability calculation circuit 423 may decrease the issue ability. On the contrary, when the average buffer residence time decreases, the data processing of the accelerator 300 is executed faster, and thus, the issue ability may be increased.

[0046] The issue ability calculation circuit 423 may adjust the issue ability based on the average bus latency and the average buffer residence time at each preset adjustment time interval. The adjustment time interval may indicate the time interval for adjusting the issue ability. The adjustment time interval may be experimentally set to a time interval at which the average bus latency and the average buffer residence time may change significantly because multiple read requests may be issued.

[0047] The read request issue circuit 420 may issue a read request based on the adjusted issue ability. When the adjusted issue ability is greater than the existing issue ability, the read request issue circuit 420 may increase the number of data items read from the memory device 200 by the read request. On the contrary, when the adjusted issue ability is decreased compared to the existing issue ability, the read request issue circuit 420 may decrease the number of data items read from the memory device 200 by the read request.

[0048] The read buffer 430 may temporarily store the read data corresponding to the read request and the arrival time of the stored read data. The read buffer 430 may include a read data buffer 431 and an arrival time table 432.

[0049] The read data buffer 431 can temporarily store the read data. The read data buffer 431 can temporarily store the read data received according to the read request issued by the read request issuing circuit 420.

[0050] The arrival time table 432 can store the arrival time corresponding to the read data stored in the read data buffer 431. When receiving the read data, the arrival time table 432 can receive the current time from the timer 441 included in the read buffer management circuit 440. Next, the arrival time table 432 can store the current time received from the timer 441 as the arrival time of the read data. Therefore, the arrival time table 432 can store the time when the read data is received as the arrival time of the read data.

[0051] In this case, the arrival time can correspond to multiple pieces of read data received according to the same read request. The read request sent by the DMA device 400 can request to read multiple pieces of data at a time, and thus, multiple pieces of read data received according to the same read request can be received simultaneously. Therefore, multiple pieces of read data received according to the same read request can have the same arrival time.

[0052] When the read data is output to the accelerator 300, the arrival time table 432 can output the arrival time of the read data corresponding to the output read data to the read buffer management circuit 440. The arrival time of the read data output to the read buffer management circuit 440 can be used to calculate the average buffer residence time, as described below.

[0053] When receiving the read data from the memory device 200, the read buffer 430 can send an arrival notification of the read data to the read request issuing circuit 420. The arrival notification of the read data can be a notification indicating that the read data corresponding to the read request is received from the memory device 200 through the system bus 500. When the read buffer 430 sends the arrival notification of the read data, the issue time table 422 can output the generation time of the read request corresponding to the read data to the read buffer management circuit 440, and the read buffer management circuit 440 can calculate the average bus delay.

[0054] The read buffer management circuit 440 can count the current time and calculate the average bus delay and the average buffer residence time. The read buffer management circuit 440 can include a timer 441 (also referred to as a timer circuit), an average bus delay calculation circuit 442, and an average buffer residence time calculation circuit 443.

[0055] Timer 441 can count the current time. Timer 441 can output the current time to the issue schedule 422, arrival schedule 432, average bus delay calculation circuit 442, and average buffer residence time calculation circuit 443. When Timer 441 outputs the current time to issue schedule 422, issue schedule 422 can store the current time as the issue time of the read request. When Timer 441 outputs the current time to arrival schedule 432, arrival schedule 432 can store the current time as the arrival time of the read data. When Timer 441 outputs the current time to average bus delay calculation circuit 442 and average buffer residence time calculation circuit 443, average bus delay calculation circuit 442 and average buffer residence time calculation circuit 443 can calculate the average bus delay and average buffer residence time respectively as described below.

[0056] When receiving the read data from memory device 200, average bus delay calculation circuit 442 can calculate the average bus delay based on the issue time of the read request. The average bus delay can indicate the time taken from the time when the read request is sent through system bus 500 to the time when the read data is received. The average buffer residence time can change depending on the state of system bus 500. For example, when the state of system bus 500 is a busy state, the average bus delay can increase. In contrast, when the state of system bus 500 is not a busy state, the average bus delay can decrease.

[0057] When the read data is received from memory device 200, average bus delay calculation circuit 442 can receive the issue time of the read request from issue schedule 422. In addition, average bus delay calculation circuit 442 can receive the current time from Timer 441 after receiving the issue time of the read request.

[0058] Average bus delay calculation circuit 442 can calculate the average bus delay based on the difference between the issue time of the read request and the current time. Average bus delay calculation circuit 442 can calculate the difference between the issue time of the read request and the current time as the bus delay. Next, average bus delay calculation circuit 442 can calculate the average bus delay by obtaining the moving average between the calculated bus delay and the previously calculated average bus delay.

[0059] When the read data stored in the read buffer 430 is output to the accelerator 300, the average buffer residence time calculation circuit 443 may calculate the average buffer residence time based on the arrival time of the read data. The average buffer residence time may indicate the time taken from the time when the read data is received to the time when the received read data is output to the accelerator 300. The average buffer residence time may vary depending on the throughput of the accelerator 300. For example, when the throughput of the accelerator 300 is high, the average buffer residence time may be reduced. On the contrary, when the throughput of the accelerator 300 is low, the average buffer residence time may be increased.

[0060] When the read data is received from the memory device 200, the average buffer residence time calculation circuit 443 may receive the arrival time of the read data from the arrival time table 432. In addition, the average buffer residence time calculation circuit 443 may receive the current time from the timer 441 after receiving the arrival time of the read data.

[0061] The average buffer residence time calculation circuit 443 may calculate the average buffer residence time based on the difference between the arrival time of the read data and the current time. The average buffer residence time calculation circuit 443 may calculate the difference between the arrival time of the read data and the current time as the buffer residence time. Next, the average buffer residence time calculation circuit 443 may calculate the average buffer residence time by obtaining a moving average between the calculated buffer residence time and the previously calculated average buffer residence time.

[0062] The accelerator interface 450 may connect the DMA device 400 to the accelerator 300. The accelerator interface 450 may manage requests and data transfers between the accelerator 300 and the DMA device 400.

[0063] The bus interface 460 may connect the DMA device 400 to the system bus 500. The bus interface 460 may manage requests and data transfers between the DMA device 400 and the system bus 500.

[0064] As described above, the DMA device 400 according to an embodiment of the inventive concept may calculate the average bus delay and the average buffer residence time, adjust the issue ability based on the average bus delay and the average buffer residence time, and issue a read request based on the adjusted issue ability. As a result, the DMA device 400 may provide improved performance depending on the throughput of the accelerator 300 and the state of the system bus 500.

[0065] Figure 3 is a diagram illustrating an operation of a read request according to a DMA device according to an embodiment.

[0066] Figure 3 FIG. 4 shows a read request issuing circuit 420, a read buffer management circuit 440, and a bus interface 460 included in a DMA device 400 according to an embodiment.

[0067] The read request issuing circuit 420 may include a request table 421 and an issue schedule table 422. In an embodiment according to Figure 3 the request table 421 may store issued read requests, and may store a first read request to a fourth read request. In an embodiment according to Figure 3 the issue schedule table 422 may store issue times corresponding to the read requests stored in the request table 421, and may store a first issue time to a fourth issue time. In this case, the first issue time to the fourth issue time may correspond to the first read request to the fourth read request, respectively.

[0068] In an embodiment according to Figure 3 when the read request issuing circuit 420 issues a fourth read request to the bus interface 460, the request table 421 may store the fourth read request. In addition, when the read request issuing circuit 420 issues the fourth read request, the issue schedule table 422 may receive the current time from the read buffer management circuit 440, and convert the received current time into a fourth issue time.

[0069] Figure 4 FIG. 5 is a diagram illustrating an operation of receiving read data according to a DMA device according to an embodiment.

[0070] Figure 4 FIG. 6 shows a read request issuing circuit 420, a read buffer 430, a read buffer management circuit 440, and a bus interface 460 included in a DMA device 400 according to an embodiment.

[0071] The read buffer 430 may include a read data buffer 431 and an arrival schedule table 432. In an embodiment according to Figure 4 the read data buffer 431 may temporarily store received read data, and may store a first read data to a fourth read data. In an embodiment according to Figure 4 the arrival schedule table 432 may store arrival times corresponding to the read data stored in the read data buffer 431, and may store a first arrival time. In this case, the first arrival time may correspond to the first read data to the fourth read data. In this case, the first read data to the fourth read data may be read data received according to the same read request.

[0072] In an embodiment according to Figure 4In an embodiment, when the read buffer 430 receives the first to fourth read data from the bus interface 460, the read data buffer 431 may store the first to fourth read data. In this case, when the read buffer 430 receives the first to fourth read data, the arrival schedule 432 may receive the current time from the read buffer management circuit 440 and store the received current time as the first arrival time. In addition, when the read buffer 430 receives the first to fourth read data, the read buffer 430 may send an arrival notification of the read data to the read request issuing circuit 420.

[0073] Figure 5 FIG. is a diagram illustrating an operation of calculating an average bus delay by a DMA device according to an embodiment.

[0074] Figure 5 FIG. shows a read request issuing circuit 420, a read buffer management circuit 440, and a bus interface 460 included in the DMA device 400 according to an embodiment. In this case, a request table 421 and an issue schedule 422 included in the read request issuing circuit 420 may be in the same state as shown in Figure 3 as shown.

[0075] When receiving an arrival notification of read data, the read request issuing circuit 420 may output a fourth issue time stored in the issue schedule 422 to the average bus delay calculation circuit 442 of the read buffer management circuit 440.

[0076] When receiving the fourth issue time from the read request issuing circuit 420, the average bus delay calculation circuit 442 may receive the current time from the timer 441. Next, the average bus delay calculation circuit 442 may calculate a difference between the fourth issue time and the current time as the bus delay. The average bus delay calculation circuit 442 may calculate the average bus delay by obtaining a moving average between the calculated bus delay and a previously calculated average bus delay.

[0077] Figure 6 FIG. is a diagram illustrating an operation of calculating an average buffer residence time by a DMA device according to an embodiment.

[0078] Figure 6 FIG. shows a read buffer 430, a read buffer management circuit 440, and an accelerator interface 450 included in the DMA device 400 according to an embodiment. In this case, a read data buffer 431 and an arrival schedule 432 included in the read buffer 430 may be in the same state as shown in Figure 4 as shown.

[0079] The read buffer 430 may output the temporarily stored first to fourth read data to the accelerator 300 via the accelerator interface 450 according to the request of the accelerator 300. After outputting the first to fourth read data to the accelerator interface 450, the read buffer 430 may output the first arrival time stored in the arrival schedule 432 to the average buffer residence time calculation circuit 443 of the read buffer management circuit 440.

[0080] When receiving the first arrival time from the read buffer 430, the average buffer residence time calculation circuit 443 may receive the current time from the timer 441. Next, the average buffer residence time calculation circuit 443 may calculate the difference between the first arrival time and the current time as the buffer residence time. The average buffer residence time calculation circuit 443 may calculate the average buffer residence time by obtaining the moving average between the calculated buffer residence time and the previously calculated average buffer residence time.

[0081] Figure 7 FIG. is a diagram illustrating an operation of adjusting the issuing ability by a DMA device according to an embodiment.

[0082] Figure 7 FIG. shows a read request issuing circuit 420 and a read buffer management circuit 440 included in the DMA device 400 according to an embodiment.

[0083] The issuing ability calculation circuit 423 of the read request issuing circuit 420 may adjust the issuing ability at each preset adjustment time interval. In this case, in order to adjust the issuing ability, the issuing ability calculation circuit 423 may receive the average bus delay T from the average bus delay calculation circuit 442 of the read buffer management circuit 440 at each adjustment time interval BL and receive the average buffer residence time T from the average buffer residence time calculation circuit 443 of the read buffer management circuit 440 BR .

[0084] The issuing ability calculation circuit 423 may adjust the issuing ability based on the received average bus delay T BL and the average buffer residence time T BR . For example, the issuing ability calculation circuit 423 may adjust the issuing ability to be proportional to the average bus delay T BL . In addition, the issuing ability calculation circuit 423 may adjust the issuing ability to be inversely proportional to the average buffer residence time T BR .

[0085] Figure 8 FIG. is a flowchart illustrating an operation method of a DMA device according to an embodiment.

[0086] Reference Figure 8 In operation S810, the DMA device 400 may issue a read request. The DMA device 400 may issue a read request through the read request issuing circuit 420 based on the issuing capability. The read request issued by the read request issuing circuit 420 may be sent to the memory device 200 through the bus interface 460 and the system bus 500. The read request issuing circuit 420 may store the issued read request in the request table 421.

[0087] In operation S820, the DMA device 400 may store the issuing time of the read request. For example, the DMA device 400 may store the issuing time corresponding to the read request issued in operation S810 in the issuing time table 422 of the read request issuing circuit 420. In this case, the issuing time table 422 may store the current time received from the timer 441 of the read buffer management circuit 440 as the issuing time of the read request.

[0088] In operation S830, the DMA device 400 may receive read data. For example, the read buffer 430 of the DMA device 400 may receive the read data corresponding to the read request issued in operation S810 through the bus interface 460. In this case, the number of read data may be multiple. By receiving the read data, the read buffer 430 may send a notification of the arrival of the read data to the read request issuing circuit 420.

[0089] In operation S840, the DMA device 400 may temporarily store the read data. For example, the DMA device 400 may temporarily store the read data received in operation S830 in the read data buffer 431 of the read buffer 430. In this case, the read data buffer 431 may store the read data until the read data is output to the accelerator 300.

[0090] In operation S850, the DMA device 400 may store the arrival time of the read data. For example, the DMA device 400 may store the arrival time corresponding to the read data received in operation S830 in the arrival time table 432 of the read buffer 430. In this case, the arrival time table 432 may store the current time received from the timer 441 of the read buffer management circuit 440 as the arrival time of the read data.

[0091] In operation S860, the DMA device 400 may calculate the average bus latency. For example, the DMA device 400 may calculate the average bus latency through the average bus latency calculation circuit 442 based on the issue time of the read request and the current time. By receiving the arrival notification of the read data, the average bus latency calculation circuit 442 may receive the issue time of the read request from the issue time table 422 of the read request issue circuit 420. In addition, the average bus latency calculation circuit 442 may receive the current time from the timer 441 of the read buffer management circuit 440. Next, the average bus latency calculation circuit 442 may calculate the average bus latency based on the difference between the received issue time of the read request and the current time.

[0092] In operation S870, the DMA device 400 may output the read data. For example, the read data buffer 431 of the DMA device 400 may output the received read data to the accelerator 300 through the accelerator interface 450 according to the request from the accelerator 300.

[0093] In operation S880, the DMA device 400 may calculate the average buffer residence time. For example, the DMA device 400 may calculate the average buffer residence time through the average buffer residence time calculation circuit 443 based on the arrival time of the read data and the current time. When the read data is output to the accelerator 300, the average buffer residence time calculation circuit 443 may receive the arrival time of the read data from the arrival time table 432 of the read buffer 430. In addition, the average buffer residence time calculation circuit 443 may receive the current time from the timer 441 of the read buffer management circuit 440. Next, the average buffer residence time calculation circuit 443 may calculate the average buffer residence time based on the difference between the received arrival time of the read data and the current time.

[0094] In operation S890, the DMA device 400 may adjust the issue ability. For example, the DMA device 400 may adjust the issue ability through the issue ability calculation circuit 423 based on the average bus latency and the average buffer residence time. In this case, the issue ability calculation circuit 423 may adjust the issue ability to be proportional to the average bus latency and may adjust the issue ability to be inversely proportional to the average buffer residence time.

[0095] After the issue ability is adjusted in operation S890, the process proceeds to operation S810, and the DMA device 400 may issue a read request based on the adjusted issue ability.

[0096] By using the operation method of the DMA device 400 according to the embodiments of the above inventive concept, the issue ability can be adjusted based on the average bus latency and the average buffer residence time, and by issuing read requests based on the adjusted issue ability, the DMA device 400 can provide improved performance depending on the throughput of the accelerator 300 and the state of the system bus 500.

[0097] Figure 9 is a flowchart showing a method by which a DMA device adjusts issue ability based on average bus latency according to an embodiment.

[0098] Refer to Figure 9 , in operation S910, the DMA device 400 may determine whether the average bus latency has increased. The DMA device 400 may determine whether the average bus latency has increased from a previously calculated value through the read request issuing circuit 420.

[0099] When it is determined that the average bus latency has increased, the process proceeds to operation S920, and the DMA device 400 may increase the issue ability. When the average bus latency increases, the DMA device 400 may increase the issue ability through the issue ability calculation circuit 423 to pre-read data used by the accelerator 300 from the memory device 200.

[0100] Next, in operation S930, the DMA device 400 may increase the number of data items read according to the read request. That is, by increasing the issue ability, when the read request is subsequently issued, the DMA device 400 may increase the number of data items read according to the read request.

[0101] When it is determined that the average bus latency has decreased, the process proceeds to operation S940, and the DMA device 400 may decrease the issue ability. When the average bus latency decreases, it is not necessary to pre-read data requested by the accelerator 300 from the memory device 200, and thus, the DMA device 400 may decrease the issue ability through the issue ability calculation circuit 423.

[0102] Next, in operation S950, the DMA device 400 may decrease the number of data items read according to the read request. That is, by decreasing the issue ability, when the read request is subsequently issued, the DMA device 400 may decrease the number of data items read according to the read request.

[0103] Figure 10 is a flowchart showing a method by which a DMA device adjusts issue ability based on average buffer residence time according to an embodiment.

[0104] Refer to Figure 10, in operation S1010, the DMA device 400 may determine whether the average buffer residence time increases. The DMA device 400 may determine whether the average buffer residence time increases from a previously calculated value by reading the request issuing circuit 420.

[0105] When it is determined that the average buffer residence time increases, the process proceeds to operation S1020, and the DMA device 400 may reduce the issuing ability. When the average buffer residence time increases, the data processing of the accelerator 300 is delayed, and thus, the DMA device 400 may reduce the issuing ability through the issuing ability calculation circuit 423.

[0106] Next, in operation S1030, the DMA device 400 may reduce the number of data items read according to the read request. Operations S1020 and S1030 may be the same as Figure 9 operations S940 and S950 respectively.

[0107] When it is determined that the average buffer residence time decreases, the process proceeds to operation S1040, and the DMA device 400 may increase the issuing ability. When the average buffer residence time decreases, the data processing of the accelerator 300 is executed quickly, and thus, the DMA device 400 may increase the issuing ability through the issuing ability calculation circuit 423.

[0108] Next, in operation S1050, the DMA device 400 may increase the number of data items read according to the read request. Operations S1040 and S1050 may be the same as Figure 9 operations S920 and S930 respectively.

[0109] As is conventional in the field of the inventive concept, embodiments are described and illustrated in the drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based fabrication techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, they may be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0110] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it is to be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A direct memory access (DMA) device for reading data for an accelerator from a memory device, the DMA device comprising: A controller configured to control operations of the DMA device; A read request issuing circuit configured to issue a read request based on an issuing capability and store an issuing time of the read request; A read buffer configured to temporarily store read data corresponding to the read request and store an arrival time of the read data; And A read buffer management circuit configured to count a current time, calculate an average bus latency based on the issuing time of the read request when the read data is received from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator, Wherein, the read request issuing circuit is configured to adjust the issuing capability based on the average bus latency and the average buffer residence time, and issue the read request based on the adjusted issuing capability.

2. The DMA device according to claim 1, wherein, The controller is configured to set an initial value of the issuing capability based on a size of the read buffer.

3. The DMA device according to claim 1, wherein The read request issuing circuit includes: A request table configured to store the issued read request; and An issuing time table configured to receive the current time from the read buffer management circuit when the read request is issued, and store the received current time as the issuing time of the read request.

4. The DMA device according to claim 1, wherein, The read buffer includes: A read data buffer configured to temporarily store the read data; and An arrival time table configured to receive the current time from the read buffer management circuit when the read data is received, and store the received current time as the arrival time of the read data.

5. The DMA device according to claim 4, wherein, The arrival time corresponds to multiple pieces of read data received according to the same read request.

6. The DMA device according to claim 1, wherein, When the read data is received from the memory device, the read buffer is configured to send an arrival notification of the read data to the read request issuing circuit, and When the arrival notification of the read data is received, the read request issuing circuit is configured to output the issuing time of the read request corresponding to the read data to the read buffer management circuit.

7. The DMA device according to claim 6, wherein, When the issuing time of the read request is received, the read buffer management circuit is configured to calculate the average bus latency based on a difference between the issuing time of the read request and the current time.

8. The DMA device according to claim 1, wherein, When the temporarily stored read data is output to the accelerator, the read buffer is configured to output the arrival time of the read data corresponding to the read data to the read buffer management circuit.

9. The DMA device according to claim 8, wherein, When receiving the arrival time of the read data, the read buffer management circuit is configured to calculate the average buffer residence time based on the difference between the arrival time of the read data and the current time.

10. The DMA device according to claim 1, wherein, The read request issuing circuit is configured to adjust the issuing ability based on the average bus delay and the average buffer residence time at each of a plurality of preset adjustment time intervals.

11. The DMA device according to claim 1, wherein, The read request issuing circuit is configured to adjust the issuing ability in proportion to the average bus delay and inversely proportional to the average buffer residence time.

12. The DMA device according to claim 11, wherein, The read request issuing circuit is configured to adjust the number of data items read from the memory device according to the read request in proportion to the issuing ability.

13. An operating method of a direct memory access (DMA) device for reading data for the operation of an accelerator from a memory device, the operating method comprising: Issuing a read request by a read request issuing circuit based on an issuing ability; Storing the issuing time of the read request in the read request issuing circuit; Receiving, by a read buffer, read data corresponding to the read request; Temporarily storing the read data corresponding to the read request in the read buffer; Storing the arrival time of the read data in the read buffer; Calculating, by a read buffer management circuit, an average bus delay based on the issuing time of the read request; Calculating, by the read buffer management circuit, an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator; Adjusting, by the read request issuing circuit, the issuing ability based on the average bus delay and the average buffer residence time; and Issuing, by the read request issuing circuit, the read request based on the adjusted issuing ability.

14. The operating method according to claim 13, further comprising: After receiving the read data, sending, by the read buffer, a notification of the arrival of the read data to the read request issuing circuit; and When receiving the arrival notification of the read data, outputting, by the read request issuing circuit, the issuing time of the read request corresponding to the read data to the read buffer management circuit.

15. The operating method according to claim 14, wherein, Calculating the average bus delay includes calculating the average bus delay based on the difference between the issuing time of the read request and the current time when the issuing time of the read request is received.

16. The operating method according to claim 13, further comprising: When the temporarily stored read data is output to the accelerator, outputting, by the read buffer, the arrival time of the read data corresponding to the read request to the read buffer management circuit.

17. The operating method according to claim 16, wherein, Calculating the average buffer residence time includes calculating the average buffer residence time based on the difference between the arrival time of the read data and the current time when the arrival time of the read data is received.

18. The operating method according to claim 13, wherein Adjusting the issuing ability includes: Adjusting the issuing ability in proportion to the average bus latency; and Adjusting the issuing ability inversely proportional to the average buffer residence time.

19. The operating method according to claim 18, wherein, Issuing the read request includes: issuing the read request by adjusting the number of data read from the memory device according to the read request in proportion to the issuing ability.

20. An electronic device, comprising: A memory device configured to store data; An accelerator configured to operate based on the data stored in the memory device; And A direct memory access (DMA) device configured to read data for the operation of the accelerator from the memory device, Wherein, the DMA device includes: A controller configured to control the operation of the DMA device; A read request issuing circuit configured to issue a read request based on an issuing ability and store the issuing time of the read request; A read buffer configured to temporarily store read data corresponding to the read request and store the arrival time of the read data; and A read buffer management circuit configured to count the current time, calculate an average bus latency based on the issuing time of the read request when the read data is received from the memory device, and calculate an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator, Wherein, the read request issuing circuit is configured to adjust the issuing ability based on the average bus latency and the average buffer residence time, and issue the read request based on the adjusted issuing ability.

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