Data transmission method, electronic device, storage medium and program product

Abstract

The invention discloses a data transmission method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, and the method comprises the steps that when data transmission needs to be carried out, an equipment end can receive first information corresponding to a direct memory access module sent by a processor based on a bus, and the first information is configuration information or operation information; determining the type of the first information, wherein the type of the first information is used for indicating that the first information is configuration information or operation information; storing the first information in a memory according to the type of the first information; and in response to a data transmission instruction sent by the processor, transmitting the data based on the first information in the memory. Therefore, the first information does not need to be stored in a memory of the processor, but is directly sent to the equipment end, and then the equipment end stores the first information, so that the problem that the memory utilization rate is relatively low due to the fact that the first information is stored in processing is avoided.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data transmission method, an electronic device, a storage medium, and a program product. Background Art

[0002] During data transmission, data can be transmitted through a Direct Memory Access (DMA) controller.

[0003] In related technologies, by applying for descriptors in the host-side memory, the transmission information of discrete memory blocks can be filled into multiple descriptors respectively, and the direct memory access controller sequentially performs data transmission according to the information in the descriptors until all descriptors are executed, that is, the data transmission is completed. However, in the above process, descriptors need to be applied for again each time, resulting in low memory utilization. Summary of the Invention

[0004] This application provides a data transmission method, an electronic device, a storage medium, and a program product to at least solve the problem of low memory utilization.

[0005] This application provides a data transmission method, including:

[0006] Receiving first information corresponding to a direct memory access module sent by a processor based on a bus, where the first information is configuration information or operation information, the configuration information is used to indicate an address for reading and writing data in the processor, and the operation information is used to indicate a data transmission strategy;

[0007] Storing the first information in a memory;

[0008] In response to a data transmission instruction sent by the processor, based on the first information in the memory, transmitting the data.

[0009] This application further provides a data transmission device, including: a receiving module, a storage module, and a transmission module, where

[0010] The receiving module is configured to receive first information corresponding to a direct memory access module sent by a processor based on a bus, where the first information is configuration information or operation information, the configuration information is used to indicate an address for reading and writing data in the processor, and the operation information is used to indicate a data transmission strategy;

[0011] The storage module is configured to store the first information in a memory;

[0012] The transmission module is configured to, in response to a data transmission instruction sent by the processor, based on the first information in the memory, transmit the data.

[0013] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above data transmission methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program implements the steps of any of the above data transmission methods when executed by a processor.

[0015] The present application also provides a computer program product including a computer program, which implements the steps of any of the above data transmission methods when executed by a processor.

[0016] Through the present application, when data transmission is required, a receiving processor receives first information corresponding to a direct memory access module sent based on a bus, where the first information is configuration information or operation information, the configuration information is used to indicate an address for reading and writing data in the processor, and the operation information is used to indicate a data transmission strategy; the first information is stored in the memory; in response to a data transmission instruction sent by the processor, based on the first information in the memory, the data is transmitted. In this way, through the above method, it is not necessary to store the first information in the host-side memory, but directly send it to the device side, thereby reducing the discrete memory on the host side, improving the utilization rate of the host-side memory, and preventing the first information from being discretely stored in the host-side memory, thus avoiding the problem of memory leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of the system architecture provided by the embodiment of the present application;

[0019] Figure 2 It is a schematic flowchart of the data transmission method provided by the embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of the data transmission process provided by the embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the process of a direct memory access controller processing operation information provided by the embodiment of the present application;

[0022] Figure 5 It is a schematic diagram of the structure of data transmission provided by the embodiment of the present application;

[0023] Figure 6 An interactive schematic diagram of data transmission provided by an embodiment of the present application;

[0024] Figure 7 A structural schematic diagram of a data transmission device provided by an embodiment of the present application;

[0025] Figure 8 A structural schematic diagram of an electronic device provided by the present application. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0027] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] First, the nouns involved in the present application are explained:

[0029] Direct Memory Access (DMA): Direct Memory Access is a technology that allows external devices (such as hard disks, graphics cards, network cards, etc.) to directly exchange data with the computer memory without going through the central processing unit. Through direct memory access, external devices can directly transfer data to the memory or read data from the memory, which can greatly reduce the burden on the central processing unit and improve the efficiency of data transmission and the overall performance of the computer.

[0030] Field-Programmable Gate Array (FPGA): A field-programmable gate array is an integrated circuit that can be programmed and configured at the hardware level. A field-programmable gate array allows users to define its internal logic structure through programming to meet specific functional requirements. This makes the field-programmable gate array extremely flexible and customizable in design and can adapt to different application scenarios.

[0031] Field-Programmable Gate Array Accelerator (FPGA Accelerator): A field-programmable gate array accelerator is a hardware accelerator that utilizes the flexibility and parallel processing capabilities of a field-programmable gate array to accelerate specific computing tasks. By transforming computationally intensive tasks (such as machine learning inference, big data processing, image recognition, etc.) into hardware-level parallel operations, the field-programmable gate array accelerator can significantly improve processing speed and efficiency. In this accelerator, the field-programmable gate array is programmed into a circuit that performs specific functions, without relying on the central processing unit to execute all calculations, thereby reducing latency, lowering power consumption, and enhancing overall performance.

[0032] In the related art, the transfer information of discrete memory blocks can be filled into multiple descriptors by applying for descriptors in the host-side memory, and the direct memory access controller sequentially performs data transfer according to the information in the descriptors until all descriptors are executed, that is, the data transfer is completed. However, in the above process, descriptors need to be re-applied for each transfer, resulting in low memory utilization.

[0033] To address the above problem, in the embodiments of the present application, when data transfer is required, the device side can receive the first information corresponding to the direct memory access module sent by the processor based on the bus. The first information is configuration information or operation information. The configuration information is used to indicate the addresses for reading and writing data in the processor, and the operation information is used to indicate the data transfer strategy; determine the type of the first information, where the type of the first information is used to indicate whether the first information is configuration information or operation information; store the first information in the memory according to the type of the first information; and in response to the data transfer instruction sent by the processor, transfer the data based on the first information in the memory. In this way, the first information does not need to be stored in the memory of the processor, but is directly sent to the device side, and the device side then stores the first information, thereby avoiding the problem of low memory utilization caused by storing the first information in the processor.

[0034] To enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the data transfer method depends, the specific application environment architecture or specific hardware architecture will be described herein. Refer to Figure 1 , Figure 1 is the schematic diagram of the system architecture provided by the embodiments of the present application. Please refer to Figure 1, including a host side 101 and a device side 102. The host side 101 can be the central processing unit of an electronic device, and the device side 102 can be a field programmable gate array accelerator. The electronic device can be any device with on-device computing capabilities, such as a server, a terminal device, etc. The device side 102 can include a direct memory access controller, which can be used to transfer data from the host side 101 to the device side 102 and can also be used to transfer data from the device side 102 to the host side 101.

[0036] The following uses specific embodiments to elaborate in detail on the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following will describe the embodiments of this application with reference to the accompanying drawings.

[0037] Figure 2 It is a schematic flowchart of the data transmission method provided by the embodiment of this application. As Figure 2 shown, the embodiment of this application provides a data transmission method, and a detailed description of the method is as follows:

[0038] S201. Receive the first information corresponding to the direct memory access module sent by the processor based on the bus.

[0039] The execution subject of the embodiment of this application can be an electronic device or the device side in the electronic device. The device side can be a field programmable gate array accelerator, a hard disk, a graphics processing unit, a camera, an audio processing card, etc. The execution subject can also be a data transmission device provided in the device side, and the data transmission device can be implemented through software or through a combination of software and hardware.

[0040] The processor can refer to the host side. Data transmission can refer to data transmission between the host side and the device side.

[0041] The bus can be used for communication between the processor and the device side. The bus can refer to a bus control module. For example, the bus can be a System Management Bus (SMBus) control module.

[0042] The direct memory access module can be used for data transmission between the device side and the host side.

[0043] The first information can be configuration information or operation information.

[0044] Configuration information can be used to indicate the addresses for reading and writing data in a processor. The configuration information can include at least one of the following: address information of the memory for data transfer corresponding to the direct memory access module, and / or the size of the memory for data transfer corresponding to the direct memory access module.

[0045] Among them, when initializing the processor, the processor needs to apply for multiple memory spaces in the memory. The memory spaces can be used to store data to be transferred or received data. The address information of the memory space is the address information of the memory for data transfer, and the size of the memory space is the size of the memory for data transfer.

[0046] For example, for any address for reading and writing, the configuration information can be: 0x0001, 128kb.

[0047] Operation information can be used to indicate the data transfer strategy.

[0048] The operation information can include at least one of the following: the first address, the second address for transfer by the direct memory access module, and / or the transfer length. The first address is used to indicate the source address of the transfer by the direct memory access module. The second address is used to indicate the destination address of the transfer by the direct memory access module. The operation information can be transmitted in the form of an array. Optionally, the operation information can include arrays corresponding to multiple first addresses, multiple second addresses, and / or multiple transfer lengths; it can also include arrays corresponding to the first address, the second address, and / or the transfer length.

[0049] Among them, the source address can refer to the starting position of data transfer, that is, the direct memory access module transfers the data at the source address. The source address can be the address of the device side or the host side; the destination address can refer to the end position of data transfer, that is, the position where the direct memory access module finally writes the data. The destination address can be the address of the device side or the host side; the transfer length can refer to the data size of the transferred data. According to the source address and the destination address, the data transfer direction can be determined, that is, whether the data transfer is from the host side to the device side or from the device side to the host side.

[0050] For example, the operation information can be: source address 0x1000, destination address 0x80000000, transfer length 4MB.

[0051] S202. Store the first information in the memory.

[0052] The memory can refer to the storage space of the device side. The memory can include a cache module and a storage module. The cache module can be used to store frequently accessed data, temporarily stored data, etc. The storage module can be used to persistently store data, that is, store data that needs to be stored long-term.

[0053] The first information can be stored in the following manner: The device side determines the type of the first information, where the type of the first information is used to indicate that the first information is configuration information or operation information; according to the type of the first information, when the type of the first information indicates that the first information is configuration information, the first information is stored in the storage module; when the type of the first information indicates that the first information is operation information, the first information is stored in the cache module.

[0054] That is, the device side stores the configuration information in the storage module and stores the operation information in the cache module.

[0055] Optionally, the first information can be a preset protocol type, and the preset protocol type can include a frame header field, a frame type field, a length field, a data field, a frame tail field, a check field, etc.

[0056] Among them, the frame header field can be used to identify the start of the frame (i.e., the first information); the frame type field can be used to represent the type of the first information. For example, assuming the first information is configuration information, the frame type field of the first information can be 0x0001, and assuming the first information is operation information, the frame type field of the first information can be 0x0002. In this way, by obtaining the frame type field of the first information, the type of the first information can be determined, that is, whether the first information is configuration information or operation information; the length field can be used to represent the length of the data field; the data field can be used to represent the actual data transmitted; the frame tail field can be used to identify the end of the frame (i.e., the first information); the check field can be the check value of the first information, which is used to ensure the correctness of data transmission.

[0057] Exemplarily, assuming that when the frame type field is 0x0001, it indicates that the first information is configuration information, and when the frame type field is 0x0002, it indicates that the first information is operation information, the first information can be as shown in Table 1. Please refer to Table 1.

[0058] Table 1

[0059]

[0060] Among them, according to the frame type of 0x0001 shown in Table 1, it can be determined that the first information is configuration information.

[0061] Exemplarily, assuming that when the frame type field is 0x0001, it indicates that the first information is configuration information, and when the frame type field is 0x0002, it indicates that the first information is operation information, the first information can be as shown in Table 2. Please refer to Table 2.

[0062] Table 2

[0063]

[0064] Among them, according to the frame type shown in Table 2 being 0x0002, it can be determined that the first information is operation information.

[0065] S203. In response to the data transmission instruction sent by the processor, based on the first information in the memory, the data is transmitted.

[0066] The data transmission instruction can be used to instruct the direct memory access module to transmit the data according to the first information in the memory.

[0067] For example, assume that according to the first information in the memory, it can be determined that the configuration information indicates that there are memory spaces 1, 2, and 3 in the processor, and the operation information indicates that the data in memory space 1 is transmitted to the memory at the device end. Then, the direct memory access module, in response to the data transmission instruction sent by the processor, transmits the data in memory space 1 to the memory at the device end.

[0068] Assume that according to the first information in the memory, it can be determined that the configuration information indicates that there are memory spaces 1, 2, and 3 in the processor, and the operation information indicates that the memory data at the device end is transmitted to memory space 2. Then, the direct memory access module, in response to the data transmission instruction sent by the processor, transmits the memory data at the device end to memory space 2.

[0069] In the embodiments of the present application, when the direct memory access module needs to transmit data, it can receive the first information corresponding to the direct memory access module sent by the processor based on the bus. The first information can be configuration information or operation information. The configuration information can be used to indicate the addresses for reading and writing data in the processor. The configuration information can include the address information of the memory for data transmission corresponding to the direct memory access module, and / or the size of the memory for data transmission corresponding to the direct memory access module. The operation information can be used to indicate the data transmission strategy. The operation information can include the first address, the second address, and / or the transmission length transmitted by the direct memory access module; store the first information in the memory. The memory can include a cache module and a storage module. Store the configuration information in the storage module and store the operation information in the cache module; in response to the data transmission instruction sent by the processor, based on the first information in the memory, transmit the data. In this way, through the above method, the first information for indicating data transmission can be stored in the memory without occupying the host-side memory space, thereby improving the utilization rate of the host-side memory. At the same time, the configuration information and the operation information are distinguished by the frame type field and stored separately, improving the utilization rate of the device-side storage space.

[0070] Based on any of the above embodiments, below, in combination with Figure 3, a detailed description of the data transmission process will be given.

[0071] Figure 3 This is a schematic diagram of the data transmission process provided by the embodiments of this application. Please refer to Figure 3 , the method may include:

[0072] S301. Obtain configuration information and operation information in the memory.

[0073] The memory includes a storage module and a cache module. That is, the device side can obtain configuration information from the storage module and operation information from the cache module.

[0074] S302. Determine whether the data can be transmitted based on the configuration information and the operation information.

[0075] The data can be determined whether it can be transmitted in the following way: Obtain the addresses indicated by the configuration information and the addresses indicated by the operation information, and determine whether the addresses indicated by the configuration information match the addresses indicated by the operation information. If they match, it is determined that the data can be transmitted; if they do not match, it is determined that the data cannot be transmitted.

[0076] Exemplarily, assume that for any data transmission, the addresses indicated by the configuration information are address A, address B, and address C, and the operation information indicates that the data in the device-side memory is transmitted to address B. Then it can be determined that the addresses indicated by the configuration information and the addresses indicated by the operation information match, that is, it is determined that the data can be transmitted; assume that for any data transmission, the addresses indicated by the configuration information are address A, address B, and address C, and the operation information indicates that the data in the device-side memory is transmitted to address D. Then it can be determined that the addresses indicated by the configuration information and the addresses indicated by the operation information do not match, that is, it is determined that the data cannot be transmitted.

[0077] Optionally, the matching may further include determining whether the size of the memory space matches. Assume that for any data transfer, the addresses indicated by the configuration information are address A, address B, and address C. Among them, the size of the memory space of address A is 10 KB, the size of the memory space of address B is 20 KB, and the size of the memory space of address C is 30 KB. The operation information indicates that 15 KB of data in the device-side memory is transferred to address B. Then, it can be determined that the size of the memory space indicated by the configuration information and the size of the memory space indicated by the operation information match, that is, it is determined that the data can be transferred. Assume that for any data transfer, the addresses indicated by the configuration information are address A, address B, and address C. Among them, the size of the memory space of address A is 10 KB, the size of the memory space of address B is 20 KB, and the size of the memory space of address C is 30 KB. The operation information indicates that 50 KB of data in the device-side memory is transferred to address B. Then, it can be determined that the size of the memory space indicated by the configuration information and the size of the memory space indicated by the operation information do not match, that is, it is determined that the data cannot be transferred.

[0078] S303. When the data can be transferred, determine the transfer type of the data based on the operation information.

[0079] The transfer type may include a read operation type and a write operation type.

[0080] The read operation type may refer to the device-side reading the data from the host-side. The data flow direction of the read operation type is from the host-side to the device-side. According to the source address and the destination address of the operation information, when the source address is the address of the host-side and the destination address is the address of the device-side, it can be determined that the current transfer type is the read operation type. That is, the direct memory access controller can obtain the data from the host-side source address and then transfer the data to the device-side destination address.

[0081] For example, the read operation may refer to the network interface card reading the data packet to be sent from the host-side memory; the graphics card reading the texture data from the host-side memory.

[0082] The write operation type may refer to the device-side writing the data to the host-side. The data flow direction of the write operation type is from the device-side to the host-side. According to the source address and the destination address of the operation information, when the source address is the address of the device-side and the destination address is the address of the host-side, it can be determined that the current transfer type is the write operation type. That is, the direct memory access controller can obtain the data from the device-side source address and then transfer the data to the host-side destination address.

[0083] For example, the write operation may refer to the disk controller writing the data read from the disk to the host-side memory; the device writing the collected data (such as sensor data) or the status information report to the host-side memory.

[0084] S304. Determine whether the transfer type is the read operation type.

[0085] If so, execute S305.

[0086] If not, execute S306.

[0087] S305. The controller based on the read operation processes the operation information and transfers the data.

[0088] The direct memory access controller may include a controller for read operations and a controller for write operations.

[0089] The controller for read operations further includes a read operation queue reading module, a read operation configuration information control module, and a read operation configuration receiving module.

[0090] The following uses a specific example to illustrate the process of the controller for read operations processing the operation information.

[0091] Figure 4 It is a schematic diagram of the process of the direct memory access controller provided by the embodiment of the present application for processing operation information. Please refer to Figure 4 , the device side may include a microcontroller and a field programmable gate array accelerator. Among them, the microcontroller may include a cache module and a low-speed interface, and the field programmable gate array accelerator may include a low-speed interface, a direct memory access controller, a read operation mover, and a write operation mover. The low-speed interface may include a read operation control interface and a write operation control interface. The direct memory access controller may include a read operation queue reading module, a read operation configuration information control module, a read operation configuration receiving module, a write operation queue reading module, a write operation configuration information control module, and a write operation configuration receiving module. The read operation mover may include a read operation control signal receiving module and a read operation status sending module. The write operation mover may include a write operation control signal receiving module and a write operation status sending module.

[0092] When it is determined that the transfer type is a read operation, the device side may transmit the operation information in the cache module to the read operation control interface of the field programmable gate array accelerator through the read operation control interface of the microcontroller. After the field programmable gate array accelerator receives the operation information, it transmits the operation information to the read operation queue reading module of the direct memory access controller. The read operation queue reading module transmits the operation information to the read operation configuration information control module in the queue order, and the read operation configuration information control module then transmits the operation information to the read operation control signal receiving module of the read operation mover. After the read operation control signal receiving module receives the operation information, it performs a read operation according to the operation information. After the read operation is completed, the status of the read operation is transmitted to the read operation configuration receiving module of the direct memory access controller through the read operation status sending module for status recording.

[0093] S306. The controller based on the write operation processes the operation information and transmits the data.

[0094] The controller for the write operation further includes a write operation queue reading module, a write operation configuration information control module, and a write operation configuration receiving module.

[0095] The following uses a specific example to illustrate the process of the controller for the write operation processing the operation information.

[0096] Please refer to Figure 4 , when it is determined that the transmission type is a write operation, the device side can transmit the operation information in the cache module to the write operation control interface of the field programmable gate array accelerator through the write operation control interface of the microcontroller. After receiving the operation information, the field programmable gate array accelerator transmits the operation information to the write operation queue reading module of the direct memory access controller. The write operation queue reading module transmits the operation information to the write operation configuration information control module in the queue order. The write operation configuration information control module then transmits the operation information to the write operation control signal receiving module of the write operation mover. After receiving the operation information, the write operation control signal receiving module performs a write operation according to the operation information. After the write operation is completed, the status of the write operation is transmitted to the write operation configuration receiving module of the direct memory access controller through the write operation status sending module for status recording.

[0097] In Figure 3 In the illustrated embodiment, when data needs to be transmitted, the device side can obtain the configuration information from the storage module and the operation information from the cache module. Based on the configuration information and the operation information, obtain the addresses indicated by the configuration information and the operation information, and determine whether the address indicated by the configuration information matches the address indicated by the operation information. If they match, it is determined that the data can be transmitted; if they do not match, it is determined that the data cannot be transmitted; when the data can be transmitted, based on the operation information, determine the transmission type of the data. The transmission type can include a read operation type and a write operation type. When the transmission type is the read operation type, the controller based on the read operation processes the operation information and transmits the data; when the transmission type is the write operation type, the controller based on the write operation processes the operation information and transmits the data. In this way, it is possible to pre-judge whether the addresses match according to the configuration information and the operation information, and only perform data transmission when they match, preventing the problem of data transmission failure caused by address mismatch; at the same time, when data is transmitted, the read operation type and the write operation type are separated according to the transmission type of the data, preventing the transmission conflict between the read operation and the write operation, thereby improving the efficiency of data transmission.

[0098] Based on any of the above embodiments, below, in combination with Figure 5, a detailed description of the data transmission structure is provided.

[0099] Figure 5 This is a schematic diagram of the data transmission structure provided by an embodiment of the present application. Please refer to Figure 5 , which includes a host side and a device side. Among them, the host side may include an application layer and a driver layer. The driver layer includes a bus and a transmission module. The device side may include a transmission interface, a microcontroller, a field-programmable gate array accelerator, and a memory. The microcontroller includes a receiving module, a storage module, a cache module, a control module, and a low-speed interface. The field-programmable gate array accelerator includes a low-speed interface, a direct memory access controller, and a direct memory access mover.

[0100] When data transmission is required, the driver layer of the host side can apply for multiple memory spaces in the transmission module, and send the configuration information and operation information of the memory spaces to the transmission interface of the device side through the bus, and transmit them to the receiving module through the transmission interface. The receiving module determines whether the received information is configuration information or operation information according to the type of the first information, and sends the configuration information to the storage module for storage, and sends the operation information to the cache module for storage. When data transmission is performed, the control module can send the configuration information in the storage module to the cache module. The cache module sends the configuration information and operation information to the low-speed interface of the field-programmable gate array accelerator through the low-speed interface, and transmits them to the direct memory access controller. The direct memory access controller sends the operation information to the direct memory access mover, so that the direct memory access mover performs corresponding data transmission operations on the memory.

[0101] Based on any of the above embodiments, below, in combination with Figure 6 , a detailed description of the data transmission structure is provided.

[0102] Figure 6 This is an interaction schematic diagram of the data transmission provided by an embodiment of the present application. Please refer to Figure 6 , including:

[0103] S1. The host side obtains configuration information and operation information.

[0104] S2. The host side sends the configuration information and operation information to the device side through the bus.

[0105] S3. The device side stores the configuration information in the storage module and stores the operation information in the cache module.

[0106] S4. The device side determines whether data can be transmitted according to the configuration information and operation information.

[0107] S5. The device side determines the operation type if it can perform the transmission.

[0108] S6. When the operation type at the device end is a read operation type, the operation information is processed based on the controller for the read operation, and the data is transmitted; when the operation type is a write operation type, the operation information is processed based on the controller for the write operation, and the data is transmitted.

[0109] Figure 7 is a schematic structural diagram of the data transmission device provided by the embodiment of the present application. As Figure 7 shown, the embodiment of the present application also provides a data transmission device 10, including: a receiving module 11, a storage module 12, and a transmission module 13, where

[0110] The receiving module 11 is configured to receive the first information corresponding to the direct memory access module sent by the processor based on the bus, where the first information is configuration information or operation information, the configuration information is used to indicate the address for reading and writing data in the processor, and the operation information is used to indicate the data transmission strategy;

[0111] The storage module 12 is configured to store the first information in the memory;

[0112] The transmission module 13 is configured to, in response to the data transmission instruction sent by the processor, transmit the data based on the first information in the memory.

[0113] The data transmission device provided by the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0114] In a possible design, the storage module 12 is specifically configured to

[0115] determine the type of the first information, where the type of the first information is used to indicate that the first information is the configuration information or the operation information;

[0116] Store the first information in the memory according to the type of the first information.

[0117] In a possible design, the storage module 12 is specifically configured to

[0118] When the type of the first information indicates that the first information is the configuration information, store the first information in the storage module;

[0119] When the type of the first information indicates that the first information is the operation information, store the first information in the cache module.

[0120] In a possible design, the receiving module 11 is specifically configured to, the configuration information includes at least one of the following:

[0121] Address information of the memory for data transfer corresponding to the direct memory access module;

[0122] Size of the memory for data transfer corresponding to the direct memory access module.

[0123] In a possible design, the receiving module 11 is specifically configured to, when the operation information is transmitted in the form of an array, the operation information includes at least one of the following:

[0124] The first address, which is used to indicate the source address of the transfer of the direct memory access module;

[0125] The second address, which is used to indicate the destination address of the transfer of the direct memory access module;

[0126] The transfer length of the data.

[0127] In a possible design, the transmission module 13 is specifically configured to,

[0128] Obtain the configuration information and the operation information in the memory;

[0129] Determine whether the data can be transferred based on the configuration information and the operation information;

[0130] When the data can be transferred, transfer the data based on the operation information.

[0131] In a possible design, the transmission module 13 is specifically configured to,

[0132] Determine the transfer type of the data based on the operation information, and the transfer type is a read operation type and a write operation type;

[0133] When the transfer type is a read operation type, process the operation information based on the controller of the read operation and transfer the data;

[0134] When the transfer type is a write operation type, process the operation information based on the controller of the write operation and transfer the data.

[0135] In a possible design, the transmission module 13 is specifically configured to,

[0136] Determine whether the address indicated by the configuration information matches the address indicated by the operation information;

[0137] If they match, determine that the data can be transferred;

[0138] If they do not match, determine that the data cannot be transferred.

[0139] The data transmission device provided in the embodiment of the present application can execute the technical solutions shown in the above method embodiments. The implementation principles and beneficial effects are similar, and will not be elaborated here.

[0140] Figure 8 It is a schematic structural diagram of the electronic device provided in the present application. As Figure 8 shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. Among them, the processor 501, the memory 502, and the communication component 503 are connected through a bus.

[0141] In the specific implementation process, at least one processor 501 executes the computer execution instructions stored in the memory 502, so that at least one processor 501 executes the above data transmission method embodiment.

[0142] For the specific implementation process of the processor 501, reference can be made to the above method embodiment. The implementation principles and technical effects are similar, and will not be elaborated here in this embodiment.

[0143] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly implemented by the execution of the hardware processor, or implemented by the combination of the hardware and software modules in the processor.

[0144] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0145] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the buses in the attached drawings of this application are not limited to only one bus or one type of bus.

[0146] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is set to execute the steps in any of the above-mentioned data transmission method embodiments when running.

[0147] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store computer programs.

[0148] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data transmission method embodiments.

[0149] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data transmission method embodiments.

[0150] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0151] The above has introduced in detail a data transmission method, an electronic device, a storage medium, and a program product provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data transmission method, characterized in that Comprising: A receiving processor based on first information corresponding to a direct memory access module sent via a bus, the first information being configuration information or operation information, the configuration information being used to indicate an address for reading and writing data in the processor, and the operation information being used to indicate a transmission policy for the data; Storing the first information in a memory; In response to a transmission instruction for the data sent by the processor, based on the first information in the memory, transmitting the data.

2. The method according to claim 1, characterized in that, Storing the first information in the memory includes: Determining a type of the first information, the type of the first information being used to indicate that the first information is the configuration information or the operation information; Storing the first information in the memory according to the type of the first information.

3. The method according to claim 2, wherein The memory includes a cache module and a storage module; storing the first information in the memory according to the type of the first information includes: When the type of the first information indicates that the first information is the configuration information, storing the first information in the storage module; When the type of the first information indicates that the first information is the operation information, storing the first information in the cache module.

4. The method according to any one of claims 1-3, characterized in that The configuration information includes at least one of the following: Address information of a memory for data transmission corresponding to the direct memory access module; Size of a memory for data transmission corresponding to the direct memory access module.

5. The method according to any one of claims 1 to 3, characterized in that, The operation information is transmitted in an array form, and the operation information includes at least one of the following: A first address, the first address being used to indicate a source address of transmission of the direct memory access module; A second address, the second address being used to indicate a destination address of transmission of the direct memory access module; A transmission length of the data.

6. The method according to any one of claims 1-3, characterized in that Transmitting the data based on the first information in the memory includes: Obtaining the configuration information and the operation information in the memory; Based on the configuration information and the operation information, determining whether the data can be transmitted; When the data can be transmitted, based on the operation information, transmitting the data.

7. The method according to claim 6, characterized in that, Transmitting the data based on the operation information includes: Based on the operation information, determining a transmission type of the data, the transmission type being a read operation type and a write operation type; When the transmission type is the read operation type, based on a controller for the read operation, processing the operation information and transmitting the data; When the transmission type is the write operation type, based on a controller for the write operation, processing the operation information and transmitting the data.

8. The method according to claim 7, wherein Based on the configuration information and the operation information, determining whether the data can be transmitted includes: Determining whether an address indicated by the configuration information matches an address indicated by the operation information; If they match, determining that the data can be transmitted; If they do not match, determining that the data cannot be transmitted.

9. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for implementing the steps of the data transmission method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the data transmission method according to any one of claims 1 to 8 when executed by a processor.

11. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the data transmission method according to any one of claims 1 to 8 when executed by a processor.

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