Design method for realizing bridging of intelligent bus GLINK interface of space carrier based on domestic FPGA (Field Programmable Gate Array)

Abstract

The invention provides a space carrier intelligent bus GLINK interface bridging design method based on a domestic FPGA, belongs to the field of FPGA application, can provide two paths of GLINK data transmission channels and two paths of GLINK data relay / forwarding channel high-speed interfaces at the same time by utilizing FPGA chip resources and combining with a GLINK chip, and can meet the requirements of switching networking and annular networking at the same time. An external memory access interface (EMIF) of a GLINK chip is configured for an international standardized PCIe protocol, and meanwhile, an FIFO synchronous read-write interface in a DMA mode is adopted, so that the communication safety is guaranteed, malicious attacks and accidental interruption are prevented, the communication reliability is improved, and the communication transmission rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of FPGA applications, and in particular to a design method for bridging the GLINK interface of a space vehicle intelligent bus based on domestic FPGAs. Background Art

[0002] With the maturity of FPGAs and the advancement of the domestic substitution plan, domestic FPGA chips are increasingly widely used in domestic communication equipment and national defense information equipment. The present invention is a design method for bridging the GLINK interface of a space vehicle intelligent bus based on domestic FPGAs, which can effectively improve the stability, security, and reliability of communication.

[0003] The PCI Express (PCle) bus has been widely used in processor systems. It is a high-speed serial computer expansion bus standard, belonging to the general serial interconnection bus, suitable for a wide range of applications in communication, data centers, enterprises, embedded, military, and other markets. It can be used as a bridge for peripheral device interconnection, chip-to-chip interfaces, and many other protocol standards. The PCIe bus solves the contradiction between the current people's growing needs for a better life and the bus standard with slow transmission, low bandwidth, and difficult improvement. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a design method for bridging the GLINK interface of a space vehicle intelligent bus based on domestic FPGAs, which improves the reliability of communication between the CPU and external devices and enhances the security of the communication transmission message format.

[0005] The technical solution of the present invention is as follows:

[0006] A design method for bridging the GLINK interface of a space vehicle intelligent bus based on domestic FPGAs utilizes the resources of the FPGA chip, combines with the GLINK chip, and simultaneously provides two GLINK data transmission channels and two high-speed interfaces for GLINK data relay / forwarding channels, while meeting the requirements of switched networking and ring networking.

[0007] Further,

[0008] The FPGA is configured through an independent EMIF interface protocol to achieve mode conversion, and data is sent in the NC mode and received in the NT mode.

[0009] Still further,

[0010] Downlink process:

[0011] The data flow is from the CPU to the FPGA through the PCIe protocol interface. The FPGA first configures the GLINK chip mode to the NC mode through the EMIF interface, and the data is sent to other devices through the GLINK protocol NC mode.

[0012] The CPU first configures GLINK to the NC receive mode and then waits for data transmission.

[0013] The AXI_M bus interface module of the external AXI interface is generated by the PCIe core to obtain the instruction packets and data packets sent from the CPU downwards. Among them, the instruction packets are analyzed by the instruction bar space transmission module and can be sent to the CPU through the AXI_S bus interface module for interaction between the FPGA and the CPU.

[0014] The MRD control module generates a memory read request packet according to the instructions sent from the CPU. The memory read request packet is sent to the CPU through the AXI_S bus interface module to complete the instruction interaction and the memory read request. At this time, the CPU starts to send data.

[0015] After the downlink control module obtains the data, it removes the frame header of the PCIe protocol to obtain the valid data, performs bit-width conversion to 16-bit width through the fifo core and simultaneously performs cross-clock domain conversion. The GLINK NC transmission module obtains the 16-bit width and sends it to other devices in the GLINK protocol mode.

[0016] Uplink process:

[0017] The data flow is that the data of other devices is received by the board FPGA through the GLINK protocol NT mode interface, and the FGPA is forwarded to the CPU through the PCIe protocol interface; the FPGA first configures the GLINK chip mode to the NT mode through the EMIF interface, and then the FPGA waits to receive the GLINK protocol data.

[0018] The CPU first configures GLINK to the NT receive mode and then waits for data reception.

[0019] The GLINK NT module obtains the data sent by other devices. The 16-bit width is converted to 128-bit width through the fifo ip core and simultaneously performs clock domain conversion. After the uplink control module obtains the valid data, it sends a request send instruction to the CPU through the bar space instruction module. At the same time, the MWR control module generates a memory write request. The memory write request packet is sent to the CPU through the AXI_S bus interface module; the instruction interaction and the memory write request are completed, and the data packet is sent to the CPU through the AXI_S bus interface module.

[0020] After the MWR control module finishes uploading each packet of data, it generates an MSI interrupt to tell the CPU that the uplink process has ended at this time.

[0021] The beneficial effects of the present invention are

[0022] First of all, the PCIe protocol supports full-duplex communication. The GLINK protocol belongs to simplex communication. The FPGA can be configured through an independent EMIF interface protocol to achieve mode conversion, send data in the NC mode, and receive data in the NT mode. It can realize the communication between the CPU and external devices and improve the simplicity of the overall system.

[0023] Secondly, the PCIe protocols are all mature international standard protocols, which improve the overall reliability and scalability of the system.

[0024] Thirdly, the bandwidth of PCIe is much larger than that of the GLINK protocol. The bandwidth of the overall architecture mainly depends on the transmission frequency of the GLINK protocol, which improves the controllability of the communication bandwidth.

[0025] At the same time, when it is not necessary to understand the transmitted data, encryption or decryption processing can be performed to improve the security of communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of the architecture of the present invention

[0027] Figure 2 is a schematic diagram of the working process of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0029] The present invention is directed to a mature domestic FPGA chip, which incorporates a new generation of space vehicle intelligent bus GLINK interface bridging circuit GLINK chip. The GLINK chip integrates 4-channel wide-rate high-speed serial interfaces, can adapt to the high-speed GLINK bus data transmission requirements of fiber optic channels and cable channels, and has characteristics such as a large rate range, low power consumption, compact area, and high reliability. FPGA belongs to a hardware reconfigurable chip structure with flexible design. Internally, a relative pipeline can be built according to the data packet steps, thereby achieving data parallelism and pipeline parallelism. It has a good balance among flexibility, performance, power consumption, and cost. It has the advantages of being easy to learn, flexible to expand, and low development cost. This patent utilizes the FPGA chip resources and combines with the GLINK chip to provide two GLINK data transmission channels and two GLINK data relay / forwarding channel high-speed interfaces simultaneously, which can adapt to the requirements of both switching networking and ring networking. For the internationally standardized PCIe protocol, the external memory access interface (EMIF) of the GLINK chip is configured, and at the same time, a FIFO synchronous read / write interface in the DMA mode is used to ensure the security of communication, prevent malicious attacks and accidental interruptions, improve the reliability of communication, and increase the transmission rate of communication.

[0030] The present invention realizes that the CPU is based on the Loongson platform, and the FGPA is based on the domestic architecture and the mainstream 28nm process SMQ7K325TFFG900IP. The architecture is as Figure 1 shown.

[0031] Through the AXI interface provided externally by the PCIe IP offered by the software VIVADO, the PCIe bus protocol architecture is encapsulated, simplifying PCIe development. The PCIe IP core is an IP designed to implement the PCIe protocol in FPGA products, and the IP Catalog tool in the VIVADO software completes the configuration and generation of the IP module. As Figure 2 shown:

[0032] 1) Downlink process

[0033] The data flow direction is that the CPU reaches the FPGA through the PCIe protocol interface. The FPGA first configures the GLINK chip mode to the NC mode through the EMIF interface, and the data is sent to other devices through the GLINK protocol NC mode.

[0034] The CPU first configures GLINK to the NC receiving mode and then waits for data transmission. The AXI_M bus interface module generates an external AXI interface by the PCIe core to obtain the instruction packets and data packets sent from the CPU. The instruction packets are analyzed by the instruction bar space transmission module and can be sent to the CPU through the AXI_S bus interface module to achieve the interaction between the FPGA and the CPU. The MRD control module generates a memory read request packet according to the instructions sent from the CPU. The memory read request packet is sent to the CPU through the AXI_S bus interface module to complete the instruction interaction and the memory read request. At this time, the CPU starts to send data. After the downstream control module obtains the data, the valid data is obtained after removing the PCIe protocol frame header. Since the AXI bus bit width generated by the IP core is 128-bit bandwidth and the clock is 125 MHz, the bit width is converted to 16-bit width through the fifo core and the clock domain crossing conversion is also performed at the same time. The GLINK NC transmission module obtains the 16-bit width and sends it to other devices in the GLINK protocol mode.

[0035] 2) Upstream process:

[0036] The data flow is that the data from other devices is received by the FPGA of this board card through the GLINK protocol NT mode interface, and the FGPA forwards it to the CPU through the PCIe protocol interface. The prerequisite is that the FPGA must first configure the GLINK chip mode to the NT mode through the EMIF interface, and then the FPGA waits to receive the GLINK protocol data.

[0037] The CPU first configures GLINK to the NT receiving mode and then waits for data reception. The GLINK NT module obtains the data sent from other devices. The 16-bit width is converted to 128-bit width through the fifo ip core and the clock domain conversion is also performed at the same time. After the upstream control module obtains the valid data, it sends a request to send an instruction to the CPU through the bar space instruction module. At the same time, the MWR control module generates a memory write request. The memory write request packet is sent to the CPU through the AXI_S bus interface module. After completing the instruction interaction and the memory write request, the data packet will be sent to the CPU through the AXI_S bus interface module. After the MWR control module completes the upload of each packet of data, it will generate an MSI interrupt to tell the CPU the end of the upstream process at this time.

[0038] The above is only the preferred embodiment of the present invention, which is only used to illustrate the technical solutions of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A design method for bridging the intelligent bus GLINK interface based on domestic FPGAs, characterized in that: Using the FPGA chip resources and combining with GLINK chips, it provides two GLINK data transmission channels and two high-speed interfaces for GLINK data relay / forwarding channels at the same time, and can meet the requirements of switching network and ring network at the same time.

2. The method according to claim 1, characterized in that: The FPGA is configured through an independent EMIF interface protocol to achieve mode conversion. Data is sent in the NC mode and received in the NT mode.

3. The method according to claim 2, characterized in that: Downlink process: The data flow is that the CPU reaches the FPGA through the PCIe protocol interface. The FPGA first configures the GLINK chip mode to the NC mode through the EMIF interface, and the data is sent to other devices through the GLINK protocol NC mode.

4. The method according to claim 3, characterized in that: The CPU first configures GLINK to the NC receive mode and then waits for data sending; The AXI_M bus interface module of the external AXI interface is generated by the PCIe core to obtain the instruction packet and data packet sent by the CPU in the downlink; The MRD control module generates a memory read request packet according to the instruction sent by the CPU. The memory read request packet is sent to the CPU through the AXI_S bus interface module to complete the instruction interaction and memory read request. At this time, the CPU starts to send data; After the downlink control module obtains the data, it removes the frame header of the PCIe protocol to obtain the valid data, performs bit width conversion to 16-bit width through the fifo core and performs cross-clock domain conversion at the same time. The GLINK NC transmission module obtains the 16-bit width and sends it to other devices in the GLINK protocol manner.

5. The method according to claim 4, characterized in that: The instruction packet is analyzed through the instruction bar space transmission module and can be sent to the CPU through the AXI_S bus interface module for interaction between the FPGA and the CPU.

6. The method according to claim 2, characterized in that: Uplink process: The data flow is that the data of other devices is received by the board FPGA through the GLINK protocol NT mode interface and forwarded to the CPU by the FGPA through the PCIe protocol interface; the FPGA first configures the GLINK chip mode to the NT mode through the EMIF interface, and then the FPGA waits to receive the GLINK protocol data.

7. The method according to claim 6, characterized in that: The CPU first configures GLINK to the NT receive mode and then waits for data receiving; The GLINK NT module obtains the data sent by other devices. The 16-bit width is converted to 128-bit width through the fifo ip core while performing the clock domain conversion. After the uplink control module obtains the valid data, it sends a request send instruction to the CPU through the bar space instruction module. At the same time, the MWR control module generates a memory write request, and the memory write request packet is sent to the CPU through the AXI_S bus interface module; after completing the instruction interaction and the memory write request, the data packet is sent to the CPU through the AXI_S bus interface module.

8. The method according to claim 7, wherein After the MWR control module completes the upload of each packet of data, it generates an MSI interrupt to tell the CPU the end of the uplink process at this time.

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