PCIe-based high-speed data transmission method, device and system

Abstract

The invention discloses a PCIe-based high-speed data transmission method, device and system, the PCIe-based high-speed data transmission method comprises the following steps: pre-determining a master device and a slave device comprising a standard mode and a high-speed mode in a PCIe link, when the master device is in the standard mode, sending a high-speed mode starting request to a data link layer of the master device by a transaction request layer of the master device; the data link layer of the master device judges whether a high-speed mode is supported according to the current link state, and if yes, the data link layer of the master device sends a high-speed mode starting request to the slave device; when the slave device receives the high-speed mode starting request, the data link layer of the slave device judges whether the high-speed mode is supported or not according to the current link state of the slave device, and if yes, the data link layer of the slave device returns a first agreement signal to the master device; the master device initiates a high speed mode in response to receiving the first agreement signal. According to the invention, high-speed data transmission can be carried out more reasonably and efficiently.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a high-speed data transmission method, device, and system based on PCIe. Background Art

[0002] In modern computer architectures, the efficiency and speed of data transmission have become key performance evaluation indicators. With the continuous evolution of computer technology, the demand for data transmission in various fields has shown an explosive growth trend, especially in the fields of big data processing and high-performance computing.

[0003] PCIe (Peripheral Component Interconnect Express), as a high-speed serial computer expansion bus standard, relies on SERDES (Serializer / Deserializer) technology to achieve high-speed serial data transmission. It converts parallel data into serial data for long-distance transmission and then restores it to parallel data for processing at the receiving end. With its excellent performance, PCIe occupies a core position in many computing devices such as personal computers, servers, and workstations, providing a stable and high-speed connection channel for various expansion cards and devices.

[0004] Currently, in the high-speed mode switching process of PCIe devices, relatively fixed configuration schemes or simple automatic detection mechanisms are generally adopted. For example, most devices rely on fixed options preset in the BIOS to determine whether to activate the high-speed mode, but they cannot flexibly switch modes according to dynamic factors such as the real-time transmission status of the link, the instantaneous processing efficiency of the device, and the data traffic. This is likely to cause the device to be unable to fully exploit the potential of the high-speed mode in specific scenarios, and may even have a negative impact on the stability and accuracy of data transmission due to forced entry into the high-speed mode in inappropriate situations.

[0005] The disclosure of the above background art content is only for assisting in understanding the inventive concept and technical solution of the present invention, and it does not necessarily belong to the prior art of this application, nor does it necessarily provide technical guidance; without clear evidence indicating that the above content was publicly available before the filing date of this application, the above background art should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0006] The object of the present invention is to provide a high-speed data transmission method, device, and system based on PCIe, which can perform high-speed data transmission more reasonably and efficiently.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: A high-speed data transmission method based on PCIe, comprising the following steps: The master device and the slave device in the PCIe link are pre-determined. The master device and the slave device include a standard mode and a high-speed mode, and the data transfer speed corresponding to the high-speed mode is greater than that corresponding to the standard mode. Among them, the standard mode is the PCIe standard mode. The high-speed mode generally refers to achieving a higher data transfer rate than the standard mode in certain specific application scenarios, PCIe links or devices by optimizing the hardware design, adopting more advanced signal processing technologies or increasing the link width. For example, in the standard mode of PCIe 5.0, the transfer rate of each channel is lower than 32 GT / s or is 32 GT / s, and in the corresponding high-speed mode, the transfer rate of each channel is not less than 32 GT / s; When the master device is in the standard mode, the transaction request layer of the master device sends a high-speed mode enabling request to its data link layer; In response to receiving the high-speed mode enabling request, the data link layer of the master device determines whether it supports the high-speed mode according to its current link state. If it supports, the data link layer of the master device sends the high-speed mode enabling request to the slave device; In response to receiving the high-speed mode enabling request, the data link layer of the slave device determines whether it supports the high-speed mode according to its current link state. If it supports, the data link layer of the slave device returns a first consent signal to the master device; In response to receiving the first consent signal, the master device activates the high-speed mode.

[0008] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the following steps are further included: When activating the high-speed mode, the master device sends a second consent signal to the slave device; In response to receiving the second consent signal, the slave device activates the high-speed mode.

[0009] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the master device / slave device activates the high-speed mode in the following manner: The transaction layer of the master device / slave device updates the transaction processing strategy to match the high-speed mode, including adjusting the data sending frequency and increasing the upper limit of the number of transaction requests; and / or, The data link layer of the master device / slave device reconfigures the data transfer parameters to match the high-speed mode, including: adjusting the traffic upper limit and error control parameters; and / or, The physical layer of the master device / slave device optimizes the signal reception parameters, including: equalization parameters, clock data recovery parameters and data sampling parameters.

[0010] Further, in continuation of any one of the above-described technical solutions or a combination of multiple technical solutions, when the data link layer of the master device sends the request to enable the high-speed mode to the slave device, the transaction layer of the master device waits for the slave device to return a first consent signal or a rejection signal. During the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device pauses the transmission of user service data.

[0011] Further, in continuation of any one of the above-described technical solutions or a combination of multiple technical solutions, when the master device and the slave device enter the high-speed mode, one of the master device and the slave device is the sender and the other is the receiver. And the sender transmits data to the receiver in the following manner: The transaction layer of the sender adds a Header and a CRC1 checksum to the target transmission data to obtain a first data, and sends the first data to the data link layer of the sender; The data link layer of the sender checks the first data, and after the check passes, first deletes the CRC1 checksum in the first data and then adds a CRC2 checksum to obtain a second data, and transmits the second data to the physical layer of the sender; The physical layer of the sender adds STAR and END flags to the second data to obtain a third data, and sends the third data to the receiver.

[0012] Further, in continuation of any one of the above-described technical solutions or a combination of multiple technical solutions, the receiver receives the target transmission data in the following manner: The physical layer of the receiver receives the third data and decodes the data, including removing the STAR and END flag bits in the third data to obtain a fourth data, and transmitting the fourth data to the data link layer of the receiver; The data link layer of the receiver receives the fourth data, and performs a CRC2 check on the fourth data. If the check passes, it deletes the CRC2 checksum in the fourth data to obtain a fifth data, and transmits the fifth data to the transaction layer of the receiver; The transaction layer of the receiver receives the fifth data, extracts the Payload in the fifth data, and obtains the transmitted data, and the data reception is completed.

[0013] Further, in continuation of any one of the above-described technical solutions or a combination of multiple technical solutions, after the data link layer of the sender deletes the CRC1 checksum in the first data, it adds a Sequence flag during the process of adding the CRC2 checksum to obtain the second data; The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR, and END flag in the third data.

[0014] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, after the transaction layer of the receiving end confirms the completion of data reception, it sends a data reception completion signal to the sending end; Upon receiving the data reception completion signal, the sending end checks whether there is other data to be sent. If not, the sending end switches to the standard mode and sends a request to end the high-speed mode to the receiving end. The receiving end switches to the standard mode upon receiving the request to end the high-speed mode.

[0015] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the following steps are further included: When the master device and the slave device are in the high-speed mode, the master device and the slave device monitor the link status of their respective data link layers in real time; When the link status of the data link layer of any one of the master device and the slave device meets one of the following conditions: The link traffic is lower than a preset traffic threshold; The number of data errors exceeds a preset first number threshold; The bit error rate is higher than a preset first bit error rate threshold; The data transmission quantity is lower than a preset first rate threshold; Then the device that meets one of the above conditions exits the high-speed mode to switch to the standard mode and sends a request to exit the high-speed mode to the other device.

[0016] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when the master device / slave device is in the high-speed mode, if one of the following conditions is met: The data transmission delay is greater than a preset first duration threshold; The data retransmission rate is greater than a preset first retransmission rate threshold; Then the master device / slave device exits the high-speed mode to switch to the standard mode.

[0017] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, determining the master device and the slave device in the PCIe link includes: Determining the upstream device in the PCIe link as the master device and the downstream device in the PCIe link as the slave device.

[0018] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the following method is used to evaluate whether the current link status supports the high-speed mode: Obtain the current link state, where the link state includes the current data transmission rate, the available space in the receiver buffer, the number of data transmission errors, and the bit error rate; If the current data transmission rate meets the requirement of not being higher than a preset second rate threshold, the available space in the receiver buffer is not lower than a preset storage space, the number of data transmission errors is lower than a preset second number threshold, and the bit error rate is not lower than a preset bit error rate threshold, it is determined that the current link state supports the high-speed mode; otherwise, it is determined that the current link state does not support the high-speed mode.

[0019] According to another aspect of the present invention, there is provided a data transmission device configured to perform data transmission based on the PCIe-based high-speed data transmission method according to any one of the above technical solutions or a combination of multiple technical solutions.

[0020] According to another aspect of the present invention, there is provided a computer system including the data transmission device according to any one of the above technical solutions or a combination of multiple technical solutions.

[0021] The beneficial effects brought by the technical solutions provided by the present invention are as follows: a. By pre-determining the master device and the slave device in the PCIe link, the link condition of the master device is usually more resource-intensive than that of the slave device. The master device always sends a high-speed mode opening request to the slave device, which can first evaluate the link state of the master device. If the link state of the master device does not support opening the high-speed mode, there is no need to send a high-speed mode opening request to the slave device, saving the link resources for data transmission and ensuring the stability of data transmission; b. By setting the transaction layer of the master device to wait for the first consent signal or the second rejection signal returned by the slave device, and setting the physical layer of the master device to maintain the standard mode to keep the current basic data transmission function, the data link layer of the master device pauses the sending of user service data, without adding additional resource pressure, and avoiding problems such as increased delay caused by data retransmission; c. During the process of the master device and the slave device opening the high-speed mode, the device layers cooperate to open the high-speed mode, optimize the parameters related to signal reception, can enhance the ability to restore high-speed signals, and are ready to receive signals / data transmitted at a higher frequency and a higher rate. It can improve the data transmission speed while ensuring the accuracy and reliability of data transmission. And in the high-speed mode, if problems occur, such as excessive data retransmission or excessive transmission delay, the master and slave devices will automatically exit the high-speed mode and switch to the standard mode, which can avoid data loss and ensure the stability of data transmission; d. The present invention proposes a communication frame format for high-speed mode with lower overhead. By adding a header and CRC1 check, verifying the data, adding a Sequence and then CRC2 check, and adding STAR and END, through hierarchically and specifically adding necessary identifiers and check information, it is possible to reduce unnecessary redundancy while ensuring data accuracy check and reliability check, reduce communication overhead, and improve data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 Flowchart of the high-speed data transmission method based on PCIe provided for an exemplary embodiment of the present invention; Figure 2 Schematic diagram of the principle of requesting to switch to high-speed mode provided for an exemplary embodiment of the present invention; Figure 3 Schematic diagram of the process of optimizing the communication frame format at the sending end provided for an exemplary embodiment of the present invention; Figure 4 Schematic diagram of the process of optimizing the communication frame format at the receiving end provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0026] Given that existing data transmission technologies have obvious limitations in monitoring link status in the decision-making process of high-speed mode switching, they usually only focus on whether the transmission rate reaches a certain preset threshold, but lack comprehensive consideration of key factors such as link traffic details, data error frequency, and bit error rate. Due to the omission of these important information, the arbitration rules of existing link status detection methods when evaluating the rationality of high-speed mode switching often have deviations, resulting in a lack of scientificity in the decision-making process of mode switching, and frequent unreasonable switching decisions.

[0027] In addition, during the initiation phase of the high-speed mode switching request, the existing technology is relatively extensive in terms of the mechanism for waiting for a reply between the initiator and the receiver and the control of the subsequent operation process. For example, after sending a request to start the high-speed mode, the current mechanism only adopts a simple retransmission request processing method when no reply is received for a long time. This not only leads to a serious waste of resources, but also significantly reduces the efficiency of the switching operation. At the same time, in the process of waiting for the receiver to reply, there is also a lack of effective solutions for how to ensure the stable operation of basic communication functions and maintain the continuity of important data transmission, which greatly affects the smoothness of the entire high-speed mode switching process.

[0028] In addition, the traditional PCIe communication frame format has the problem of excessively high proportion of redundant information such as verification and identification during data transmission. In high-speed mode, the bandwidth and transmission resources occupied by such redundant information cannot be underestimated, which directly leads to a reduction in the efficiency of effective data transmission and is difficult to meet the needs of high-speed and efficient data transmission. Especially in the face of massive data transmission, due to the technical limitations of PCIe itself, the SERDES rate cannot be maximized, resulting in the dilemma of insufficient utilization of the SERDES rate, which also greatly restricts the improvement of data transmission performance.

[0029] Based on the deficiencies of the above-mentioned prior art, the present application aims to provide a more flexible and intelligent high-speed data transmission method based on PCIe. By reasonably arbitrating according to the real-time state of the link (including various factors such as transmission rate, traffic conditions, data quality, etc.), it accurately determines whether it is suitable to switch to the high-speed mode, gives full play to the advantages of the high-speed mode, and at the same time ensures the stability of data transmission.

[0030] In one embodiment of the present invention, a high-speed data transmission method based on PCIe is provided, as Figure 1 shown. The method includes the following steps: Predetermine the master device and the slave device in the PCIe link. The master device and the slave device include a standard mode (i.e., the PCIe standard mode) and a high-speed mode (i.e., the PCIe high-speed mode), and the data transmission speed corresponding to the high-speed mode is greater than the data transmission speed corresponding to the standard mode; When the master device is in the standard mode, the transaction request layer of the master device sends a high-speed mode activation request to its data link layer; In response to receiving the high-speed mode activation request, the data link layer of the master device determines whether it supports the high-speed mode according to its current link state. If it supports, the data link layer of the master device sends the high-speed mode activation request to the slave device; In response to receiving the high-speed mode activation request, the data link layer of the slave device determines whether it supports the high-speed mode according to its current link state. If it supports, the data link layer of the slave device returns a first consent signal to the master device; In response to receiving the first consent signal, the master device activates the high-speed mode; While activating the high-speed mode, the master device sends a second consent signal to the slave device; In response to receiving the second consent signal, the slave device activates the high-speed mode.

[0031] If the data link layer of the master device determines that its current link state does not support the high-speed mode, the data link layer of the master device returns a first rejection signal to its transaction layer. In response to receiving the first rejection signal, the transaction layer of the master device maintains the standard mode. If the data link layer of the slave device determines that it does not support the high-speed mode according to its current link state, the slave device returns a second rejection signal to the master device. In response to receiving the second rejection signal, the master device maintains the standard mode.

[0032] Among them, the master device and the slave device in the PCIe link are predetermined, and preferably, the upstream device in the PCIe link is determined to be the master device, and the downstream device in the PCIe link is determined to be the slave device. In the PCIe link, the link status of the upstream device is usually more resource-intensive than the link status of the downstream device. Therefore, by determining that the upstream device in the PCIe link is the master device, and the master device always sends a high-speed mode start request to the slave device, the link status of the master device can be evaluated first. If the link status of the master device does not support the high-speed mode, it is not necessary to send a high-speed mode start request to the slave device, thereby saving link resources for data transmission and ensuring the stability of data transmission.

[0033] When the master device is in standard mode, the data link layer of the master device can send the high-speed mode start request to the slave device at a preset frequency, and the transaction layer of the master device waits for the slave device to return a first approval signal or a second rejection signal, and during the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device suspends the sending of user business data.

[0034] Based on the high-speed mode switching mechanism proposed in the present application, when the device is initialized, the main device self-checks whether it supports the high-speed mode and actively queries whether the sub-device supports the high-speed mode. When both parties support the high-speed mode and there is a high-speed transmission demand, the transaction layer of the main device initiates a request to start the high-speed mode. The request to start the high-speed mode can be sent through the PCIe interface. Specifically, the PCIe3.0 or higher version standard can be used for transmission. The request to start the high-speed mode includes information that clearly identifies the request to enter the high-speed transmission mode and a request packet of necessary parameters such as the device ID that initiated the request and the target device address (in some embodiments, it can also include information such as the amount of data, the required transmission speed, etc.), and is passed to the data link layer of the main device.

[0035] If one of the master device and the slave device does not support high-speed mode, the master device does not initiate a request to start high-speed mode. The high-speed transmission requirements of the master device and the slave device can be set in a variety of ways. For example, in response to receiving a high-speed mode start instruction input by a user, it is determined that there is a high-speed transmission requirement; for example, when the master device and the slave device are currently in standard mode and have a data transmission requirement, it is also determined that there is a high-speed transmission requirement, and the master device initiates a request to start high-speed mode at a preset frequency; for example, the master device and the slave device are currently in standard mode and have a data transmission requirement, and the amount of data to be transmitted is greater than a preset data amount threshold, it is also determined that there is a high-speed transmission requirement.

[0036] Monitoring and arbitration of the link state of the master device by its data link layer: The data link layer comprehensively collects link state information, including the current data transmission rate (which can be obtained by statistically analyzing the transceiver rate information of the physical layer feedback signal), link traffic conditions (by analyzing the amount of data already sent and to be sent); available space in the receiver buffer, the number of data transmission errors, and the bit error rate, etc. These metrics are used to comprehensively evaluate the data transmission quality. Then, pattern arbitration is performed according to the preset arbitration rules. For example, when the transmission rate is much lower than the high-speed rated rate, the link traffic is low, and the data quality is good, it is inclined to allow switching to the high-speed mode. Specifically, if the current data transmission rate meets the condition of not being higher than the preset second rate threshold (the second rate threshold is lower than the data transmission rate in the high-speed mode), the available space in the receiver buffer is not less than the preset storage space, the number of data transmission errors is lower than the preset second number threshold, and the bit error rate is not less than the preset bit error rate threshold, then it is determined that the current link state supports the high-speed mode; otherwise, it is determined that the current link state does not support the high-speed mode.

[0037] When the link state of the data link layer of the master device supports the high-speed mode, the data link layer of the master device sends the high-speed mode activation request to the physical layer of the master device, and the physical layer of the master device sends the high-speed mode activation request to the physical layer of the slave device.

[0038] During the process of the master device waiting for the slave device to feedback and respond to the high-speed mode activation request, the following operations are performed at each layer: The transaction layer of the master device waits for the slave device to return the first consent signal or the second rejection signal; The physical layer of the master device maintains the PCIe standard mode to ensure basic communication; The data link layer of the master device pauses user service data (regular data transmission), and special low-priority real-time data transmission is processed according to special mechanisms. Among them, low-special-priority real-time data is a special code pattern sequence, which is non-user service data for link control, status maintenance, etc. It needs to be processed in a timely manner to maintain the health and correct operation of the link, but the latency requirement is usually not high. The special mechanism can be DLLP (Data Link Layer Packet) for the confirmation of transaction layer data packets, traffic control credit update, power consumption management, etc.; the physical layer uses ordered sets (such as TS1, TS2, EDB, SKP, etc.) for link training, clock compensation, entry and exit of the electrical idle state, etc.

[0039] The switching high-speed transmission mechanism proposed in this application sets the above more refined optimization strategies for the waiting duration. The waiting, reply, and collaborative operation processes of the master device during the high-speed mode switching improve the switching efficiency, avoid resource waste and communication interruption problems caused by retransmission and other situations during the switching process, and ensure the normal maintenance of the basic communication function during the switching period and the continuity of important data transmission.

[0040] As Figure 2 shown, when the master device receives the first consent signal returned by the slave device (the ACK shown in Figure 2 i.e., the acknowledgment reply), each layer of it collaboratively enables the high-speed mode.

[0041] The transaction layer of the master device updates the transaction processing strategy to match the high-speed mode, including adjusting the data sending frequency, increasing the upper limit of the number of transaction requests, etc. The data link layer of the master device reconfigures the data transmission parameters to match the high-speed mode, including: adjusting the traffic upper limit, error control parameters, etc. The physical layer of the master device optimizes the signal reception parameters, including: equalization parameters, clock data recovery parameters, and data sampling parameters, etc. While each layer of the master device collaboratively enables the high-speed mode, it replies to the slave device with an ACK (signal to confirm the enabling of the high-speed mode) again to indicate that it also enables the high-speed mode and is ready for high-speed data transmission.

[0042] Based on the high-speed mode switching mechanism proposed in this application, the slave device performs the following operations for receiving high-speed transmission requests and arbitration and enabling the high-speed mode.

[0043] The physical layer of the slave device receives the request signal, restores and decodes it, and then passes it to its data link layer. The data link layer performs link state monitoring and arbitration from its own perspective (checking cache resources, evaluating processing capabilities, analyzing data quality, etc.). Specifically, the link state evaluation method is the same as that of the master device and will not be elaborated here.

[0044] As Figure 1 and Figure 2 shown, if the data link layer of the slave device meets the conditions for entering the high-speed transmission mode, it sends a second consent signal (another ACK signal) to the master device to indicate consent to switch to the high-speed mode. If there are problems with its own link state (such as insufficient cache, limited processing capabilities, poor link quality, etc.), it sends a rejection signal (such as the Nack shown in Figure 2 to negatively reply), terminates the process of switching to the high-speed mode, and maintains the standard mode communication.

[0045] After the slave device sends an ACK to the master device and receives the ACK replied by the initiator, each layer of the slave device adjusts to enable the high-speed mode. The transaction layer of the slave device prepares to receive large-scale data transactions and optimizes the response process. The data link layer of the slave device correspondingly adjusts traffic control, error control parameters, etc. The physical layer of the slave device optimizes signal reception parameters and formally enters the high-speed transmission mode to perform high-speed data transmission with the initiator. The way for each layer of the slave device to cooperate to enable the high-speed mode is the same as that of the master device and will not be elaborated here.

[0046] In an embodiment of the present invention, after the master device and the slave device enter the high-speed mode, the two parties optimize the communication frame format in the following manner to reduce redundant information, improve the transmission efficiency of valid data, and better adapt to the data transmission requirements in the high-speed mode while ensuring data accuracy and integrity.

[0047] When the master device and the slave device enter the high-speed mode, one of the master device and the slave device is the sender and the other is the receiver, and the sender transmits data to the receiver in the following manner.

[0048] The operation of the sender is as Figure 3 shown. The transaction layer of the sender adds a Header and a CRC1 check to the target transmission data to obtain the first data, and sends the first data to the data link layer of the sender. Adding the Header and CRC1 is used to identify basic information such as the data source and type, as well as preliminary data accuracy verification.

[0049] The data link layer of the sender checks the first data, and after the check passes, first deletes the CRC1 check in the first data, then adds a Sequence flag and a CRC2 check to obtain the second data, and transmits the second data to the physical layer of the sender. Among them, adding the Sequence flag is used to identify the order of the data, which is convenient for the receiver to reorganize the data. Adding the CRC2 check again can further ensure the integrity and accuracy of the data during link transmission.

[0050] The physical layer of the sender adds STAR (start identifier) and END (end identifier) flags to the second data to obtain the third data, and sends the third data to the receiver. By adding necessary identifiers and check information layer by layer and specifically, it is possible to reduce unnecessary redundancy and communication overhead while ensuring data accuracy verification and reliability verification.

[0051] The operation of the receiver is as Figure 4 shown. The receiver receives the target transmission data in the following manner: The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR, and END flag in the third data, removes the STAR and END flag bits in the third data after receiving and decoding the third data to obtain the fourth data, and transmits the fourth data to the data link layer of the receiving end; The data link layer of the receiving end receives the fourth data and performs CRC2 check on the fourth data. If the check passes, it deletes the CRC2 checksum and Sequence flag in the fourth data to obtain the fifth data, and transmits the fifth data to the transaction layer of the receiving end; The transaction layer of the receiving end receives the fifth data, extracts the Payload in the fifth data, obtains the transmitted data, and the data reception is completed.

[0052] When the master device and the slave device are in high-speed mode, the master device and the slave device monitor the link status of their own data link layers in real time. When the link status of the data link layer of any one of the master device and the slave device satisfies one of the following conditions, the mode exits the high-speed mode mechanism: (1) The link traffic is lower than the preset traffic threshold; (2) The number of data errors exceeds the preset first number threshold; (3) The bit error rate is higher than the preset first bit error rate threshold; (4) The data transmission quantity is lower than the preset first rate threshold; (5) The data transmission delay is greater than the preset first duration threshold; (6) The data retransmission rate is greater than the preset first retransmission rate threshold.

[0053] The device that meets one of the above conditions exits the high-speed mode to switch to the standard mode and sends a request to exit the high-speed mode to the other device.

[0054] After the transaction layer of the receiving end confirms that the data reception is completed, it sends a data reception completion signal to the sending end; the sending end responds to the received data reception completion signal and self-checks whether there is other data to be sent. If not, the sending end switches to the standard mode and sends a request to end the high-speed mode to the receiving end. The receiving end switches to the standard mode in response to the received request to end the high-speed mode, and ends the high-speed mode.

[0055] Compared with the existing technology, the beneficial effects of the present technical solution include: (1) Reducing latency and overhead: When a request enters the high-speed mode, the present invention does not require a complex link state monitoring and arbitration process for both the receiving and sending devices simultaneously. Instead, the master device always sends a request to enable the high-speed mode to the slave device. This can first evaluate the link state of the master device. If the link state of the master device does not support enabling the high-speed mode, there is no need to send a request to enable the high-speed mode to the slave device, which not only reduces latency but also decreases overhead, improves the efficiency of data transmission, and ensures the stability of data transmission. (2) Improving transmission accuracy and reliability: During the process of enabling the high-speed mode for the master and slave devices, their respective layers cooperate to enable the high-speed mode, optimize the parameters related to signal reception, improve the ability to restore high-speed signals, and prepare to receive electrical signals transmitted at a higher frequency and rate. This not only increases the data transmission speed but also improves the transmission accuracy and reliability of the data. (3) Automatically exiting the high-speed mode: During high-speed transmission, if problems occur, such as excessive data retransmission or excessive transmission delay, the master and slave devices will automatically exit the high-speed mode and switch to the standard mode, which can avoid data loss and ensure the stability of data transmission. (4) Optimizing the communication frame format: This technical solution proposes a communication frame format for the high-speed mode with less overhead. By adding a header and CRC1 check, verifying the data, adding a Sequence, then adding CRC2 check, and adding STAR and END, the communication frame format is optimized, improving the efficiency of data transmission. (5) Wide range of applications: This technical solution mainly relates to the "computer hardware technology field", "data transmission technology field", and "high-speed interface technology field", and can be widely applied to devices such as personal computers, servers, and workstations to connect various expansion cards and devices, with broad application prospects.

[0056] In an embodiment of the present invention, a data transmission device is provided, and the data transmission device is configured to perform data transmission based on the PCIe-based high-speed data transmission method described in any of the above embodiments.

[0057] In an embodiment of the present invention, a computer system is provided, including the data transmission device described in the above embodiment.

[0058] It should be noted that the inventive concepts of the data transmission device and computer system embodiments provided by the present invention are the same as those of the above PCIe-based high-speed data transmission method embodiments. By way of introduction, all the contents of the PCIe-based high-speed data transmission method embodiments are incorporated into the data transmission device and computer system embodiments.

[0059] Due to the advanced nature of this technical solution, it can be widely used in the fields of computer systems, data transmission and high-performance computing. First, this technical solution proposes a high-speed mode communication frame format with lower overhead, which can greatly improve the efficiency and speed of data transmission, especially in the fields of big data processing and high-performance computing, which will greatly improve the performance and response speed of the system. Secondly, when requesting to enter the high-speed mode, this technical solution determines whether it has the conditions to enter the high-speed transmission mode at one time through the master device and the slave device, which can reduce the overhead in the link state monitoring and arbitration process and improve the response speed of the system. In addition, during the data transmission process in the high-speed mode, this technical solution can effectively solve problems such as signal distortion and interference by adjusting flow control parameters, error control parameters, etc., which will improve the transmission accuracy and reliability of data. Therefore, this technical solution has great advantages and broad application prospects in high-speed data transmission, and will meet the growing demand for data transmission efficiency and speed in modern computer systems.

[0060] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0061] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A high-speed data transmission method based on PCIe, characterized in that, Including the following steps: Predetermine the master device and the slave device in the PCIe link. The master device and the slave device include a standard mode and a high-speed mode, and the data transfer speed corresponding to the high-speed mode is greater than the data transfer speed corresponding to the standard mode; When the master device is in the standard mode, the transaction request layer of the master device sends a high-speed mode enabling request to its data link layer; In response to receiving the high-speed mode enabling request, the data link layer of the master device determines whether it supports the high-speed mode according to its current link state. If it supports, the data link layer of the master device sends the high-speed mode enabling request to the slave device; In response to receiving the high-speed mode enabling request, the data link layer of the slave device determines whether it supports the high-speed mode according to its own current link state. If it supports, the data link layer of the slave device returns a first consent signal to the master device; In response to receiving the first consent signal, the master device activates the high-speed mode.

2. The high-speed data transmission method based on PCIe according to claim 1, wherein It also includes the following steps: When activating the high-speed mode, the master device sends a second consent signal to the slave device; In response to receiving the second consent signal, the slave device activates the high-speed mode.

3. The high-speed data transmission method based on PCIe according to claim 2, wherein The master device / slave device activates the high-speed mode in the following manner: The transaction layer of the master device / slave device updates the transaction processing policy to match the high-speed mode, including adjusting the data sending frequency and increasing the upper limit of the number of transaction requests; And / or, The data link layer of the master device / slave device reconfigures the data transfer parameters to match the high-speed mode, including: adjusting the traffic upper limit and error control parameters; and / or, The physical layer of the master device / slave device optimizes the signal reception parameters, including: equalization parameters, clock data recovery parameters, and data sampling parameters.

4. The high-speed data transmission method based on PCIe according to claim 1, characterized in that, When the data link layer of the master device sends the high-speed mode enabling request to the slave device, the transaction layer of the master device waits for the slave device to return a first consent signal or a rejection signal. During the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device suspends the sending of user service data.

5. The high-speed data transmission method based on PCIe according to claim 1, wherein When the master device and the slave device enter the high-speed mode, one of the master device and the slave device is the sending end and the other is the receiving end. And the sending end transfers data to the receiving end in the following manner: The transaction layer of the sending end adds a Header and a CRC1 check to the target transfer data to obtain a first data, and sends the first data to the data link layer of the sending end; The data link layer of the sending end checks the first data, and after the check passes, first deletes the CRC1 check in the first data and then adds a CRC2 check to obtain a second data, and transfers the second data to the physical layer of the sending end; The physical layer of the sending end adds STAR and END flags to the second data to obtain a third data, and sends the third data to the receiving end.

6. The high-speed data transmission method based on PCIe according to claim 5, wherein The receiving end receives the target transfer data in the following manner: The physical layer of the receiving end receives the third data and decodes the data, including removing the STAR and END flag bits in the third data to obtain the fourth data, and transmitting the fourth data to the data link layer of the receiving end; The data link layer of the receiving end receives the fourth data, and performs CRC2 check on the fourth data. If the check passes, the CRC2 check in the fourth data is removed to obtain the fifth data, and the fifth data is transmitted to the transaction layer of the receiving end; The transaction layer of the receiving end receives the fifth data, extracts the Payload in the fifth data, obtains the transmitted data, and the data reception is completed.

7. The high-speed data transmission method based on PCIe according to claim 6, characterized in that, After removing the CRC1 check in the first data, the data link layer of the sending end adds the Sequence flag while adding the CRC2 check to obtain the second data; The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR and END flag in the third data.

8. The high-speed data transmission method based on PCIe according to claim 5, wherein After the transaction layer of the receiving end confirms that the data reception is completed, it sends a data reception completion signal to the sending end; In response to receiving the data reception completion signal, the sending end checks whether there is other data to be sent. If not, the sending end switches to the standard mode and sends a request to end the high-speed mode to the receiving end. In response to receiving the request to end the high-speed mode, the receiving end switches to the standard mode.

9. The high-speed data transmission method based on PCIe according to claim 1, wherein It also includes the following steps: When the master device and the slave device are in the high-speed mode, the master device and the slave device monitor the link status of their own data link layers in real time; When the link status of the data link layer of any one of the master device and the slave device satisfies one of the following conditions: The link traffic is lower than the preset traffic threshold; The number of data errors exceeds the preset first number threshold; The bit error rate is higher than the preset first bit error rate threshold; The data transmission quantity is lower than the preset first rate threshold; Then the device that satisfies one of the above conditions exits the high-speed mode to switch to the standard mode and sends a request to exit the high-speed mode to the other device.

10. The high-speed data transmission method based on PCIe according to claim 1, characterized in that When the master device / slave device is in the high-speed mode, if one of the following conditions is satisfied: The data transmission delay is greater than the preset first duration threshold; The data retransmission rate is greater than the preset first retransmission rate threshold; Then the master device / slave device exits the high-speed mode to switch to the standard mode.

11. The high-speed data transmission method based on PCIe according to claim 1, wherein, Determine the master device and the slave device in the PCIe link in advance, including: Determine the upstream device in the PCIe link as the master device, and determine the downstream device in the PCIe link as the slave device.

12. The high-speed data transmission method based on PCIe according to claim 1, wherein Evaluate whether the current link status supports the high-speed mode through the following method: Obtain the current link status, and the link status includes the current data transmission rate, the available space in the receiving end buffer, the number of data transmission errors, and the bit error rate; If the current data transmission rate meets the requirement of not being higher than a preset second rate threshold, the available space in the receiver buffer is not lower than a preset storage space, the number of data transmission errors is lower than a preset second number threshold, and the bit error rate is not lower than a preset bit error rate threshold, it is determined that the current link state supports the high-speed mode; otherwise, it is determined that the current link state does not support the high-speed mode.

13. A data transmission device, characterized in that, The data transmission device is configured to perform data transmission based on the PCIe-based high-speed data transmission method according to any one of claims 1 to 12.

14. A computer system, characterized in that, It includes the data transmission device as described in claim 13.

Images