Chip control method and device and chip

Abstract

The embodiment of the invention discloses a chip control method and device and a chip, and the control method comprises the steps: judging whether a strong drive signal is received in a preset digital window or not after the factory configuration of a target chip is completed; if so, detecting whether a communication key carried by the strong driving signal is valid; and if yes, cutting off an analog state switch of the main channel, and converting the communication state of the main channel from an analog signal state to a digital signal state. According to the invention, the communication state of the main channel is converted from the analog state to the digital state by using the strong driving signal carrying the communication key, so that the main channel can realize the transmission of the digital signal; the technical problem that in the prior art, a chip needs to independently occupy one pin to serve as an internal parameter flashing interface, so that the integration level of the chip is low is solved, and the technical effects that a parameter flashing interface does not need to be additionally reserved, the integration level of the chip is improved, and the size and cost of the chip are reduced are achieved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of chip control, and in particular, to a control method, device, and chip for a chip. Background Art

[0002] In chip design, a separate communication interface is usually reserved so that the parameters of the internal registers of the chip can be rewritten through this communication interface subsequently. However, this requires a separate pin of the chip, resulting in a low integration degree of the chip. Summary of the Invention

[0003] Embodiments of the present invention provide a control method, device, and chip for a chip, which solve the technical problem of low integration degree of the chip caused by the need for a separate pin of the existing chip as an interface for internal parameter rewriting.

[0004] Embodiments of the present invention provide a control method for a chip. The target chip includes a main channel and a secondary channel, and realizes a communication connection with a host computer through a single-wire dual-channel. The control method includes:

[0005] After the target chip completes the factory configuration, it is determined whether a strong drive signal is received within a preset digital window, where the strong drive signal is a signal transmitted by the host computer through the main channel and carrying a communication key and having a level higher than a preset level value;

[0006] If received, it is detected whether the communication key carried by the strong drive signal is valid;

[0007] If valid, the analog state switch of the main channel is cut off, and the communication state of the main channel is converted from an analog signal state to a digital signal state.

[0008] Further, after converting the communication state of the main channel from an analog signal state to a digital signal state, the control method further includes:

[0009] Obtain the digital-state rewriting signal transmitted by the host computer;

[0010] Based on the rewriting signal, the internal parameters of the target chip are rewritten.

[0011] Further, if the target chip has not completed the factory configuration, the control method further includes:

[0012] Detect whether there is a rising edge or a falling edge of a rewriting signal in the dual-channel of the target chip within a preset duration;

[0013] If present, the channel that first generates the rising edge or the falling edge of the rewriting signal is awakened;

[0014] Based on the wake-up channel, obtain the programming signal transmitted by the host computer, and use the programming signal to implement the internal parameter programming of the target chip.

[0015] Further, the control method further includes:

[0016] If the detection result is that there is no rising edge or falling edge of the programming signal in the dual channels of the target chip within the preset time period, re-detection is performed until a channel that can be awakened is detected.

[0017] Further, before determining whether a strong drive signal is received within a preset digital window, the control method further includes:

[0018] Detect whether the communication status of the main channel is normal;

[0019] If the detection result is that there is a communication fault in the main channel, directly use the secondary channel to obtain the digital programming signal transmitted by the host computer.

[0020] Further, the control method further includes:

[0021] During the communication process using the main channel, control the secondary channel to remain closed.

[0022] Further, the control method further includes:

[0023] Obtain a switch control signal, where the switch control signal is input through a human-computer interaction unit;

[0024] Based on the switch control signal, close the analog state switch of the main channel, and convert the communication state of the main channel from the digital signal state to the analog signal state.

[0025] An embodiment of the present invention further provides a control device for a chip. The target chip includes a main channel and a secondary channel, and realizes a communication connection with the host computer through a single-wire dual-channel. The control device includes:

[0026] A signal judgment unit, configured to determine whether a strong drive signal is received within a preset digital window after the target chip completes the factory configuration, where the strong drive signal is a signal transmitted by the host computer through the main channel and carrying a communication key and having a level higher than a preset level value;

[0027] A key detection unit, configured to detect whether the communication key carried by the strong drive signal is valid if the judgment result of the signal judgment unit is that the strong drive signal is received;

[0028] A status switching unit, configured to cut off the analog state switch of the main channel and convert the communication state of the main channel from an analog signal state to a digital signal state if the detection result of the key detection unit is valid.

[0029] Further, after the status switching unit converts the communication state of the main channel from an analog signal state to a digital signal state, the control device further includes:

[0030] A signal acquisition unit, configured to acquire the digital write signal transmitted by the host computer;

[0031] A chip writing unit, configured to implement internal parameter writing of the target chip based on the write signal.

[0032] An embodiment of the present invention further provides a chip, which includes a single-wire dual-channel controller and an internal chip module; the single-wire dual-channel controller includes the control device of the chip described in any of the above embodiments; the single-wire dual-channel controller and the internal chip module are communicatively connected through a bus;

[0033] The single-wire dual-channel controller includes two input / output interfaces, and the two input / output interfaces respectively generate a main channel and a secondary channel, and the main channel and the secondary channel are communicatively connected to the host computer through a single connection line.

[0034] An embodiment of the present invention discloses a control method, device and chip for a chip. The control method includes: after the target chip completes factory configuration, determining whether a strong drive signal is received within a preset digital window, where the strong drive signal is a signal transmitted by the host computer through the main channel and carrying a communication key and having a level higher than a preset level value; if received, detecting whether the communication key carried by the strong drive signal is valid; if valid, cutting off the analog state switch of the main channel and converting the communication state of the main channel from an analog signal state to a digital signal state. The present application converts the communication state of the main channel from an analog state to a digital state by using a strong drive signal carrying a communication key, so that the main channel can realize the transmission of digital signals, solves the technical problem that the chip in the prior art needs to separately occupy a pin as an interface for internal parameter writing, resulting in low integration of the chip, and realizes the technical effects of not requiring an additional reserved parameter writing interface, improving the integration of the chip, reducing the chip size and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a structural diagram of a single-wire dual-channel chip provided by an embodiment of the present invention;

[0036] Figure 2 is a flowchart of a control method for a chip provided by an embodiment of the present invention;

[0037] Figure 3 It is a structural diagram of a control device for a chip provided by an embodiment of the present invention;

[0038] Figure 4 It is a structural diagram of a single - line dual - channel controller provided by an embodiment of the present invention;

[0039] Figure 5 It is a structural diagram of the main - channel input / output interface control provided by an embodiment of the present invention;

[0040] Figure 6 It is a structural diagram of the sub - channel input / output interface control provided by an embodiment of the present invention. Specific implementation manners

[0041] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the convenience of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0042] It should be noted that the terms "first", "second", etc. in the description, claims and drawings of the present invention are used to distinguish different objects, rather than to limit a specific order. Each of the following embodiments of the present invention can be executed independently, and the embodiments can also be combined with each other for execution. The embodiments of the present invention do not make specific limitations on this.

[0043] In chip design, by multiplexing the I / O (Input / Output) interface, that is, sharing one pin for multiple functions, the same pin can implement different functions in different working modes.

[0044] Figure 1 It is a structural diagram of a single - line dual - channel chip provided by an embodiment of the present invention. Referring to Figure 1 , the host computer 10 can be connected to two I / O ports of the target chip 20 through a single line, respectively generating a main - channel I / O - 1 and a sub - channel I / O - 2. That is, the target chip 20 includes a main channel and a sub - channel, and realizes communication connection with the host computer 10 through a single - line dual - channel. Under normal circumstances, the main channel undertakes the communication work, and only when the main - channel communication fails, will the sub - channel be enabled for communication.

[0045] Figure 2 It is a flowchart of a control method for a chip provided by an embodiment of the present invention. As Figure 2 shown, the control method for this chip specifically includes the following steps:

[0046] S101. After the target chip completes the factory configuration, determine whether a strong drive signal is received within a preset digital window. The strong drive signal is a signal carrying a communication key and having a level higher than a preset level value transmitted by the host computer through the main channel.

[0047] Specifically, the target chip 20 is configured for factory settings, that is, the parameters of the registers inside the target chip 20 are set so that the registers inside the target chip 20 can output corresponding analog signals according to the set parameters. Before the target chip 20 completes the factory configuration, since the registers are not set with parameters, the registers cannot output analog signals normally. At this time, the analog output port of the main channel is in a digital state, that is, the main channel can only transmit digital signals at this time. The host computer 10 can normally access the internal chip module 21 of the target chip 20 through the main channel or the secondary channel and set the register parameters using digital signals. Once the target chip 20 completes the factory configuration, that is, the registers inside the target chip 20 complete the parameter setting, the analog output port of the main channel becomes an analog state and can only transmit analog signals.

[0048] If, after the target chip 20 completes the factory configuration, the host computer 10 wants to access the internal chip module 21 and rewrite the register parameters of the target chip 20 again, it is necessary to change the main channel back to the digital state so that it can transmit digital signals. At this time, the host computer 10 needs to send a strong drive signal to the single-wire dual-channel controller 22 in the target chip 20. The strong drive signal is a signal higher than the preset level value. For example, if the normally transmitted communication signal is a signal with a voltage of 5V, the preset level value can be set to 7V. At the same time, the strong drive signal also carries a pre-set communication key.

[0049] The single-wire dual-channel controller 22 will continuously detect in real time within a given preset digital window whether it receives the strong drive signal transmitted by the host computer 10 through the main channel. Exemplarily, the preset digital window can be set to 6 ms.

[0050] S102. If received, detect whether the communication key carried by the strong drive signal is valid.

[0051] S103. If valid, cut off the analog state switch of the main channel and convert the communication state of the main channel from the analog signal state to the digital signal state.

[0052] Specifically, the single-line dual-channel controller 22 pre-stores a decryption key that matches the communication key carried by the strong drive signal. If the single-line dual-channel controller 22 detects the communication key within a preset digital window and determines that the communication key is valid based on the decryption key, the analog status switch of the main channel is cut off so that the peer status of the main channel is converted from the analog signal state to the digital signal state. At this point, the main channel can perform digital signal communication, and can realize the function of subsequently directly flashing the internal register parameters through the main channel.

[0053] The present application converts the communication state of the main channel from an analog state to a digital state by using a strong driving signal carrying a communication key, so that the main channel can realize the transmission of digital signals, thereby solving the technical problem of low chip integration caused by the chip in the prior art needing to occupy a pin separately as an interface for internal parameter flashing, and achieving the technical effect of not requiring an additional reserved parameter flashing interface, improving chip integration, and reducing chip size and cost.

[0054] On the basis of the above technical solutions, after the communication state of the main channel is converted from the analog signal state to the digital signal state in S103, the control method further includes:

[0055] Obtain the digital flash signal transmitted by the host computer; based on the flash signal, implement the internal parameter flashing of the target chip.

[0056] Specifically, after the main channel is converted into a digital signal state under the action of a strong driving signal, the upper computer 10 can directly send a digital flash signal to the single-line dual-channel controller 22. The single-line dual-channel controller 22 modifies the internal parameters of the target chip 20 based on the flash signal to realize the parameter flashing of the target chip 20.

[0057] On the basis of the above technical solutions, if the target chip has not completed the factory configuration, the control method further includes:

[0058] Detect whether there is a rising edge or falling edge of the flash signal in the dual channels of the target chip within the preset time length; if so, wake up the channel that first generates the rising edge or falling edge of the flash signal; obtain the flash signal transmitted by the host computer based on the awakened channel, and use the flash signal to flash the internal parameters of the target chip.

[0059] Specifically, if the target chip 20 has not been factory configured, the register cannot output analog signals normally because the parameters of the register have not been set. At this time, the analog output port of the main channel is in a digital signal state, that is, the main channel can only transmit digital signals at this time. The host computer 10 can normally access the chip internal module 21 of the target chip 20 through the main channel or the secondary channel, and configure the register parameters through digital signals.

[0060] Specifically, the host computer 10 can normally perform single-wire communication with the target chip 20 through a single-wire dual-channel, and by default, it is the priority main-channel communication. After the target chip 20 is powered on, both the main and secondary channels are in the awakened state at this time. At this time, the single-wire dual-channel controller 22 continuously detects whether there is a rising edge or a falling edge on the main channel or the secondary channel. If detected, the channel that generates the edge first is awakened, and the awakened channel that generates the edge first can be normally communicated to transmit digital signals.

[0061] Optionally, the control method further includes:

[0062] If the detection result is that there is no rising edge or falling edge of the writing signal in the dual channels of the target chip within a preset time period, re-detection is performed until a channel that can be awakened is detected.

[0063] Specifically, if the single-wire dual-channel controller 22 does not detect a rising edge or a falling edge on the main channel or the secondary channel within a preset time period, it returns to the state where the target chip 20 is powered on and both the main channel and the secondary channel are awakened. The single-wire dual-channel controller 22 will re-perform the above detection process until one of the channels meets the wake-up condition, that is, a rising edge or a falling edge is detected on one of the channels within a preset time period. Exemplarily, the preset time period can be set to 2 ms, or can be set to other time periods according to needs, and no specific limitation is made here.

[0064] It should be noted that during the process that the target chip 20 has not completed the factory configuration, if the host computer 10 wants to restore to the analog signal state, relevant registers can be configured through single-wire communication to force the main channel to switch to the analog signal state. At this time, the digital signal state of the main channel is turned off. If you want to continue to access the internal module 21 of the target chip 20, the secondary channel can be used for communication; or by reconfiguring the register parameters, an analog state signal can be output within a preset time window, and a digital state signal can be output outside the preset time window, and no specific limitation is made here.

[0065] Optionally, before determining whether a strong drive signal is received within a preset digital window, the control method further includes:

[0066] Detect whether the communication status of the main channel is normal; if the detection result is that there is a communication fault in the main channel, directly use the secondary channel to obtain the digital writing signal transmitted by the host computer.

[0067] Specifically, if after the target chip 20 is powered on, it is detected that the communication status of the main channel fails and signal transmission cannot be normally performed, then at this time, the host computer 10 can directly transmit the digital writing signal value to the single-wire dual-channel controller 22 through the secondary channel to write the parameters inside the register.

[0068] It should be noted that although the secondary channel can directly transmit the digital flashing signal of the host computer, the secondary channel itself has its own working mode, which is in the input state under normal circumstances. The primary channel is in the analog output state, and a strong drive signal is required to achieve the digital input state, enabling the pins of the primary channel to be multiplexed as the interface for internal parameter flashing. To prevent the occurrence of a small probability event of strong drive signal drive failure and also considering the robustness of the chip, the secondary channel is set as the standby channel when the primary channel fails, and it will only be enabled after the primary channel communication fails.

[0069] Optionally, the control method further includes: during the communication using the primary channel, controlling the secondary channel to remain closed.

[0070] Specifically, during the communication of the primary channel or during the signal transmission through the preset digital window, the secondary channel cannot communicate, that is, the secondary channel needs to always remain in the closed state.

[0071] Optionally, the control method further includes:

[0072] Obtaining a switch control signal, where the switch control signal is input through a human-machine interaction unit; based on the switch control signal, closing the analog state switch of the primary channel, and converting the communication state of the primary channel from the digital signal state to the analog signal state.

[0073] Specifically, after switching the primary channel to the digital communication state, it can be manually switched to the permanent analog signal state. The specific method is that the user inputs a switch control signal through the human-machine interaction unit, and the single-line dual-channel controller 22 controls the analog state switch of the primary channel to close based on the switch control signal, so that the communication state of the primary channel is converted from the digital signal state to the analog signal state. Among them, the human-machine interaction unit can be embodied in any form that can allow the user to input a switch control signal, such as a display screen, a DIP switch, a button, etc., and no specific limitation is made here.

[0074] In an optional embodiment, after switching the primary channel to the digital communication state, the register can be configured to open the analog window during the digital signal communication. During the analog window, the PAD (input / output pin of the chip) is in the analog output state for analog signal transmission, and after the analog window ends, it is switched to the digital state for digital signal transmission.

[0075] Figure 3 It is the structural diagram of a control device for a chip provided by an embodiment of the present invention. Among them, the target chip includes a primary channel and a secondary channel, and realizes the communication connection with the host computer through a single-line dual-channel, as Figure 3 shown, the control device of this chip includes:

[0076] A signal judgment unit 31, configured to determine whether a strong drive signal is received within a preset digital window after the target chip completes factory configuration, where the strong drive signal is a signal carrying a communication key and having a level higher than a preset level value transmitted by the host computer through the main channel;

[0077] A key detection unit 32, configured to detect whether the communication key carried by the strong drive signal is valid if the judgment result of the signal judgment unit is that a strong drive signal is received;

[0078] A state switching unit 33, configured to cut off the analog state switch of the main channel and convert the communication state of the main channel from the analog signal state to the digital signal state if the detection result of the key detection unit is valid.

[0079] Optionally, after the state switching unit 33 converts the communication state of the main channel from the analog signal state to the digital signal state, the control device further includes:

[0080] A signal acquisition unit, configured to acquire a digital write signal transmitted by the host computer;

[0081] A chip writing unit, configured to implement internal parameter writing of the target chip based on the write signal.

[0082] Optionally, if the target chip has not completed factory configuration, the control device further includes:

[0083] A signal detection unit, configured to detect whether there is a rising edge or a falling edge of a write signal in the dual channels of the target chip within a preset duration;

[0084] A channel wake-up unit, configured to wake up the channel that first generates a rising edge or a falling edge of the write signal if the detection result of the signal detection unit is that there is one;

[0085] The chip refresh unit is further configured to acquire a write signal transmitted by the host computer based on the awakened channel and implement internal parameter writing of the target chip by using the write signal.

[0086] Optionally, the signal detection unit is further configured to:

[0087] If the detection result is that there is no rising edge or falling edge of the write signal in the dual channels of the target chip within a preset duration, re-detect until a channel that can be awakened is detected.

[0088] Optionally, before the signal judgment unit 31 determines whether a strong drive signal is received within a preset digital window, the control device further includes:

[0089] A state monitoring unit, configured to detect whether the communication state of the main channel is normal;

[0090] The chip flashing unit is further configured to directly obtain the digital flashing signal transmitted by the host computer through the secondary channel if the detection result of the status monitoring unit indicates that there is a communication fault in the primary channel.

[0091] Optionally, the control device further includes:

[0092] A channel control unit, configured to control the secondary channel to remain closed during the communication process of the chip flashing unit using the primary channel.

[0093] Optionally, the status switching unit is further configured to obtain a switch control signal, where the switch control signal is input through the human-machine interaction unit; and based on the switch control signal, close the analog state switch of the primary channel, and convert the communication state of the primary channel from the digital signal state to the analog signal state.

[0094] The control device of the chip provided by the embodiment of the present invention has the same technical features as the chip control method provided by the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0095] The embodiment of the present invention further provides a chip, as Figure 1 shown. The chip includes a single-wire dual-channel controller 22 and an internal chip module 21; the single-wire dual-channel controller 22 includes the control device of the chip in any of the above embodiments; the single-wire dual-channel controller 22 and the internal chip module 21 are communicatively connected through a bus.

[0096] The single-wire dual-channel controller 22 includes two input / output interfaces (i.e., Figure 1 I / O-1 and I / O-2 shown in

[0097] Figure 4 ), and the two input / output interfaces respectively generate a primary channel and a secondary channel. The primary channel and the secondary channel are communicatively connected to the host computer 10 through a single connection line.

[0098] Optionally, as Figure 4 shown, the single-wire dual-channel controller 22 specifically includes a single-wire communication controller and a channel selection controller. Among them, the single-wire communication controller includes the control device of the chip in any of the above embodiments. The single-wire communication controller receives the channel input selected by the channel selection controller, and then sends the communication signal to the internal chip module 21; or outputs the communication signal of the internal chip module 21 through the channel selected by the channel selection controller. The channel selection controller is configured to output the enable signals of the primary and secondary channels to implement the input / output selection of the primary and secondary channels.

[0099] Figure 5 is the control structure diagram of the primary channel input / output interface provided by the embodiment of the present invention.Figure 6 It is the control structure diagram of the secondary channel input / output interface provided by the embodiment of the present invention.

[0100] As Figure 5 shown, only when the analog state switch of the main channel is turned on can digital signal communication be carried out normally; otherwise, the main channel is in the analog signal state. When the main / secondary channel input enable is high and the output enable is low, it is a write operation at this time. The main or secondary channel input is sent to the single-wire communication controller through the channel selection controller and the controller input, and the data is sent to the internal module. When the main / secondary channel input enable is low and the output enable is high, it is a read operation at this time. The channel selection controller outputs the main / secondary channel output enable signal, enabling the selected output PAD (the input / output pin of the chip), and the single-wire output of the single-wire communication controller outputs the signal to the host computer 10 through the selected PAD. The opening and closing of the analog state switch are controlled by the single-wire dual-channel communication controller.

[0101] Refer to Figure 6 , Figure 6 for the multiplexing of the PAD and analog input in . When using the secondary channel for communication, just directly input the single-wire communication signal to access the internal module 21 of the chip. The secondary channel is used as a backup channel and is generally only used when the main channel cannot be accessed; otherwise, it will affect the analog input signal of the PAD.

[0102] The chip provided by the embodiment of the present invention includes the control device of the chip in the above embodiment. Therefore, the chip provided by the embodiment of the present invention also has the beneficial effects described in the above embodiment, which will not be elaborated here.

[0103] In the description of the embodiment of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0104] Finally, it should be noted that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A control method for a chip, characterized in that, The target chip includes a main channel and a secondary channel, and realizes communication connection with the host computer through single-wire dual-channel. The control method includes: After the target chip completes the factory configuration, it is judged whether a strong drive signal is received within a preset digital window. Wherein, the strong drive signal is a signal carried with a communication key and with a level higher than a preset level value transmitted by the host computer through the main channel; If received, it is detected whether the communication key carried by the strong drive signal is valid; If valid, the analog state switch of the main channel is cut off, and the communication state of the main channel is converted from the analog signal state to the digital signal state.

2. The control method of the chip according to claim 1, characterized in that After the communication state of the main channel is converted from the analog signal state to the digital signal state, the control method further includes: Obtaining the digital-state writing signal transmitted by the host computer; Based on the writing signal, the internal parameters of the target chip are written.

3. The control method of the chip according to claim 1, wherein If the target chip has not completed the factory configuration, the control method further includes: Detecting whether there is a rising edge or a falling edge of the writing signal in the dual channels of the target chip within a preset duration; If present, the channel that first generates the rising edge or the falling edge of the writing signal is woken up; Based on the woken-up channel, the writing signal transmitted by the host computer is obtained, and the internal parameters of the target chip are written by using the writing signal.

4. The control method of the chip according to claim 3, wherein The control method further includes: If the detection result is that there is no rising edge or falling edge of the writing signal in the dual channels of the target chip within the preset duration, re-detection is performed until a channel that can be woken up is detected.

5. The control method of the chip according to claim 1, wherein Before judging whether a strong drive signal is received within a preset digital window, the control method further includes: Detecting whether the communication state of the main channel is normal; If the detection result is that the main channel has a communication fault, the digital-state writing signal transmitted by the host computer is directly obtained by using the secondary channel.

6. The control method of the chip according to claim 1, wherein The control method further includes: During the process of communicating by using the main channel, the secondary channel is controlled to remain closed.

7. The control method of the chip according to claim 1, wherein The control method further includes: Obtaining a switch control signal, where the switch control signal is input through a human-computer interaction unit; Based on the switch control signal, the analog state switch of the main channel is closed, and the communication state of the main channel is converted from the digital signal state to the analog signal state.

8. A control device for a chip, characterized in that, The target chip includes a main channel and a secondary channel, and realizes communication connection with the host computer through single-wire dual-channel. The control device includes: A signal judgment unit, configured to judge whether a strong drive signal is received within a preset digital window after the target chip completes the factory configuration. Wherein, the strong drive signal is a signal carried with a communication key and with a level higher than a preset level value transmitted by the host computer through the main channel; A key detection unit, configured to detect whether the communication key carried by the strong drive signal is valid if the judgment result of the signal judgment unit is that the strong drive signal is received; A state switching unit, configured to cut off the analog state switch of the main channel and convert the communication state of the main channel from an analog signal state to a digital signal state if the detection result of the key detection unit is valid.

9. The control device of the chip according to claim 8, characterized in that, After the state switching unit converts the communication state of the main channel from an analog signal state to a digital signal state, the control device further includes: A signal acquisition unit, configured to acquire a digital write signal transmitted by the host computer; A chip writing unit, configured to implement internal parameter writing of the target chip based on the write signal.

10. A chip, characterized in that, The chip includes a single-wire dual-channel controller and an internal chip module; the single-wire dual-channel controller includes the control device of the chip according to any one of claims 8-9 above; the single-wire dual-channel controller and the internal chip module are communicatively connected through a bus; The single-wire dual-channel controller includes two input / output interfaces, and the two input / output interfaces respectively generate a main channel and a secondary channel, and the main channel and the secondary channel are communicatively connected to the host computer through a single connection line.

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