System and device for verifying RFID tag chip based on SystemVerilog, and storage medium

Abstract

The invention discloses an RFID (Radio Frequency Identification) tag chip verification system and device based on SystemVerilog, and a storage medium. The system comprises a use case database, a generator module, a driver module, an input monitoring module, a reference model module and a result comparison module. Wherein a plurality of test cases are stored in the case database; the generator module is used for generating an excitation sequence according to the test case; the driver module is used for converting the excitation sequence into a verification operation instruction and sending the verification operation instruction to the chip to be tested and the reference model module; the input monitoring module is used for capturing the actual output response of the chip to be detected; the reference model module is used for simulating an ideal output response of the chip to be tested according to the verification operation instruction; and the result comparison module is used for comparing the actual output response with the ideal output response to obtain a verification result of the chip to be tested. The verification system provided by the invention not only ensures the function correctness of the RFID tag chip, but also ensures the reliability of the RFID tag chip in practical application, and can greatly improve the verification efficiency and quality.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency identification, and in particular, to an RFID tag chip verification system, device and storage medium based on SystemVerilog. Background Art

[0002] With the wide application of near field communication (RFID) technology, the design and verification of RFID tag chips have become key steps to ensure product reliability and performance. RFID technology has attracted much attention due to its applications in payment, access control, information exchange, etc.

[0003] In order to ensure that RFID tag chips can meet the requirements of high performance and low power consumption, it is necessary to verify RFID tag chips to ensure their performance. However, in the field of RFID tag chip verification, traditional verification methods can no longer meet the growing demands. For example, due to the complexity and functional diversity of RFID tag chip design, traditional manual testing methods are not only time-consuming and laborious, but also difficult to cover all test scenarios.

[0004] Currently, for the verification of RFID tag chips, although there are some commercial verification platforms that provide certain support, these platforms often focus on specific application scenarios and lack highly customized verification solutions for the characteristics of RFID tag chips. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an RFID tag chip verification system, device and storage medium based on SystemVerilog.

[0006] The first aspect of the present invention provides an RFID tag chip verification system based on SystemVerilog, including a use case database, a generator module, a driver module, an input monitoring module, a reference model module and a result comparison module;

[0007] Wherein, the use case database stores multiple test cases;

[0008] The generator module is used to generate an excitation sequence according to the test case and transfer the excitation sequence to the driver module;

[0009] The driver module is used to convert the excitation sequence into a verification operation instruction and send the verification operation instruction to the chip under test and the reference model module;

[0010] The input monitoring module is used to capture the actual output response of the chip under test and transmit the actual output response of the chip under test as a first response signal to the result comparison module;

[0011] The reference model module is used to simulate the ideal output response of the chip under test according to the verification operation instruction, and transmit the ideal output response of the reference model module to the result comparison module as the second response signal;

[0012] The result comparison module is used to compare the first response signal with the second response signal to obtain the verification result of the chip under test.

[0013] Furthermore, the test case records the operation steps of the test process; the test case specifically includes a function test case, an extreme value test case, an abnormal test case, and a performance test case.

[0014] Furthermore, the generator module generates an excitation sequence according to the test case, specifically including the following steps:

[0015] Determine the target variables to be tested in the test case;

[0016] Specify the relationships between the target variables and the value ranges of the target variables as the constraint conditions of the target variables;

[0017] Generate random values that meet the constraint conditions of the target variables and assign them to the target variables;

[0018] Load the assigned target variables into the corresponding test cases and combine multiple test cases to generate an excitation sequence.

[0019] Furthermore, the driver module converts the excitation sequence into a verification operation instruction through the following steps:

[0020] Perform protocol encapsulation on the excitation sequence according to the interface protocol of the chip under test;

[0021] Define a clock signal and perform timing control on the excitation sequence encapsulated with the interface protocol according to the timing requirements of the interface protocol;

[0022] Convert the excitation sequence into a verification operation instruction based on timing.

[0023] Furthermore, the actual output response of the chip under test specifically includes a data output signal, a status change signal, an external interaction signal, and a read / write response signal.

[0024] Furthermore, the input monitoring module captures the actual output response of the chip under test through the following steps:

[0025] Sample the data of the chip under test at the clock edge to obtain a data output signal;

[0026] Monitor the level change inside the chip under test to obtain a status change signal;

[0027] Capture the signaling data sent out by the chip under test to obtain an external interaction signal;

[0028] Sample the response code of the chip under test, associate the read and write operations of the chip under test according to the response code, and obtain a read and write response signal.

[0029] Further, the reference model module completes the simulation of the chip under test through the following steps:

[0030] Obtain the interface data of the chip under test, establish a virtual interface to simulate the input and output interfaces of the chip under test, and input or output data through the virtual interface;

[0031] According to the functional description of the chip under test, perform behavioral modeling on the chip under test in the reference model, simulate the behavioral functions of the chip under test, and obtain an ideal output response.

[0032] Further, after the result comparison module obtains the verification result of the chip under test, the following steps are further included:

[0033] Perform an execution regression test on the chip under test to determine the code coverage rate and functional coverage rate of the chip under test.

[0034] The second aspect of the present invention discloses an electronic device, including a processor and a memory;

[0035] The memory is used to store the program of a SystemVerilog-based RFID tag chip verification system described in the first aspect;

[0036] The processor is used to execute the program.

[0037] The second aspect of the present invention discloses a computer-readable storage medium, the storage medium stores a program of a SystemVerilog-based RFID tag chip verification system described in the first aspect, and the program can be executed by a processor.

[0038] The embodiments of the present invention have the following beneficial effects: The SystemVerilog-based RFID tag chip verification system, device and storage medium proposed by the present invention achieve an efficient verification process, which has a clear hierarchical structure. Through parameterized interface data and address width, the system finally has good flexibility. The present invention conducts a large number of randomized tests through different test cases, significantly improving the efficiency and credibility of verification. The verification system provided by the present invention not only ensures the functional correctness of the RFID tag chip, but also ensures its reliability in actual applications, and can greatly improve the verification efficiency and quality.

[0039] Additional aspects and advantages of the present invention will be given in the following description section, some will become apparent from the following description, or can be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0041] Figure 1 It is a schematic diagram of the framework structure of the RFID tag chip verification system based on SystemVerilog of the present invention.

[0042] Figure 2 It is a schematic diagram of the verification test effect of the chip to be tested using the RFID tag chip verification system based on SystemVerilog of the present invention.

[0043] Figure 3 It is a schematic diagram of the structure of an electronic device of the present invention.

[0044] Figure 4 It is a schematic diagram of the structure of a computer-readable storage medium of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the following further details the present application in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] The first embodiment of the present invention provides an RFID tag chip verification system based on SystemVerilog, including a use case database, a generator module, a driver module, an input monitoring module, a reference model module, and a result comparison module.

[0047] The RFID tag chip verification system provided by the present invention is built using the SystemVerilog methodology and has a modular architecture design. SystemVerilog is a high-level hardware description language extended from traditional Verilog HDL. It supports object-oriented programming features, enabling verification engineers to build reusable and extensible verification components. Therefore, the RFID tag chip verification system built by the present invention has a clear hierarchical structure and good flexibility through parameterized interface data and address widths.

[0048] Such as Figure 1As shown in the figure, the RFID tag chip verification system built by the present invention includes a Test_top layer and an Enviorment layer. Among them, a use case database, a system clock, and an interface for connecting the chip under test (DUT, Device under test) are set in the Test_top layer. The chip under test is connected to the Enviorment layer through the physical interface of the Test_top layer for verification testing; the system clock is used to provide timing so that the verification system, the physical interface, and the chip under test use the same clock and reset signal; multiple test cases are stored in the use case database.

[0049] In the embodiments of the present invention, the test cases are mainly imported into the use case database in the form of code from the outside; in some embodiments, the test cases can also be obtained by loading using system functions in text form. The test cases are used to record the operation steps of the test implementation process and can verify whether the functions of the chip under test meet the expectations in specific scenarios. The test cases specifically include functional test cases, extreme value test cases, exception test cases, and performance test cases; among them, the functional test cases are used to verify whether the functions of the chip under test meet the design specifications; the boundary test cases are used to check the function implementation effect of the chip under test in extreme scenarios or boundary conditions; the exception test cases are used to check the processing ability of the chip under test in various abnormal scenarios; the performance test cases are used to check the performance index situation of the chip under test when executing functions. The test cases imported in the embodiments of the present invention focus on general commands, such as entering wake-up, waiting, reset, and application according to instructions; through different types of test cases, the chip under test can be tested completely and comprehensively to ensure that the various parameters of the chip under test meet the design expectations.

[0050] Each function execution module of the verification system is encapsulated in the Enviorment layer, including a generator module, a driver module, an input monitoring module, a reference model module, and a result comparison module. Through the cooperation of the modules in the Enviorment layer, a complete verification environment is formed.

[0051] Generator module: In the embodiments of the present invention, the generator module is used to generate an excitation sequence according to the test cases and transfer the excitation sequence to the driver module. In the embodiments of the present invention, the generator module generates an excitation sequence according to the test cases, specifically including the following steps:

[0052] S101. Determine the target variables to be tested in the test cases. In the chip verification environment, since there are too many test scenarios to be covered, one or more target variables need to be defined for each test case, and random values are taken for the target variables to avoid the inefficiency of manually writing fixed test cases. In SystemVerilog, the rand keyword can be used to declare the target variables and specify their data types as needed.

[0053] S102. Specify the relationships between target variables and the value ranges of target variables as the constraint conditions for the target variables.

[0054] To ensure that the generated test cases meet specific conditions or follow certain rules, it is necessary to specify the relationships between target variables and limit the value ranges of target variables as constraint conditions. In SystemVerilog, constraint conditions can be set by adding constraint blocks. Specifically, the generated constraint blocks include unconditional constraint blocks and conditional constraint blocks. Among them, unconditional constraint blocks are effective in any case, and conditional constraint blocks are only effective when the preset trigger conditions are met.

[0055] S103. Generate random values that meet the constraint conditions of the target variables and assign them to the target variables. After setting the target variables and constraint conditions, legal random values are generated according to the constraints and applied to the target variables. In SystemVerilog, random values can be generated by calling the randomize() method. Specifically, if it is necessary to dynamically modify the constraints or add additional conditions, the with clause can be used during the call; the with clause can temporarily add or overwrite the original constraints to achieve more flexible test scenarios.

[0056] S104. Load the assigned target variables into the corresponding test cases and combine multiple test cases to generate an excitation sequence. After completing the assignment of the target variables, multiple groups of test cases are packaged to form an excitation sequence. In SystemVerilog, an excitation sequence can be generated in a case by following predefined rules and constraints.

[0057] In the verification system of the embodiments of the present invention, through the design of the generator, the content and order of the excitation can be flexibly adjusted according to needs, thereby improving the test coverage rate and the ability to discover potential problems.

[0058] Driver module: In the embodiments of the present invention, the driver module is used to convert the excitation sequence into verification operation instructions and send the verification operation instructions to the chip under test and the reference model module. Specifically, the driver module converts the excitation sequence into verification operation instructions through the following steps:

[0059] S201. Perform protocol encapsulation on the excitation sequence according to the interface protocol of the chip under test. Since the chip under test may have different interface protocols (such as AXI, APB, I2C, etc.), it is necessary to perform protocol encapsulation on the excitation sequence to ensure that it can be read by the chip under test. The operations of protocol encapsulation include adding protocol fields, timing alignment, etc.

[0060] S202. Define a clock signal and perform timing control on the excitation sequence encapsulating the interface protocol according to the timing requirements of the interface protocol. In the embodiment of the present invention, the system clock of the Test_top layer of the verification system is used as the basis for timing control to clarify the timing relationships of various key signals (including clock signals, reset signals, data signals, etc.), ensuring that signal changes occur at the valid edges of the clock.

[0061] S203. Convert the excitation sequence into verification operation instructions based on timing. After completing protocol encapsulation and timing control, in SystemVerilog, the drive_transaction() method can be used to convert the excitation sequence into verification operation instructions and drive the verification operation instructions into the chip under test for verification testing.

[0062] In the embodiment of the present invention, the driver module can convert the abstract data packet into specific verification operation instructions and drive the verification operation instructions into the chip under test and the reference model module for verification testing. As Figure 2 shown is the effect diagram of using the RFID tag chip verification system based on SystemVerilog of the present invention to perform verification testing on the chip under test. The chip under test obtains verification operation instructions such as REQA, WUPA, ANTI_DONE, etc. from the verification system to control the chip under test to complete operations such as data calculation, state change, and interactive signal sending to verify the reliability of the chip under test.

[0063] Input monitoring module: In the embodiment of the present invention, the input monitoring module is used to capture the actual output response of the chip under test and transmit the actual output response of the chip under test to the result comparison module as the first response signal. The possible actual output responses of the chip under test include data output signals, state change signals, external interactive signals, and read / write response signals. In the embodiment of the present invention, the input monitoring module captures the actual output response of the chip under test through the following steps:

[0064] Data output signal: The data output signal represents the calculation result or transmitted data formed after the chip under test processes the input verification operation instructions, including the instruction execution result of the processor, etc. In the embodiment of the present invention, the data of the chip under test is sampled at the clock edge by the input monitoring module to obtain the data output signal.

[0065] State change signal: The state change signal can indicate the working state or operation result of the chip under test. In the embodiment of the present invention, the input monitoring module continuously monitors the level change inside the chip under test to obtain the state change signal.

[0066] External interaction signal: The external interaction signal represents the handshake or confirmation signal sent out by the chip under test. In the embodiments of the present invention, the input monitoring module captures the signaling data sent out by the chip under test and parses to obtain the external interaction signal.

[0067] Read-write response signal: The read-write response signal represents the read-write response of the chip under test to the bus operation. In the embodiments of the present invention, the input monitoring module samples the response code of the chip under test, correlates the read-write operation of the chip under test according to the response code, and obtains the read-write response signal.

[0068] Reference model module: In the embodiments of the present invention, the reference model module is used to simulate the ideal output response of the chip under test according to the verification operation instruction, and transmits the ideal output response of the reference model module to the result comparison module as the second response signal. In the embodiments of the present invention, the reference model is implemented by Systemverilog and embedded in the verification environment through modular design.

[0069] Specifically, when establishing the reference model, first obtain the interface data of the chip under test, determine the input and output interfaces and internal logic of the chip under test, then establish a virtual interface (Virtual Interface) to simulate the input and output interfaces of the chip under test, and input or output data through the virtual interface. Secondly, according to the function description of the chip under test, perform behavioral modeling on the chip under test in the reference model, simulate the behavioral functions of the chip under test, and obtain the ideal output response.

[0070] In the embodiments of the present invention, the reference model module simulates the functions designed by the chip under test and generates the ideal output response, and these results will be compared with the actual output response of the chip under test to ensure that the design implementation meets the expectations.

[0071] Result comparison module: In the embodiments of the present invention, the result comparison module is used to compare the first response signal with the second response signal to obtain the verification result of the chip under test. The result comparison module receives the actual output response from the input monitoring module and the ideal output response from the reference model module, and then compares whether the two are consistent. If they are consistent, it notifies the driver to continue sending new verification operation instructions; if they are inconsistent, it reports an error and may stop the verification process.

[0072] In some embodiments, after the result comparison module obtains the verification result of the chip under test, the following steps are further included:

[0073] Perform regression testing on the chip under test to determine the code coverage and function coverage of the chip under test.

[0074] Regression testing refers to the process of re-running existing test cases when making modifications to the chip under test or switching verification scenarios, ensuring that the original functions are not damaged. As a crucial verification method, regression testing not only guarantees that no new issues are introduced when fixing existing defects but also maintains the effectiveness of previously passed test cases. It runs throughout the entire chip verification process to ensure that even after achieving the expected code and functional coverage, the system still undergoes thorough regression testing. Only when all regression tests are successfully passed can the verification phase be officially declared complete. This method not only ensures the technical accuracy of the design solution but also guarantees the stability and reliability of the product throughout its entire life cycle.

[0075] The verification system of the embodiments of the present invention is developed based on the scenarios of the ISO / IEC 14443 standard protocol, enabling broader compatibility and functional versatility. By leveraging advanced features of SystemVerilog such as classes, interfaces, randomization, etc., a highly flexible and reusable verification platform can be constructed. For example, in the design of the generator, diverse stimuli can be achieved by writing complex constraint conditions to make the tests more comprehensive. In addition, adopting the concept of object-oriented programming (OOP) can make the code easier to maintain and extend, further enhancing the flexibility and scalability of the verification system. The verification system of the embodiments of the present invention is particularly suitable for fields with strict verification requirements such as RFID tag chips, which can significantly shorten the verification cycle and improve product quality. At the same time, code coverage and functional coverage are collected through regression testing to ensure that the design is not only technically correct but also remains stable and reliable throughout its life cycle. This enables the design team to maintain the effectiveness of previously passed test cases while fixing defects, ensuring the project schedule.

[0076] Figure 3 It is a schematic structural diagram of the electronic device proposed in the second embodiment of the present invention. In this embodiment, the memory stores program instructions for implementing the SystemVerilog-based RFID tag chip verification system of any of the above embodiments. The processor is used to execute the program instructions stored in the memory for SystemVerilog-based RFID tag chip verification. Among them, the processor can also be referred to as the CPU (Central Processing Unit). The processor may be an integrated circuit chip with signal processing capabilities. The processor can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0077] The content of the system in the first embodiment of the present invention is applicable to the embodiment of the present electronic device. The function specifically implemented in the embodiment of the present electronic device is the same as that in the above system embodiment, and the beneficial effects achieved are also the same as those of the above system.

[0078] Figure 4 It is a schematic structural diagram of a computer-readable storage medium according to the third embodiment of the present invention. The computer-readable storage medium of the fourth embodiment of the present invention stores program instructions capable of implementing the above-mentioned RFID tag chip verification system based on SystemVerilog. Among them, the program instructions can be stored in the above storage medium in the form of a software product, including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods in various embodiments of the present invention. The aforementioned computer-readable storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, or terminal devices such as computers, servers, mobile phones, and tablets.

[0079] The content of the system in the first embodiment of the present invention is applicable to the embodiment of the present computer-readable storage medium. The function specifically implemented in the embodiment of the present computer-readable storage medium is the same as that in the above system embodiment, and the beneficial effects achieved are also the same as those of the above system.

[0080] This embodiment also provides a computer program product. When the computer program product runs on a computer, it causes the computer to execute the above-related steps to implement the RFID tag chip verification system based on SystemVerilog provided in the above embodiment.

[0081] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data that have been authorized by the user or fully authorized by all parties. And the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for the user to select authorization or rejection.

[0082] Those skilled in the art can understand that the modules in the devices in the embodiments of the present invention can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments of the present invention can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the corresponding claims, abstract and drawings) and all the processes or units of any method or device thus disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the corresponding claims, abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0083] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above functions can be allocated to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0084] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus or device), or used in combination with these instruction execution systems, apparatuses or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport a program for use by or in connection with an instruction execution system, apparatus or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation or other suitable processing as necessary, and then stored in a computer memory.

[0085] In addition, each embodiment in this specification is described in a progressive manner, and the same or similar parts among the embodiments can be referred to each other. In particular, for embodiments of devices, equipment, etc., since they are basically similar to the method embodiments, the relevant parts can refer to the partial descriptions of the method embodiments. The embodiments of devices, equipment, etc. described above are only illustrative. The modules, units, etc. described as separate components may or may not be physically separated, that is, they can be located in one place or distributed to multiple places, such as the nodes of a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above-described embodiment solutions. Those skilled in the art can understand and implement without creative work.

[0086] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiment, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following well-known technologies in the art can be used: discrete logic circuits with logic gate circuits for implementing logic functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0087] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0088] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated in this embodiment. Thus, the features defined with the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that at least one such feature is included in this embodiment. In the description of the present invention, the meaning of the word "plurality" is at least two or more, such as two, three, four, etc., unless otherwise specifically defined in the embodiment.

[0089] In an embodiment of the present invention, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of another identical element in the process, method, article or device comprising such element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0090] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. After considering the specification and practicing the present invention, those skilled in the art will readily conceive of other embodiments of the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.

Claims

1. An RFID tag chip verification system based on SystemVerilog, characterized in that It includes a use case database, a generator module, a driver module, an input monitoring module, a reference model module, and a result comparison module; Among them, the use case database stores multiple test cases; The generator module is used to generate an excitation sequence according to the test cases and transfer the excitation sequence to the driver module; The driver module is used to convert the excitation sequence into a verification operation instruction and send the verification operation instruction to the chip under test and the reference model module; The input monitoring module is used to capture the actual output response of the chip under test and transmit the actual output response of the chip under test as a first response signal to the result comparison module; The reference model module is used to simulate the ideal output response of the chip under test according to the verification operation instruction and transmit the ideal output response of the reference model module as a second response signal to the result comparison module; The result comparison module is used to compare the first response signal with the second response signal to obtain the verification result of the chip under test.

2. The RFID tag chip verification system based on SystemVerilog according to claim 1, wherein The test cases record the operation steps of the test process; the test cases specifically include function test cases, extreme value test cases, abnormal test cases, and performance test cases.

3. The RFID tag chip verification system based on SystemVerilog according to claim 2, wherein The generator module generates an excitation sequence according to the test cases, specifically including the following steps: Determine the target variables to be tested in the test cases; Specify the relationships between the target variables and the value ranges of the target variables as the constraint conditions of the target variables; Generate random values that meet the constraint conditions of the target variables and assign them to the target variables; Load the assigned target variables into the corresponding test cases and combine multiple test cases to generate an excitation sequence.

4. A SystemVerilog-based RFID tag chip verification system according to claim 1, wherein, The driver module converts the excitation sequence into a verification operation instruction through the following steps: Perform protocol encapsulation on the excitation sequence according to the interface protocol of the chip under test; Define a clock signal and perform timing control on the excitation sequence encapsulated with the interface protocol according to the timing requirements of the interface protocol; Convert the excitation sequence into a verification operation instruction based on timing.

5. The RFID tag chip verification system based on SystemVerilog according to claim 1, characterized in that The actual output response of the chip under test specifically includes a data output signal, a status change signal, an external interaction signal, and a read / write response signal.

6. The RFID tag chip verification system based on SystemVerilog according to claim 5, characterized in that, The input monitoring module captures the actual output response of the chip under test through the following steps: Sample the data of the chip under test at the clock edge to obtain a data output signal; Monitor the level change inside the chip under test to obtain a status change signal; Capture the signaling data sent by the chip under test externally to obtain an external interaction signal; Sample the response code of the chip under test and associate the read / write operation of the chip under test according to the response code to obtain a read / write response signal.

7. The RFID tag chip verification system based on SystemVerilog according to claim 1, characterized in that The reference model module completes the simulation of the chip under test through the following steps: Obtain the interface data of the chip under test, establish a virtual interface to simulate the input / output interface of the chip under test, and input or output data through the virtual interface; According to the function description of the chip under test, perform behavioral modeling on the chip under test in the reference model, simulate the behavioral functions of the chip under test, and obtain an ideal output response.

8. The RFID tag chip verification system based on SystemVerilog according to claim 1, characterized in that, After the result comparison module obtains the verification result of the chip under test, the following steps are further included: Perform regression testing on the chip under test to determine the code coverage and functional coverage of the chip under test.

9. An electronic device, characterized in that, It includes a processor and a memory; The memory is used to store a program of a SystemVerilog-based RFID tag chip verification system according to any one of claims 1-8; The processor is used to execute the program.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program of a SystemVerilog-based RFID tag chip verification system according to any one of claims 1-8, and the program can be executed by a processor.

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