Synchronization unit verification method and device, electronic equipment and storage medium
By obtaining the mapping relationship of the synchronization unit and the number of errors of the error type, the test case with the most errors is determined, which solves the problem of low efficiency of synchronization unit verification and realizes efficient and accurate synchronization unit verification.
Patent Information
- Application Number
- CN202510428210.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-07-18
AI Technical Summary
The verification efficiency of synchronization units in the prior art is low because the error of the same synchronization unit requires repeated simulation verification multiple times, and the input and output signals cannot be effectively checked, resulting in poor verification accuracy.
After performing assertion testing on M synchronization units in N test cases, the mapping relationship is obtained, and the test case name with the most errors is determined based on the hierarchy of each target synchronization unit and the number of errors of the error type, and sent it to the client for waveform simulation verification.
It improves the verification efficiency of the synchronization unit, avoids repeated simulation, shortens verification time, improves the targetedness and accuracy of verification, and saves labor costs.
Smart Images
Figure CN120337834A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technologies, and in particular, to a method, apparatus, electronic device, and storage medium for verifying a synchronization unit. Background Art
[0002] In digital circuit design, a synchronization unit (sync cell) is a very important and commonly used unit. A synchronization unit is a circuit structure used to achieve data synchronization across clock domains (Clock Domain Crossing, CDC) in digital circuit design. Its function is to ensure that data can be safely and accurately transmitted from one clock domain to another, and the clock frequencies and clock phases of these two clock domains may be different. In complex digital circuit design, synchronization units are key technical means to ensure the correct transmission of data between different clock domains. Therefore, the verification of synchronization units is particularly important.
[0003] The traditional verification method is to write targeted test cases for signals across clock domains to verify the functions of synchronization units. For the same synchronization unit, multiple test cases are usually required for function verification; and in the verification results, errors of the same synchronization unit may appear in different test cases. Since it is necessary to re-simulate and verify each error of each synchronization unit that appears in each test case, there will be a situation of repeated simulation verification of the same synchronization unit error, thus resulting in low verification efficiency of synchronization units. Summary of the Invention
[0004] This application provides a method, apparatus, electronic device, and storage medium for verifying a synchronization unit, so as to at least solve the problem in the related art that repeated simulation verification of the same synchronization unit error leads to low verification efficiency of synchronization units.
[0005] The present application provides a verification method for a synchronization unit. The method includes: after N test cases perform assertion tests on M synchronization units, obtaining at least one mapping relationship. Each mapping relationship is a mapping relationship between each test case name and the hierarchical structure corresponding to each target synchronization unit, each error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type. Each target synchronization unit is one of at least one target synchronization unit that has an error during the assertion test among the M synchronization units. N≥1 and is a positive integer, and M≥1 and is a positive integer; based on the hierarchical structure corresponding to each target synchronization unit, querying each error type corresponding to each target synchronization unit and the number of errors corresponding to each error type in at least one mapping relationship; based on the number of errors corresponding to each error type, determining at least one target test case name corresponding to each target synchronization unit. Each target test case name is the name of the test case that triggers each error type of error when each target synchronization unit performs an assertion test, and the number of errors corresponding to each error type is the largest; sending at least one target test case name to the client.
[0006] The present application also provides a verification device for a synchronization unit. The device includes: a transceiver module, configured to obtain at least one mapping relationship after N test cases perform assertion tests on M synchronization units. Each mapping relationship is a mapping relationship between each test case name and the hierarchical structure corresponding to each target synchronization unit, each error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type. Each target synchronization unit is one of at least one target synchronization unit that has an error during the assertion test among the M synchronization units. N≥1 and is a positive integer, and M≥1 and is a positive integer. A processing module, configured to query each error type corresponding to each target synchronization unit and the number of errors corresponding to each error type in at least one mapping relationship based on the hierarchical structure corresponding to each target synchronization unit. The processing module is further configured to determine at least one target test case name corresponding to each target synchronization unit based on the number of errors corresponding to each error type. Each target test case name is the name of the test case that triggers each error type of error when each target synchronization unit performs an assertion test, and the number of errors corresponding to each error type is the largest. The transceiver module is further configured to send at least one target test case name to the client.
[0007] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above verification methods for a synchronization unit when executing the computer program.
[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, when the computer program is executed by a processor, the steps of any one of the above verification methods for a synchronization unit are implemented.
[0009] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of any one of the above verification methods for the synchronization unit.
[0010] Through the present application, since at least one mapping relationship can be obtained, at least one target synchronization unit with an error can be determined. Also, based on the error type and the number of errors, at least one target test case with the most error occurrences can be selected from multiple test cases for each target synchronization unit, and then the names of at least one target test case are sent to the client, enabling the verification personnel to perform waveform simulation verification on the target synchronization unit based on at least one target test case in a targeted manner. At the same time, it avoids the situation where the verification personnel repeatedly perform simulation verification on the same synchronization unit error, making the analysis of the synchronization unit more targeted, shortening the verification time, improving the verification efficiency, and saving labor costs. Description of the Drawings
[0011] To more clearly illustrate the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0012] Figure 1 Topological structure diagram of the verification system for the synchronization unit provided by the embodiment of the present application;
[0013] Figure 2 Flow diagram of a verification method for a synchronization unit provided by the embodiment of the present application;
[0014] Figure 3 Schematic diagram of the generation of the configuration file provided by the embodiment of the present application;
[0015] Figure 4 Schematic diagram of the generation of the document where at least one mapping relationship provided by the embodiment of the present application is located;
[0016] Figure 5 Block diagram of the structure of the verification device for the synchronization unit provided by the embodiment of the present application;
[0017] Figure 6 Hardware structure diagram of an electronic device provided by the embodiment of the present application. Detailed Embodiments
[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.
[0019] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0020] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0021] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the method for generating a literature review depends, the specific application environment architecture or specific hardware architecture is described herein.
[0022] The embodiments of the present application are applied to the scenario of verifying synchronous units in digital circuit design.
[0023] A synchronous unit (also known as a sync cell) is a circuit structure used to achieve cross-clock domain data synchronization in digital circuit design. The functions of the synchronous unit include: eliminating metastability, data synchronization, clock domain isolation, and improving system stability. Among them, metastability refers to the situation where a flip-flop cannot reach a definite state (for example, the 0 or 1 state) within a predetermined time. The synchronous unit can solve the metastability problem by introducing two or more flip-flops between two clock domains. Data synchronization means that the synchronous unit can ensure that the input data is stable at the clock edge of the target clock domain, avoiding data errors caused by clock uncertainty. Clock domain isolation means that the synchronous unit can achieve logical isolation between two clock domains by sampling data using independent flip-flops. Improving system stability means that the synchronous unit can reduce the system instability and data inconsistency caused by cross-clock domain transmission.
[0024] In the related art, functional verification of a synchronization unit is performed by writing targeted test cases. However, this method may result in repeated simulation verification of errors for the same synchronization unit, thereby leading to low verification efficiency of the synchronization unit. In addition, this method cannot always check the input and output signals of the sync cell, and there is a possibility that the input and output signals flip multiple times. Therefore, verification points will be missed, resulting in poor verification accuracy of the synchronization unit.
[0025] To solve the above technical problems, an embodiment of the present application provides a method for verifying a synchronization unit. The method includes: after N test cases perform assertion tests on M synchronization units, obtaining at least one mapping relationship; based on the hierarchical structure corresponding to each target synchronization unit, querying each error type and the number of errors corresponding to each error type for each target synchronization unit in at least one mapping relationship; determining at least one target test case name corresponding to each target synchronization unit based on the number of errors corresponding to each error type; and sending at least one target test case name to the client. Since at least one mapping relationship includes the error types and the number of errors of at least one target synchronization unit with errors, it is possible to determine, based on the error types and the number of errors, at least one target test case with the most error occurrences for each target synchronization unit from multiple test cases, and then send at least one target test case name to the client, enabling the verification personnel to perform waveform simulation verification on the target synchronization unit based on at least one target test case in a targeted manner. At the same time, it avoids the situation where the verification personnel repeatedly simulate and verify errors for the same synchronization unit, shortens the verification time, and improves the verification efficiency.
[0026] The following takes Figure 1 the verification system of the synchronization unit shown as an example to describe the method provided by the embodiment of the present application.
[0027] As Figure 1 shown, Figure 1 is the topological structure diagram of the verification system of the synchronization unit provided by the embodiment of the present application. Figure 1 The verification system 100 of the synchronization unit in [Figure] includes a verification device 101 of the synchronization unit and a client 102.
[0028] The verification device 101 of the synchronization unit in the embodiment of the present application can be any device with communication and computing functions. For example, the verification device 101 of the synchronization unit can be a server, a cloud server, or a virtual machine. The verification device 101 of the synchronization unit can be integrated with a pre-analysis processing module.
[0029] The client 102 can be any device with communication and display functions. The client 102 can provide an input function for the verification personnel. For example, the client 102 can be a handheld device, a vehicle-mounted device, etc.
[0030] Figure 1 The verification system of the synchronization unit shown is only for illustration and not for limiting the technical solutions of this application. Those skilled in the art should understand that in the specific implementation process, the verification system of the synchronization unit may further include more devices, which are not limited.
[0031] An embodiment of this application provides a verification method for a synchronization unit, which is applied to Figure 1 the verification device of the synchronization unit shown, as Figure 2 shown Figure 2 is a schematic flowchart of a verification method for a synchronization unit provided by an embodiment of this application. The verification method for the synchronization unit includes the following steps:
[0032] S201: After performing assertion tests on M synchronization units with N test cases, obtain at least one mapping relationship.
[0033] Wherein, N≥1 and is a positive integer, and M≥1 and is a positive integer.
[0034] Each mapping relationship is a mapping relationship between each test case name and the hierarchical structure corresponding to each target synchronization unit, each error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type.
[0035] Each target synchronization unit is one of at least one target synchronization unit that has errors during the assertion test among the M synchronization units.
[0036] In some alternative embodiments, the verification device of the synchronization unit obtains N simulation logs corresponding to N test cases; traverses each simulation log, extracts the name of each test case corresponding to each simulation log, the error information of each target synchronization unit, where the error information includes the hierarchical structure corresponding to each target synchronization unit, as well as at least one error type corresponding to each target synchronization unit and the number of errors corresponding to each error type; generates at least one mapping relationship according to the name of each test case, the hierarchical structure corresponding to each target synchronization unit, at least one error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type.
[0037] Wherein, each test case is used to trigger at least one synchronization unit to perform an assertion test to obtain each simulation log.
[0038] The hierarchical structure corresponding to each target synchronization unit can also be referred to as the path corresponding to each target synchronization unit.
[0039] In one example, the verification device of the synchronization unit obtains N simulation logs corresponding to N test cases, retrieves each simulation log in sequence, and extracts the information corresponding to each keyword from each simulation log according to at least one keyword, so as to obtain the name of each test case corresponding to each simulation log and the error information of each target synchronization unit.
[0040] Among them, the at least one keyword includes testcase_name, Sync_cell_hire, assertion.*sync_cell_ckn.*fail, Times.
[0041] testcase_name is used to indicate the name of each test case. For example, the test case name is testcase_1.
[0042] Sync_cell_hire is used to indicate the hierarchical structure corresponding to each target synchronization unit. For example, the hierarchical structure is Top_tb.dut...sync_cell_chk1.
[0043] In assertion.*sync_cell_ckn.*fail, “sync_cell_ckn” is used to indicate the error type of each target synchronization unit. For example, the error type is glitch (i.e., glitch error) or stable (input signal stability error due to insufficient stable duration).
[0044] Times is used to indicate the number of errors of each error type. For example, the number of errors is 1. It can be understood that when the verification device of the synchronization unit traverses the first simulation log, since “*fail” is retrieved for the first time, the number of errors is recorded as 1.
[0045] In the embodiments of the present application, at least one mapping relationship can be stored in a hash list of string type. The hash key (key value) of the hash list is a string concatenated by the hierarchical structure, error type, and test case name of each target synchronization unit; the value value is the recorded number of errors. For example, the key value is a field concatenated by “Top_tb.dut...sync_cell_chk1”, “glitch”, and “testcase_1”.
[0046] Optionally, in order to facilitate splitting the key value, the verification device of the synchronization unit can add special characters (for example, the special character is “&&”) between the hierarchical structure and the error type, and between the error type and the test case name.
[0047] It can be understood that when the verification device of the synchronization unit traverses the subsequent simulation log, after retrieving "*fail", it first queries whether there is the same key value in the hash column; if it exists, the value of its value is incremented by 1; if it does not exist, a new hash key value is created again.
[0048] It can be understood that storing at least one mapping relationship in the hash list enables the verification device of the synchronization unit to quickly locate the error information of each target synchronization unit. Compared with traversing the entire data set, the search efficiency is greatly improved. In addition, by concatenating the hierarchical structure, error type, and test case name of the target synchronization unit into a hash key value, a unique identifier is provided for each synchronization unit error information. Ensure that the information of different synchronization units, different error types, and different test cases can be accurately distinguished. When concatenating the key values, special characters are added to facilitate the subsequent splitting of the key values. When specific information such as the hierarchical structure, error type, or test case name of the synchronization unit needs to be obtained, it can be easily split based on the special characters, providing convenience for further data analysis and processing.
[0049] In some optional embodiments, the verification device of the synchronization unit obtains M synchronization units and N test cases included in the design under test; runs N test cases, triggers at least one synchronization unit bound with a configuration file, and verifies the performance of each synchronization unit under different input conditions to obtain N simulation logs corresponding to the N test cases.
[0050] Among them, each synchronization unit is bound with a configuration file (also called a Bind file). The configuration file is used to indicate the binding relationship between each synchronization unit and at least one assertion. Each test case corresponds to each simulation log one by one.
[0051] The design under test (DUT) can be any circuit design including synchronization units.
[0052] In one example, the verification device of the synchronization unit receives a binding request from the client; based on multiple synchronization unit names, obtains multiple synchronization units of the design under test; based on at least one assertion name, binds each synchronization unit with at least one assertion corresponding to the at least one assertion name to obtain a configuration file for each synchronization unit.
[0053] Among them, the binding request carries multiple synchronization unit names and at least one assertion name required for each synchronization unit.
[0054] At least one assertion includes one or more of a glitch test assertion and an input signal stability test assertion. Optionally, at least one assertion may further include an assertion coverage test assertion.
[0055] Among them, the glitch test assertion is used to check whether glitches will occur in signals crossing clock domains of synchronous units.
[0056] The input signal stability test assertion is used to detect whether the stable duration of the input clock of a synchronous unit is greater than or equal to a preset duration. It can be understood that for the input signal stability test assertion, the preset durations corresponding to different DUTs are different, and the input signal stability test assertion can be processed by means of parameter passing to determine the preset durations corresponding to different DUTs. Thus, the reuse of the input signal stability test assertion among multiple DUTs with different requirements can be achieved, avoiding the repeated development of assertions.
[0057] The assertion coverage test assertion is used to detect the proportion of the number of triggered or verified assertions of a synchronous unit in the total number of assertions.
[0058] Exemplarily, as Figure 3 shown, Figure 3 is a schematic diagram for generating a configuration file provided by an embodiment of the present application. In Figure 3 , the input is at least one assertion name and a synchronous unit name, and the verification device of the synchronous unit performs a Bind process on each synchronous unit and at least one assertion corresponding to at least one assertion name based on the at least one assertion name, and the output is a Bind file.
[0059] In some optional embodiments, the verification device of the synchronous unit obtains a filtering file; searches whether there is at least one error type in at least one error type of each target synchronous unit that is consistent with any one of at least one allowed error type; if so, deletes at least one first error type from the at least one error type to obtain at least one second error type of each target synchronous unit; generates at least one mapping relationship according to at least one second error type of each target synchronous unit, the number of errors corresponding to each second error type, each test case name, and the hierarchical structure corresponding to each target synchronous unit.
[0060] Among them, the filtering file includes at least one allowed error type, and at least one preset hierarchical structure corresponding to at least one target synchronous unit corresponding to each allowed error type.
[0061] The allowed error type may be an error type of an error of a synchronous unit that can be tolerated. For example, the allowed error type may be an error of missing sampling of a relatively static cross-clock signal of a synchronous unit.
[0062] As Figure 4 shown, Figure 4 is a schematic diagram for generating a document where at least one mapping relationship provided by an embodiment of the present application is located. In Figure 4Among them, the input file is the path of the regression folder where multiple simulation logs are located and the filtering file. The verification device of the synchronization unit pre-analyzes and processes the multiple simulation logs and the filtering file, and the output file is the document where at least one mapping relationship is located. Among them, the pre-analysis process is the process by which the verification device of the synchronization unit generates at least one mapping relationship, which will not be elaborated here.
[0063] Optionally, the verification device of the synchronization unit adds the hierarchical structure of the synchronization unit corresponding to each first error type in at least one first error type to the filtering file, and uses this filtering file as the input file for the next pre-analysis process.
[0064] S202: Based on the hierarchical structure corresponding to each target synchronization unit, query each error type corresponding to each target synchronization unit and the number of errors corresponding to each error type in at least one mapping relationship.
[0065] S203: Based on the number of errors corresponding to each error type, determine at least one target test case name corresponding to each target synchronization unit.
[0066] Among them, each target test case name is the name of the test case that triggers each target synchronization unit to perform an assertion test and has each error type, and the number of errors corresponding to each error type is the most.
[0067] S204: Send at least one target test case name to the client.
[0068] It can be understood that after the client receives at least one target test case name, the verification personnel can run the simulation waveform for each target test case according to the at least one target test case corresponding to the at least one target test case name, and check whether there are unexpected glitches in each target synchronization unit, and whether the stable duration of the input signal of each synchronization unit is greater than or equal to the preset duration.
[0069] If the verification personnel detect that there are unexpected glitches in the target synchronization unit, or the stable duration of the input signal of the synchronization unit is less than the preset duration, the verification personnel can judge whether there is a design defect (bug) in the target synchronization unit based on the result of running the simulation waveform. If it is determined that there is a design bug in the target synchronization unit, the verification personnel repair the target synchronization unit.
[0070] In some alternative embodiments, after at least one target synchronization unit is repaired, the verification device of the synchronization unit runs at least one test case corresponding to at least one target test case name, triggers at least one target synchronization unit bound with a configuration file, verifies the performance of each target synchronization unit under different input conditions, and obtains at least one first simulation log corresponding to at least one target test case; if there is no error message in at least one first simulation log, it is determined that at least one target synchronization unit is successfully repaired.
[0071] It can be understood that when there is no error message in at least one first simulation log, the verification device of the synchronization unit determines that at least one target synchronization unit is successfully repaired. At this time, when the verification device of the synchronization unit performs pre-analysis processing again, at least one obtained mapping relationship is empty, which indicates that the analysis of the covered synchronization units is completed.
[0072] In one example, the verification device of the synchronization unit traverses N simulation logs and at least one first simulation log, extracts the test information corresponding to each of the M synchronization units; based on the test information corresponding to each synchronization unit, determines the test coverage rate of the M synchronization units; if the test coverage rate meets the preset condition, it is determined that the verification of the M synchronization units is completed.
[0073] Among them, the test information is used to indicate whether each synchronization unit performs an assertion test corresponding to at least one assertion.
[0074] The preset condition may be that the test coverage rate reaches 100%.
[0075] It can be understood that when the test coverage rate does not reach 100%, it means that for the synchronization units that have not flipped (i.e., the synchronization units that have not triggered the assertion test), the verification personnel need to add test cases for assertion testing. When the test coverage rate reaches 100% and at least one mapping relationship is empty, it proves that all synchronization units have been triggered for assertion testing and all have been verified. Based on the assertion coverage rate, the accuracy of the synchronization units can be verified more completely.
[0076] Based on the above Figure 2 According to the method shown above, after N test cases perform assertion testing on M synchronization units, the verification module of the synchronization unit obtains at least one mapping relationship; based on the hierarchical structure corresponding to each target synchronization unit, queries each error type and the number of errors corresponding to each error type corresponding to each target synchronization unit in at least one mapping relationship; based on the number of errors corresponding to each error type, determines at least one target test case name corresponding to each target synchronization unit; and sends at least one target test case name to the client.
[0077] Since at least one mapping relationship can be obtained, at least one target synchronization unit that reports an error can be determined. Also, based on the error type and the number of errors, at least one target test case with the most error occurrences can be determined for each target synchronization unit from multiple test cases. Then, the names of at least one target test case are sent to the client, enabling the verification personnel to perform waveform simulation verification on the target synchronization unit based on at least one target test case in a targeted manner. At the same time, it avoids the situation where the verification personnel repeatedly simulate and verify the same synchronization unit error, making the analysis of the synchronization unit more targeted, shortening the verification time, improving the verification efficiency, and saving labor costs.
[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.
[0079] An embodiment of the present application also provides a verification device for a synchronization unit, as Figure 5 shown Figure 5 is a structural block diagram of a verification device for a synchronization unit provided by an embodiment of the present application; the device includes: a transceiver module 501, configured to obtain at least one mapping relationship after N test cases perform assertion tests on M synchronization units. Each mapping relationship is a mapping relationship between each test case name and the hierarchical structure corresponding to each target synchronization unit, each error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type. Each target synchronization unit is one of at least one target synchronization unit that has an error during the assertion test among the M synchronization units, N≥1 and is a positive integer, and M≥1 and is a positive integer.
[0080] A processing module 502, configured to query each error type corresponding to each target synchronization unit and the number of errors corresponding to each error type in at least one mapping relationship based on the hierarchical structure corresponding to each target synchronization unit.
[0081] The processing module 502 is further configured to determine at least one target test case name corresponding to each target synchronization unit based on the number of errors corresponding to each error type. Each target test case name is the name of the test case that triggers each error type of error when performing an assertion test on each target synchronization unit, and the number of errors corresponding to each error type is the most.
[0082] The transceiver module is further configured to send at least one target test case name to the client.
[0083] In some alternative embodiments, the transceiver module 501 is specifically configured to obtain N simulation logs corresponding to N test cases, where each test case is used to trigger at least one synchronization unit to perform an assertion test to obtain each simulation log; traverse each simulation log, extract the name of each test case corresponding to each simulation log, and the error information of each target synchronization unit, where the error information includes the hierarchical structure corresponding to each target synchronization unit, at least one error type of each target synchronization unit, and the number of errors corresponding to each error type; generate at least one mapping relationship according to the name of each test case, the hierarchical structure corresponding to each target synchronization unit, at least one error type of each target synchronization unit, and the number of errors corresponding to each error type.
[0084] In some alternative embodiments, the transceiver module 501 is further specifically configured to obtain a filtering file, where the filtering file includes at least one allowed error type and at least one preset hierarchical structure corresponding to at least one target synchronization unit corresponding to each allowed error type; check whether there is at least one error type in at least one error type of each target synchronization unit that is the same as any one of the at least one allowed error types; if so, delete at least one first error type from the at least one error type to obtain at least one second error type of each target synchronization unit; generate at least one mapping relationship according to at least one second error type of each target synchronization unit, the number of errors corresponding to each second error type, the name of each test case, and the hierarchical structure corresponding to each target synchronization unit.
[0085] In some alternative embodiments, the transceiver module 501 is further configured to obtain M synchronization units and N test cases included in the design under test, where each synchronization unit is bound with a configuration file, and the configuration file is used to indicate the binding relationship between each synchronization unit and at least one assertion; the processing module 502 is further configured to run N test cases to trigger at least one synchronization unit bound with a configuration file to verify the performance of each synchronization unit under different input conditions, and obtain N simulation logs corresponding to N test cases, where each test case corresponds to each simulation log one by one.
[0086] In some alternative embodiments, the transceiver module 501 is further configured to receive a binding request from a client, where the binding request carries multiple synchronization unit names and at least one assertion name required for each synchronization unit; the transceiver module 501 is further configured to obtain multiple synchronization units of the design under test based on the multiple synchronization unit names; the processing module 502 is further configured to bind each synchronization unit with at least one assertion corresponding to at least one assertion name based on the at least one assertion name to obtain a configuration file for each synchronization unit, and the at least one assertion includes one or more of a glitch test assertion and an input signal stability test assertion.
[0087] In some alternative embodiments, the processing module 502 is further configured to, after at least one target synchronization unit is repaired, run at least one test case corresponding to at least one target test case name, trigger at least one target synchronization unit bound with a configuration file, verify the performance of each target synchronization unit under different input conditions, and obtain at least one first simulation log corresponding to at least one target test case; if there is no error message in at least one first simulation log, it is determined that at least one target synchronization unit is successfully repaired.
[0088] In some alternative embodiments, the processing module 502 is further configured to traverse N simulation logs and at least one first simulation log, extract test information corresponding to each of the M synchronization units, where the test information is used to indicate whether each synchronization unit performs an assertion test corresponding to at least one assertion; based on the test information corresponding to each synchronization unit, determine the test coverage rate of the M synchronization units; if the test coverage rate meets a preset condition, it is determined that the verification of the M synchronization units ends.
[0089] For the description of the features in the embodiments corresponding to the verification device of the synchronization unit, reference may be made to the relevant description in the embodiments corresponding to the verification method of the synchronization unit, which will not be elaborated here one by one.
[0090] An embodiment of the present application further provides an electronic device, such as Figure 6 shown Figure 6 is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application; the electronic device includes a processor 10 and a memory 20, a computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above embodiments of the verification method of the synchronization unit.
[0091] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any of the above embodiments of the verification method of the synchronization unit when running.
[0092] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs, and other media that can store computer programs.
[0093] An embodiment of the present application further provides a computer program product, the above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the verification method of the synchronization unit are implemented.
[0094] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the verification method of the synchronization unit are implemented.
[0095] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0096] The above has introduced in detail a verification method, device, electronic device, and storage medium of a synchronization unit provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A verification method for a synchronization unit, characterized in that, The method includes: After performing assertion tests on M synchronization units with N test cases, obtaining at least one mapping relationship, where each mapping relationship is a mapping relationship between each test case name and the hierarchical structure corresponding to each target synchronization unit, each error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type. Each target synchronization unit is one of at least one target synchronization unit that has an error during the assertion test process among the M synchronization units, N≥1 and is a positive integer, M≥1 and is a positive integer; Based on the hierarchical structure corresponding to each target synchronization unit, querying each error type corresponding to each target synchronization unit and the number of errors corresponding to each error type in the at least one mapping relationship; Based on the number of errors corresponding to each error type, determining at least one target test case name corresponding to each target synchronization unit, where each target test case name is the name of the test case that triggers each target synchronization unit to have an error of each error type during the assertion test, and the number of errors corresponding to each error type is the largest; Sending the at least one target test case name to the client.
2. The method according to claim 1, characterized in that, The obtaining of at least one mapping relationship after performing assertion tests on M synchronization units with N test cases includes: Obtaining N simulation logs corresponding to the N test cases, where each test case is used to trigger at least one of the synchronization units to perform an assertion test, and obtaining each simulation log; Traversing each simulation log, and extracting each test case name corresponding to each simulation log and the error information of each target synchronization unit. The error information includes the hierarchical structure corresponding to each target synchronization unit, and at least one error type corresponding to each target synchronization unit and the number of errors corresponding to each error type; Generating the at least one mapping relationship according to each test case name, the hierarchical structure corresponding to each target synchronization unit, at least one error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type.
3. The method according to claim 2, wherein The generating of the at least one mapping relationship according to each test case name, the hierarchical structure corresponding to each target synchronization unit, at least one error type corresponding to each target synchronization unit, and the number of errors corresponding to each error type includes: Obtaining a filtering file, where the filtering file includes at least one allowed error type and at least one preset hierarchical structure corresponding to at least one target synchronization unit corresponding to each allowed error type; Searching whether there is at least one error type in at least one error type corresponding to each target synchronization unit that is the same as any one of the at least one allowed error types; If so, deleting the at least one first error type from the at least one error type to obtain at least one second error type corresponding to each target synchronization unit; Generate the at least one mapping relationship according to the at least one second error type of each of the target synchronization units, the number of errors corresponding to each of the second error types, each of the test case names, and the hierarchy corresponding to each of the target synchronization units.
4. The method according to claim 3, wherein The method further includes: Obtain the M synchronization units and the N test cases included in the design under test, and a configuration file is bound to each of the synchronization units, and the configuration file is used to indicate the binding relationship between each of the synchronization units and at least one assertion; Run the N test cases to trigger the at least one synchronization unit bound with the configuration file, and verify the performance of each of the synchronization units under different input conditions to obtain N simulation logs corresponding to the N test cases, and each of the test cases corresponds to each of the simulation logs one by one.
5. The method according to claim 4, wherein The method further includes: Receive a binding request from the client, where the binding request carries a plurality of synchronization unit names and at least one assertion name required for each of the synchronization units; Based on the plurality of synchronization unit names, obtain the plurality of synchronization units of the design under test; Based on the at least one assertion name, bind each of the synchronization units to the at least one assertion corresponding to the at least one assertion name to obtain the configuration file of each synchronization unit, and the at least one assertion includes one or more of a glitch test assertion and an input signal stability test assertion.
6. The method according to claim 5, characterized in that, The method further includes: After the at least one target synchronization unit is repaired, run at least one test case corresponding to the at least one target test case name, trigger the at least one target synchronization unit bound with the configuration file, and verify the performance of each of the target synchronization units under different input conditions to obtain at least one first simulation log corresponding to the at least one target test case; If the error message does not exist in the at least one first simulation log, determine that the at least one target synchronization unit is successfully repaired.
7. The method according to claim 6, wherein The method further includes: Traverse the N simulation logs and the at least one first simulation log, extract the test information corresponding to each of the M synchronization units, and the test information is used to indicate whether each of the synchronization units performs the assertion test corresponding to the at least one assertion; based on the test information corresponding to each of the synchronization units, determine the test coverage rate of the M synchronization units; If the test coverage rate meets the preset condition, determine that the verification of the M synchronization units is completed.
8. A verification device for a synchronization unit, characterized in that, The verification device for the synchronization unit includes: A transceiver module, configured to obtain at least one mapping relationship after the N test cases perform assertion tests on the M synchronization units, and each of the mapping relationships is a mapping relationship between each test case name and the hierarchy corresponding to each target synchronization unit, each error type corresponding to each of the target synchronization units, and the number of errors corresponding to each of the error types, and each of the target synchronization units is one of at least one target synchronization unit that has an error during the assertion test among the M synchronization units, N≥1 and is a positive integer, M≥1 and is a positive integer; A processing module, configured to query, based on the hierarchical structure corresponding to each of the target synchronization units, each of the error types corresponding to each of the target synchronization units and the number of errors corresponding to each of the error types in each of the at least one mapping relationship; The processing module is further configured to determine, based on the number of errors corresponding to each of the error types, at least one target test case name corresponding to each of the target synchronization units, where each target test case name is the name of a test case that triggers an assertion test for each of the target synchronization units to have an error of each of the error types, and the number of errors corresponding to each of the error types is the largest; The transceiver module is further configured to send the at least one target test case name to the client.
9. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the steps of the verification method of the synchronization unit according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the verification method of the synchronization unit according to any one of claims 1 to 7 when executed by a processor.