Single event upset resistant self-recovery in-memory computing unit design method based on SRAM (Static Random Access Memory)

Abstract

The invention discloses a single event upset resistant self-recovery in-memory computing unit design method based on an SRAM (Static Random Access Memory), and relates to a single event upset resistant self-recovery in-memory computing unit design method. The invention aims to solve the problems that the area and the power consumption are usually increased, the stability is difficult to consider and the high-energy-efficiency design of the in-memory computing architecture cannot be met in the existing radiation hardening design. On the premise of guaranteeing high energy efficiency, through circuit structure and layout design and optimization, comprehensive improvement of single event upset resistance, self-recovery capability and stability is achieved, and the design requirement for high stability of a computing architecture in a space memory is met. The invention belongs to the technical field of integrated circuit design.

Description

Technical Field

[0001] The present invention relates to a design method for an anti-single event upset self-recovery in-memory computing unit, belonging to the technical field of integrated circuit design. Background Art

[0002] The in-memory computing architecture provides transformative support for artificial intelligence applications such as space on-orbit intelligent processing and autonomous decision-making by eliminating the data transmission barrier between memory and processing units. The SRAM-based in-memory computing architecture, with its high process maturity, fast computing speed, high stability, etc., can efficiently support the deployment of diverse artificial intelligence models such as convolutional neural networks (CNNs) and spiking neural networks (SNNs). However, the single event effect (SEE) caused by radiation particles in the space environment can cause the weight parameters stored in the in-memory computing architecture to flip, that is, single event upset (SEU) occurs, seriously threatening the reliability of the in-memory computing circuit. To improve the computing power, multiple word lines are turned on in the computing mode of the in-memory computing circuit, resulting in the problem of read disturb write, reducing the stability of the stored data. Some existing radiation-hardened SRAM cells do not have the ability of soft error self-recovery, which may cause the problem of error accumulation. Moreover, the existing radiation-hardened designs usually increase the area and power consumption, and it is difficult to balance stability, not meeting the high energy efficiency design goal of the in-memory computing architecture. Therefore, there is an urgent need for a radiation-hardened design method for the in-memory computing architecture. Under the premise of ensuring high energy efficiency, through circuit structure and layout design and optimization, the comprehensive improvement of anti-single event upset, self-recovery ability and stability can be realized to meet the design requirements of high stability of the space in-memory computing architecture. Summary of the Invention

[0003] In order to solve the problem that the existing radiation-hardened designs usually increase the area and power consumption, and it is difficult to balance stability and cannot meet the high energy efficiency design of the in-memory computing architecture, the present invention further proposes a design method for an anti-single event upset self-recovery in-memory computing unit based on SRAM.

[0004] The technical solutions adopted by the present invention to solve the above problems are as follows: The steps of the present invention include:

[0005] Step 1: Decouple the read and write ports, separate the read and write ports of the classical SRAM cell, and achieve physical isolation of the read and write paths through independent bit lines and control signals;

[0006] Step 2: According to the logic operation types supported by in-memory computing, use the NMOS logic circuit design method to design the topology structure of the read port of the unit;

[0007] Step 3: Construct a pull-up network using stacked P-type transistors;

[0008] Step 4: Add redundant nodes in the storage unit to back up the stored data;

[0009] Step 5: Construct a feedback network between the storage nodes and the redundant nodes to ensure that data can be written from the storage nodes to the redundant nodes, and the redundant nodes can correct the negative flips that occur in the storage node data;

[0010] Step 6: Analyze the sensitive node pairs in the in-memory computing unit;

[0011] Step 7: Set the sizes of the transistors in the unit according to the design principle of the SRAM cell;

[0012] Step 8: Introduce source isolation technology in the pull-up network layout of the storage node to suppress the positive SEU that occurs in the storage node;

[0013] Step 9: Design the layout of the in-memory computing unit by separating the sensitive node pairs and arranging the switching transistors in an interleaved manner;

[0014] Step 10: Verify the single-event upset resistance of the in-memory computing unit;

[0015] Step 11: Determine whether the anti-radiation design index requirements are met. If so, proceed to Step 12; if not, adjust the width of the shallow trench isolation of the source isolation technology and the spacing of the sensitive node pairs, and re-execute Steps 9 to 11;

[0016] Step 12: Evaluate the design indicators;

[0017] Step 13: Determine whether the design indicators meet the design constraints. If so, execute Step 14; if not, adjust the transistor sizes in the unit and re-execute Steps 7 to 13;

[0018] Step 14: Obtain the in-memory computing unit with single-event upset self-recovery and obtain the required files.

[0019] Further, the NMOS logic circuit design method in Step 2 refers to implementing specific logic functions by connecting NMOS transistors in series / parallel.

[0020] Further, the stacked P-type transistors are in a series P-type transistor structure.

[0021] Further, the design principle of the SRAM cell in Step 7 refers to the design principles related to the read, write operations, and static noise margin of the SRAM cell.

[0022] Further, the source isolation technology in step 8 is a layout-level reinforcement technology. By introducing shallow trench isolation between the layouts of the transistors in the pull-up network, the parasitic bipolar transistor structure is blocked, the forward SEU is suppressed, and the '0' to '1' flip of the storage node is avoided.

[0023] Further, the separation of sensitive node pairs in step 9 means that each node in the sensitive node pair is as far away as possible on the layout, using a diagonal layout or a sub-region arrangement to minimize the charge sharing effect.

[0024] The staggered arrangement of switch transistors means that the on-state and off-state transistors are staggered to reduce the charge collected by the off-state transistors.

[0025] Further, the design metrics in step 12 include area, power consumption, and static noise margin.

[0026] The beneficial effects of the present invention are as follows:

[0027] 1. The present invention can significantly enhance the single-event upset resistance of the in-memory computing unit. By introducing source isolation technology in the pull-up network layout of the storage node, the forward SEU of the storage node is suppressed, effectively improving the single-event upset resistance of the in-memory computing unit.

[0028] 2. The present invention has a soft error self-recovery function. By adding redundant nodes and constructing a feedback network between the storage node and the redundant nodes, it is ensured that data can be written from the storage node to the redundant nodes, and the redundant nodes can correct the negative flips of the data in the storage node. Combining multiple layout-level reinforcement technologies, self-recovery of soft errors can be achieved without the intervention of an external recovery mechanism.

[0029] 3. The present invention adopts a read-write decoupled design. By physically isolating the read and write paths through independent bit lines and control signals, the problem of read interference with write is effectively solved, and the static noise margin of the unit can be significantly improved, enhancing the flexibility and reliability of the design.

[0030] 4. The present invention has good process compatibility and can be implemented using standard CMOS processes, seamlessly compatible with existing SRAM in-memory computing architectures, and supporting the high-performance deployment of models such as convolutional neural networks and spiking neural networks.

[0031] 5. The present invention uses stacked P-type transistors to construct the pull-up network, effectively reducing the static power consumption of the in-memory computing unit. Description of the Drawings

[0032] Figure 1 is a flowchart of the design method for a single-event upset self-recovery in-memory computing unit based on SRAM.

[0033] Figure 2Schematic diagram of the design method of a single - event - upset - resistant self - recovering in - memory computing unit;

[0034] Figure 3 Schematic diagram of the pull - up and pull - down network structure of the storage node;

[0035] Figure 4 Schematic diagram of the source isolation technology;

[0036] Figure 5 Schematic diagram of the separation of sensitive nodes and the staggered arrangement of switching transistors. Specific implementation manners

[0037] Specific implementation manner 1: As Figure 1 shown, a design method of a single - event - upset - resistant self - recovering in - memory computing unit based on SRAM, the specific steps include:

[0038] Step 1: Decouple the read and write ports of the classical SRAM cell. The write path uses dedicated bit lines and word lines, and the read path uses independent bit lines and word lines. The read and write data pass through different ports to solve the problem of read interfering with write, which is beneficial to improving the static noise margin of the cell;

[0039] Among them, the write port is responsible for writing new weight data, and the read port is responsible for reading out the logical operation result;

[0040] Step 2: According to the type of logical operations supported by the in - memory computing unit, adopt the NMOS logic circuit design method, and use N - type transistors to implement the required logical functions, and design the topological structure of the unit read port;

[0041] Step 3: Construct a pull - up network using stacked P - type transistors;

[0042] As Figure 3 shown, adopt a double - PMOS series structure, connect the first PMOS transistor 301 and the second PMOS transistor 302 in series. The source of the first PMOS transistor 301 is connected to VDD, and the drain of the second PMOS transistor 302 is connected to the storage node;

[0043] Step 4: Add redundant nodes to realize the backup of the data of the storage node. The number of redundant nodes is set according to the process size and anti - radiation performance requirements adopted;

[0044] Step 5: Construct a feedback network between the storage node and the redundant nodes to ensure that data can be written from the storage node to the redundant nodes, and the redundant nodes can correct the negative flips that occur in the data of the storage node;

[0045] Among them, the state of the flipped node is restored by other nodes through the feedback network to realize the soft - error self - recovery function;

[0046] Step 6: Traverse the cases where all node pairs flip simultaneously and analyze the sensitive node pairs in all in-memory computing units;

[0047] Step 7: Set the sizes of the transistors within the unit according to the design principle of the SRAM cell;

[0048] Among them, for the write operation, it is necessary to ensure that the storage node and the redundant node can be correctly written with data, and a smaller unit pull-up ratio is selected, that is, the size ratio of the pull-up transistor to the write port access transistor; for the read operation, considering the static noise margin, area, and power consumption comprehensively, a unit ratio of about 2 is selected, that is, the size ratio of the pull-down transistor to the read port access transistor;

[0049] Step 8: Introduce source isolation technology in the pull-up network layout of the storage node to suppress the positive SEU of the storage node;

[0050] Among them, the pull-up network layout of the storage node does not adopt the way of sharing the active region, but uses shallow trench isolation to divide the pull-up transistors;

[0051] As Figure 4 shown, the source 701 of one of the series-connected pull-up transistors is connected to VDD, its drain 703 and the source 704 of another transistor are separated by a shallow trench isolation 705, and the drain 707 of the zero-one transistor is connected to the storage node; the wider the width of the shallow trench isolation, that is, the greater the physical distance between the pull-up network transistors, the farther the distance between the emitter and collector of the parasitic bipolar transistor structure, and the stronger the ability to suppress the positive SEU, but it will increase the area overhead; therefore, the lowest spacing allowed by the process layout design rules used is selected during design;

[0052] Step 9: Design the layout of the in-memory computing unit by adopting the method of separating sensitive node pairs and staggering switch transistors;

[0053] Among them, for the sensitive node pair, during the layout design, make its sensitive nodes as far away as possible on the layout, preferably in a diagonal arrangement; adopt the way of staggering on-state transistors and off-state transistors. While achieving the purpose of separating the sensitive transistors, it is beneficial to reduce the area overhead of the unit and the collected charge of the sensitive nodes;

[0054] As Figure 5 shown, between the P-wells 901 and 903 is an N-well structure. The off-state N-type transistors 904 and 910 in the sensitive node pair are arranged diagonally on the layout. The off-state transistors 904, 906 and the on-state transistors 905, 907 are staggered, and the off-state transistor 908 and the on-state transistors 907 and 909 are staggered;

[0055] Step 10: Verify the single-event upset resistance of the in-memory computing unit;

[0056] Among them, due to the adoption of layout-level hardening technology, semiconductor processes and device simulation software TCAD or other professional software are used for verification to verify the ability of the verification unit to resist single-event upsets.

[0057] Step 11: Determine whether the radiation resistance of the in-memory computing unit meets the design requirements; if it meets the design requirements, execute Step 12; if it does not meet the design requirements, adjust the width of the shallow trench isolation and the spacing of the sensitive node pairs, and re-execute Steps 9 to 11.

[0058] Step 12: Evaluate the various design indicators of the in-memory computing unit, including area, power consumption, read / write latency, and static noise margin.

[0059] Step 13: Determine whether the various design indicators meet the design constraints; if they meet the design constraints, execute Step 14; if they do not meet the design constraints, adjust the dimensions of the transistors in the unit, and re-execute Steps 7 to 13.

[0060] Step 14: Obtain the in-memory computing unit with single-event upset self-recovery, and save all relevant files required.

[0061] As Figure 2 shown, the structure of the in-memory computing unit with single-event upset self-recovery includes a write port 1, a read port 2, a storage node 3, a redundant node 4, a feedback network 5, a feedback network 6, and a source isolation technology 7.

[0062] The above is only a preferred embodiment of the present invention, and it does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to it as equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention and is based on the technical essence of the present invention, any simple modification, equivalent replacement, and improvement made to the above embodiments still fall within the protection scope of the technical solution of the present invention.

Claims

1. A design method for a single-event upset self-recovery in-memory computing unit based on SRAM, characterized in that, The specific steps include: Step 1: Decouple the read and write ports, separate the read and write ports of the classical SRAM cell, and physically isolate the read and write paths through independent bit lines and control signals; Step 2: According to the logical operation types supported by in-memory computing, adopt the NMOS logic circuit design method to design the topology structure of the read port of the cell; Step 3: Construct the pull-up network using stacked P-type transistors; Step 4: Add redundant nodes in the storage cell to back up the stored data; Step 5: Construct a feedback network between the storage node and the redundant node to ensure that data can be written from the storage node to the redundant node, and the redundant node can correct the negative flip of the data in the storage node; Step 6: Analyze the sensitive node pairs in the in-memory computing unit; Step 7: According to the design principle of the SRAM cell, set the sizes of the transistors in the cell; Step 8: Introduce the source isolation technology in the layout of the pull-up network of the storage node to suppress the positive SEU of the storage node; Step 9: Design the layout of the in-memory computing unit by separating the sensitive node pairs and arranging the switching transistors in a staggered manner; Step 10: Verify the single-event upset resistance of the in-memory computing unit; Step 11: Judge whether the anti-radiation design index requirements are met. If they are met, go to Step 12; if not, adjust the width of the shallow trench isolation of the source isolation technology and the spacing of the sensitive node pairs, and re-execute Steps 9 to 11; Step 12: Evaluate various design indexes; Step 13: Judge whether various design indexes meet the design constraints. If they are met, execute Step 14; if not, adjust the sizes of the transistors in the cell and re-execute Steps 7 to 13; Step 14: Obtain the in-memory computing unit with single-event upset self-recovery, and obtain the required various documents.

2. A design method for a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that The NMOS logic circuit design method in Step 2 refers to realizing specific logic functions by series / parallel NMOS transistors.

3. A design method for a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that The stacked P-type transistor is a series P-type transistor structure.

4. A design method for a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that, The design principle of the SRAM cell in Step 7 refers to the design principles related to the read, write operations and static noise margin of the SRAM cell.

5. A design method for a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that, The source isolation technology in Step 8 is a layout-level hardening technology. By introducing shallow trench isolation between the layouts of the transistors in the pull-up network, the parasitic bipolar transistor structure is blocked, the positive SEU is suppressed, and the flip of the storage node from '0' to '1' is avoided.

6. A design method of a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that The separation of sensitive node pairs in Step 9 means that the nodes in the sensitive node pairs are arranged as far away from each other as possible on the layout, adopting a diagonal layout or a zonal arrangement to minimize the charge sharing effect; The staggered arrangement of the switching transistors means that the on-state and off-state transistors are arranged in a staggered manner to reduce the charge collection of the off-state transistors.

7. A design method of a single-event upset self-recovery in-memory computing unit based on SRAM according to claim 1, characterized in that The design indexes in Step 12 include area, power consumption, and static noise margin.

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