RISC-V-based ultrahigh frequency RFID reader-writer digital processing circuit

Abstract

The invention discloses an ultrahigh frequency RFID reader-writer digital processing circuit based on RISC-V. The ultrahigh frequency RFID reader-writer digital processing circuit can be applied to the technical field of radio frequency. According to the application, the processing module, the memory module and the ultrahigh frequency read-write data module are arranged, the controller core constructed based on the RISC-V architecture is arranged in the processing module, and then the processing module, the memory module and the ultrahigh frequency read-write data module are tightly coupled, so that the integration level of the reader-writer can be effectively improved; the area of the reader-writer is reduced, then the interaction process of the ultrahigh-frequency read-write data module and the controller core is managed in a coordinated mode through the bus matrix, and after the controller core receives an external control instruction sent by an upper computer, the label data reading process of the ultrahigh-frequency read-write data module is controlled according to the external control instruction. Therefore, the characteristics of the RISC-V architecture can be utilized, the manufacturing cost is reduced, and the area of the reader-writer is further reduced.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and particularly to a digital processing circuit of an ultra-high frequency RFID reader / writer based on RISC-V. Background Art

[0002] In related technologies, ultra-high frequency RFID technology is an automatic identification technology that uses wireless communication of radio frequency signals to achieve automatic identification of targets. The working principle of ultra-high frequency is to use an electronic tag that can receive and transmit radio waves to store information. The electronic tag and the reader use electromagnetic induction coupling energy for non-contact two-way communication to achieve identification of stored information and data exchange. Currently, the corresponding devices of ultra-high frequency RFID readers / writers have problems such as low integration and high cost.

[0003] In summary, the technical problems existing in related technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a digital processing circuit of an ultra-high frequency RFID reader / writer based on RISC-V, which can effectively improve the integration of the reader / writer and reduce the manufacturing cost.

[0005] To achieve the above object, the embodiments of this application propose a digital processing circuit of an ultra-high frequency RFID reader / writer based on RISC-V, and the digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V includes:

[0006] A processing module, where the processing module includes a controller core, and the controller core is constructed based on the RISC-V architecture;

[0007] A memory module, where the memory module is used to cooperate with the processing module for data storage;

[0008] An ultra-high frequency RFID data reading / writing module, and the interaction process between the ultra-high frequency RFID data reading / writing module and the controller core is coordinated and managed through a bus matrix;

[0009] Wherein, the processing module, the memory module, and the ultra-high frequency RFID data reading / writing module are tightly coupled; the controller core is used to receive external control instructions sent by a host computer, and control the tag data reading process of the ultra-high frequency RFID data reading / writing module according to the external control instructions.

[0010] In some embodiments, the controller core includes an instruction fetch module, a decoding module, an execution module, a memory access module, and a write-back module; an output end of the instruction fetch module is connected to an input end of the decoding module, an output end of the decoding module is connected to a first input end of the execution module, and a first output end of the execution module is connected to an input end of the memory access module; a second output end of the execution module is connected to an input end of the instruction fetch module for branch prediction calibration; a first output end of the memory access module is connected to an input end of the write-back module; an output end of the write-back module is respectively connected to a second input end of the execution module and an interaction end of the memory access module.

[0011] In some embodiments, a multiplier and a divider are integrated in the execution module; the controller core adopts a 32-bit instruction set, and the 32-bit instruction set includes a basic integer instruction set and a multiplication and division extension instruction set.

[0012] In some embodiments, the multiplier includes a Wallace multiplier based on Booth encoding.

[0013] In some embodiments, the controller core further includes an interrupt module, and the interrupt module is used for software terminal control and hardware clock control.

[0014] In some embodiments, the bus matrix integrates a bus bridge conversion circuit and has a built-in priority arbitration mechanism; the priority arbitration mechanism is used to adjust the data interaction sequence and resource access rights between the controller core and the peripherals.

[0015] In some embodiments, the ultra-high frequency read and write data module includes a transmission link and a reception link;

[0016] The transmission link includes a parallel-to-serial conversion module, a first verification module, and an encoding module. An input end of the parallel-to-serial conversion module is connected to an output end of the processing module, an output end of the parallel-to-serial conversion module is connected to an input end of the first verification module, an output end of the first verification module is connected to an input end of the encoding module, and an output end of the encoding module is used to connect to an external radio frequency read and write module, and the external radio frequency read and write module reads application data of the ultra-high frequency electronic tag;

[0017] The reception link includes a serial-to-parallel conversion module, a second verification module, and a decoding module. An input end of the decoding module is used to receive the application data of the external radio frequency read and write module, an output end of the decoding module is connected to an input end of the second verification module, an output end of the second verification module is connected to an input end of the serial-to-parallel conversion module, and an output end of the serial-to-parallel conversion module is connected to an input end of the processing module.

[0018] In some embodiments, the first verification module includes a CRC-16 verification module or a CRC-5 verification module; after reading the control signal from the peripheral register, the encoding module determines the working state of the CRC-16 verification module or the CRC-5 verification module according to the control signal.

[0019] In some embodiments, the decoding module includes an FM0 decoder or a Miller decoder; the FM0 decoder decodes according to the first three bits of the received data; the Miller decoder sets the count of the pilot tone in the received data according to the Miller subcarrier in the receiving link, and when the pilot tone reaches the preset count requirement, removes the Miller subcarrier in the received signal according to the locally generated Miller subcarrier to restore the Miller baseband coding, and decodes the restored Miller baseband coding using the decoding table.

[0020] In some embodiments, the memory module includes an SRAM module, an SDRAM module, or a ROM module.

[0021] The embodiments of the present application have at least the following beneficial effects: The present application provides a digital processing circuit for a UHF RFID reader / writer based on RISC-V. This solution sets a processing module, a memory module, and a UHF read / write data module, and sets a controller core constructed based on the RISC-V architecture in the processing module. Then, the processing module, the memory module, and the UHF read / write data module are tightly coupled, so as to effectively improve the integration of the reader / writer and reduce the area of the reader / writer. Then, the bus matrix is used to coordinate and manage the interaction process between the UHF read / write data module and the controller core. After the controller core receives the external control instruction sent by the host computer, it controls the tag data reading process of the UHF read / write data module according to the external control instruction, so as to utilize the characteristics of the RISC-V architecture to reduce the manufacturing cost and further reduce the area of the reader / writer. Description of the Drawings

[0022] Figure 1 is a block diagram of the digital processing circuit of the UHF RFID reader / writer based on RISC-V provided by the embodiments of the present application;

[0023] Figure 2 is a schematic diagram of the overall architecture of the controller core provided by the embodiments of the present application;

[0024] Figure 3 is a schematic diagram of the bus interaction of the digital processing circuit of the UHF RFID reader / writer based on RISC-V provided by the embodiments of the present application;

[0025] Figure 4 is a schematic diagram of the module of the UHF read / write data module provided by the embodiments of the present application. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods that are consistent with some aspects of the embodiments of the present application.

[0027] It can be understood that the terms "first", "second", etc. used in the present application may be used in this article to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information. Similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0028] The terms "at least one", "a plurality of", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, a plurality includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0030] In the related art, the ultra-high frequency RFID technology is an automatic identification technology, which uses the wireless communication of radio frequency signals to achieve the automatic identification of targets. The working principle of the ultra-high frequency RFID system is to use an electronic tag that can receive and transmit radio waves to store information. The electronic tag and the reader use electromagnetic induction coupling energy to perform non-contact two-way communication to achieve the identification of stored information and data exchange.

[0031] In the research of ultra-high frequency RFID readers and writers, most solutions are designed by using the method of board-level connection between an MCU and an ultra-high frequency RFID baseband chip. The system integration of this piecemeal non-SoC design is poor, bringing burdens in terms of area, cost, and power consumption. In recent years, there have been studies on the SoC design of ultra-high frequency RFID readers and writers, but these studies all use open-source general-purpose cores as system processors, and there are still redundancies in the structure. They fail to achieve a more refined structure design according to the embedded application scenarios of ultra-high frequency RFID readers and writers, thus limiting the optimization potential for further miniaturization and cost reduction of the UHF RFID (Ultra-High Frequency Radio Frequency Identification Technology) system. Among them, UHF refers to radio waves with a frequency range of 300 MHz - 3000 MHz and a wavelength of 1 m - 1 dm.

[0032] In view of this, an RISC-V-based digital processing circuit for ultra-high frequency RFID readers and writers is provided in an embodiment of the present application, which can effectively improve the integration of the reader and writer and reduce the area and manufacturing cost of the reader and writer.

[0033] The embodiments of the present application will be specifically described below with reference to the accompanying drawings:

[0034] Figure 1 is an optional flowchart of an RISC-V-based digital processing circuit for ultra-high frequency RFID readers and writers provided by an embodiment of the present application. Figure 1 The reader and writer in may include, but are not limited to, a processing module, a memory module, and an ultra-high frequency reading and writing data module. Among them, the processing module includes a controller core constructed based on the RISC-V architecture; the memory module includes, but is not limited to, an SRAM module, an SDRAM module, or a ROM module, and is used to cooperate with the processing module for data storage; the interaction process between the ultra-high frequency reading and writing data module and the controller core is coordinated and managed through a bus matrix. Specifically, the processing module, the memory module, and the ultra-high frequency reading and writing data module are tightly coupled; the controller core is used to receive external control instructions sent by the host computer and control the tag data reading process of the ultra-high frequency reading and writing data module according to the external control instructions.

[0035] It can be understood that during the operation of the embodiments of the present application, when a user needs to write data to an electronic tag through a UHF reader-writer, the parameters of the UHF reader-writer can be configured first through the software in the computer host. Among them, parameter configuration means that after the host software obtains the data to be sent according to the reader-writer working process specified by the protocol, the corresponding hardware parameters are configured. The parameter configuration includes, but is not limited to, operations such as the length of the data to be sent, the data to be sent, and opening the transmission link. Specifically, the UHF reader-writer includes the UHF RFID reader-writer digital processing circuit based on RISC-V and the RF reader-writer module in the embodiments of the present application. The UHF RFID reader-writer digital processing circuit based on RISC-V is used for digital logic processing and control processes, and the RF reader-writer module is used for filtering, modulating, and other processing of radio waves. After the parameter configuration is completed, the reader-writer sends the corresponding command or data to the electronic tag. Among them, the command or data is saved in the memory module through the communication module of the processing module. When the electronic tag enters the working area of the reader-writer, the processing module retrieves the command or data from the memory module, and then obtains the data format to be sent to the electronic tag after processing through the UHF data reading and writing module.

[0036] When the user needs to read the application data of the electronic tag, the reader-writer first reads the application data inside the electronic tag located in the working area, and then sends the data to the computer. Specifically, the RF reader-writer module reads the data of the tag entering the working area. The data read is first used to obtain the original application data through the UHF data reading and writing module, and then saved in the memory module by the processing module. Finally, the computer host software reads the application data through the communication module of the processing module. It can be understood that the application data is the response of the tag to the command or data of the reader-writer, including the response data and the length of the response data, which are used for the host software to read and judge to control the subsequent interaction process between the reader-writer and the tag.

[0037] In the embodiments of the present application, the processing module is the core of the reader-writer of the present application. Among them, the processing module of this embodiment has strong data processing capabilities and a large program storage space. The processing module of this embodiment is a controller core based on the RISC-V (emerging open source instruction set architecture, ISA) architecture, named RDRV32. This controller core adopts the RV32IM instruction set and uses a five-stage pipeline structure to optimize performance and efficiency.

[0038] It can be understood that, as Figure 2As shown in the figure, the controller core of the embodiment of the present application includes a fetch module, a decode module, an execute module, a memory access module, and a write-back module; the output end of the fetch module is connected to the input end of the decode module, the output end of the decode module is connected to the first input end of the execute module, and the first output end of the execute module is connected to the input end of the memory access module; the second output end of the execute module is connected to the input end of the fetch module for branch prediction calibration; the first output end of the memory access module is connected to the input end of the write-back module; the output end of the write-back module is respectively connected to the second input end of the execute module and the interaction end of the memory access module.

[0039] It can be understood that due to the actual application scenarios of the UHF RFID reader and its requirements for data processing bit width, this embodiment selects a 32-bit instruction set instead of a 64-bit one, which can not only meet the requirements of system operation but also effectively control the hardware complexity and power consumption. In addition, the 32-bit instruction set adopted by the controller core of this embodiment includes a basic integer instruction set (I) and a multiplication and division extension instruction set (M), thereby enhancing the computing power of the controller core. And, in this embodiment, by integrating dedicated multipliers and dividers ( Figure 2 the multipliers and dividers in), the additional overhead brought by using software to simulate multiplication and division operations can be avoided, so as to improve the overall performance and response speed of the reader.

[0040] Specifically, in the execution stage, in order to accelerate the execution of multiplication instructions, this embodiment adopts a Wallace tree multiplier based on Booth encoding. Among them, the Booth algorithm is an efficient binary multiplication algorithm that can reduce the number of partial products; while the Wallace tree structure can further compress these partial products, significantly shortening the time required for the final addition operation, thus greatly improving the execution efficiency of multiplication instructions.

[0041] In order to optimize the performance of the RDRV32 controller core in the fetching and memory access stages, this embodiment also introduces a four-way set-associative I-Cache (instruction cache) and D-Cache (data cache) controller. By adopting the write-back allocation strategy executed by the write-back module and selecting SRAM as the storage medium, the cache hit rate can be increased while reducing the average access time of the controller core to the memory, effectively improving the working speed of the controller in fetching and memory access operations.

[0042] In the embodiment of the present application, in order to support the local interrupt mechanism, the controller core of this embodiment also includes an interrupt module (Core Local Interrupt, CLINT). The interrupt module is responsible for providing software interrupt and hardware clock interrupt control, ensuring that the operating system or applications running on it can respond to various internal and external events in a timely manner, enhancing the real-time performance and reliability of the reader corresponding system.

[0043] It can be understood that, as Figure 3 shown, the RDRV32 controller of this embodiment can communicate with various peripheral components through the AXI4 bus. According to the structure of the RDRV32 controller, the peripherals are divided into two categories: high-speed peripherals and low-speed peripherals. High-speed peripherals include, but are not limited to, static random access memory (SRAM), dynamic random access memory (SDRAM), universal serial bus (USB), Joint Test Action Group (JTAG) interface, and ultra-high frequency radio frequency identification (UHF RFID) reader baseband circuit, all of which use the AXI4 bus protocol to directly communicate with the controller to ensure high bandwidth and low latency of data transmission. Low-speed peripherals include, but are not limited to, timer (TIMER), serial peripheral interface (SPI), universal asynchronous receiver / transmitter (UART), input / output port (I / O port), and read-only memory (ROM), which are connected through a simpler APB bus to meet their lower data transmission rate requirements.

[0044] Based on the above communication structure of the RDRV32 controller, the interaction between the controller core and external devices in the embodiments of this application can be coordinated and managed through a bus matrix. Among them, the bus matrix integrates a bus bridge conversion circuit between the AXI4 and APB buses to ensure that the high-speed running controller can communicate with the low-speed running peripherals. In addition, a priority arbitration control mechanism is also set in the bus matrix to optimize the data exchange order and resource access rights between each peripheral and the controller, so as to ensure the timely processing of critical tasks and high-priority requests, and at the same time maintain the overall performance and stability of the system where the reader is located.

[0045] In the embodiments of this application, as Figure 4 shown, the ultra-high frequency read / write data module includes a transmission link and a reception link. Among them, the transmission link includes a parallel-to-serial conversion module, a first verification module, and an encoding module. The input end of the parallel-to-serial conversion module is connected to the output end of the processing module, the output end of the parallel-to-serial conversion module is connected to the input end of the first verification module, the output end of the first verification module is connected to the input end of the encoding module, and the output end of the encoding module is used to connect to an external radio frequency read / write module, and the external radio frequency read / write module reads the application data of the ultra-high frequency electronic tag; the reception link includes a serial-to-parallel conversion module, a second verification module, and a decoding module. The input end of the decoding module is used to receive the application data of the external radio frequency read / write module, the output end of the decoding module is connected to the input end of the second verification module, the output end of the second verification module is connected to the input end of the serial-to-parallel conversion module, and the output end of the serial-to-parallel conversion module is connected to the input end of the processing module.

[0046] Based on the structure of the above ultra-high frequency reading and writing data module, when the reader of the embodiment of the present application is in use, the processing module in the reader parses each instruction sent by the computer host and makes corresponding responses. Specifically, the processing module will perform the following tasks:

[0047] In the communication system between the ultra-high frequency RFID reader and the tag, since the reader undertakes the tasks of initiating communication and controlling the protocol process according to the protocol, the internal protocol conversion mechanism should be flexibly adjusted according to external instructions rather than adopting a closed-loop design. Therefore, the reader of this embodiment selects a microcontroller unit (MCU) based on the RISC-V architecture, so that the MCU can not only execute the reader protocol middleware function, but also receive external control instructions from the host computer to realize the interaction between these instructions and the underlying hardware.

[0048] In the peripheral device where the ultra-high frequency reading and writing data module is an AXI bus component, the ultra-high frequency reading and writing data module completes parallel data exchange and bus communication with the MCU via the AXI bus bridge circuit; at the same time, in order to match the data serial transmission requirements of the transmitting module, this embodiment also sets a serial-to-parallel conversion module in the ultra-high frequency reading and writing data module to accurately convert data between different transmission modes and coordinate the timing of these two data streams to ensure smooth communication.

[0049] Specifically, the ultra-high frequency reading and writing data module consists of a bus register address and data reading logic and a first-in first-out (FIFO). By configuring specific registers to simulate software interrupts, the communication between the MCU and the ultra-high frequency reading and writing data module is realized. When the transmission interrupt signal in the interrupt register is detected, the ultra-high frequency reading and writing data module reads the data to be sent from the specified register and stores it in the FIFO, and then outputs it serially to the next processing stage; considering that the FIFO is used for unidirectional data transmission, only the stack empty and stack full status flags need to be managed, and an effective data transfer is ensured by adding a data caching mechanism, so as to achieve efficient data transfer by using a simple state control and caching strategy.

[0050] In the ISO18000-6C protocol, the cyclic redundancy check code (CRC) is used as an error checking means for command sending and receiving. This is an error detection method widely used in the communication field, which allows customizing the check code length and polynomial. Based on this feature, the reader of this embodiment adopts a CRC-16 check module or a CRC-5 check module as the first check module or the second check module according to the standard regulations, and strictly follows the specified polynomial. Except that the query command uses CRC-5, all other commands are checked using CRC-16.

[0051] Specifically, the calculation of the CRC check code uses binary division. The CRC polynomial is used as the divisor, and the data sequence to be verified is the dividend. The resulting remainder is the check code. According to the ISO18000-6C protocol, this check code is appended to the command and serially transmitted together. Following this principle and considering the serial output characteristics of the reader transmitter link to save resources, this embodiment uses a bit-level algorithm combined with adders and exclusive OR operations to implement the calculation of the CRC check code. According to the ISO18000-6C protocol in this embodiment, the forward communication from the reader to the tag uses PIE coding, where a high level represents the transmission of continuous wave, and a low level indicates the attenuation of continuous wave. During an inventory cycle, fixed modulation depth, rise and fall times, pulse width (PW), and Tari are used for coding. This is a variable-length code that represents data by different symbol lengths. Tari defines the reference time interval for transmitting the symbol "0", and PW refers to the radio frequency pulse width. The protocol stipulates that the high-level duration of the symbol "1" is 1 to 1.5 times that of Tari. This embodiment selects 1.5 times Tari as the high-level duration of the symbol "1". At the same time, the protocol has strict requirements on the width ranges and error precisions of Tari and PW.

[0052] After data encoding is completed, according to the ISO18000-6C protocol, in the forward communication from the reader to the tag, for the query command, the reader must first send a preamble and then the command. For other commands in the same session, a frame synchronization header needs to be added before transmission. The tolerance of all signal lengths based on the Tari unit needs to be controlled within ±1%. The structure of the frame synchronization header includes a delimiter with a length of 12.5 us, a PIE-coded symbol "0" with a length of Tari, and an RTcal calibration signal. The structure of the preamble includes a delimiter with a length of 12.5 us, a PIE-coded symbol "0" with a length of Tari, an RTcal calibration signal, and a TRcal calibration signal.

[0053] RTcal is set by the reader, and its length is the sum of a symbol "1" and a symbol "0". The tag distinguishes the received data symbols by half of the RTcal length, that is, those with a duration exceeding RTcal / 2 are regarded as symbol "1", and vice versa for symbol "0". If the length of a single symbol exceeds 4 times RTcal, the tag will consider it as incorrect data. When the reader wants to change the communication rate, it needs to send a continuous high-level signal with a length of at least 8 times RTcal. TRcal is also set by the reader and combined with the frequency division ratio in the query command to determine the reverse communication rate from the tag to the reader.

[0054] The ultra-high frequency (UHF) read / write data module first reads the data and control signals of the command to be sent from the RAM. These control signals specify the transmission rate of the forward link, the PIE preamble format, and the reverse link communication rate, which assist the module in calculating the TRcal length and generating the correct code pattern. According to these signals, the UHF read / write data module decides whether to add a CRC5 or CRC16 checksum to the command. Then, the UHF read / write data module generates the code pattern of the command data according to the protocol requirements and passes the result to the shaping filter of the radio frequency read / write module for pulse shaping of the modulated signal. After the transmission link of this embodiment reads the data to be sent written by the MCU from the RAM through a parallel-to-serial converter, the first check module adds a CRC5 or CRC16 checksum as needed. Then, the PIE encoder encodes the data containing the checksum according to the protocol requirements. Among them, the state machine of the transmission link defaults to the Idle state, waiting for instructions from the host computer. After receiving the instruction, the state machine of the transmission link enters the dtrans state. At this time, the digital baseband circuit reads the specified command code to be sent through the AXI bus and advances the state machine to the next stage. The encoding module starts to serially read the data through the parallel-to-serial conversion module and execute PIE encoding. At the same time, the first check module generates the corresponding checksum and encodes it together with the data. After completing the entire data reading and encoding process, the state machine returns to the Idle state, ready for the next task.

[0055] The receiving link of the UHF read / write data processing module supports FM0 encoding in reverse communication and Miller encoding with subcarriers of 2 / 4 / 8 according to the ISO18000-6C protocol. After completing the FM0 baseband decoding or the Miller baseband decoding after removing the carrier, the receiving link performs a CRC5 or CRC16 cyclic redundancy check on the data. If the check is successful, the decoding circuit writes the data to the corresponding register through the AXI bus and uses the register to simulate an interrupt to notify the middleware. Subsequently, the middleware processes the jump of the reader protocol state according to the protocol regulations and indicates the next operation.

[0056] The FM0 decoder detects the synchronization code of the received signal through a shift register. Due to different Text values when the reader initiates communication, there are two received synchronization codes. Then, the decoding circuit decodes according to the first three bits of the received data and finally outputs the decoded data result.

[0057] When the reader inventorys multiple tags, the FM0 decoder determines whether there is a collision in the tag return data according to the decoding result. If the decoding shows that there are multiple synchronization codes in the received data or the data does not conform to the coding rules, it is determined that a collision has occurred. At this time, the FM0 decoder notifies the middleware, triggering the middleware to start the anti-collision process through protocol control to handle the multi-tag inventory.

[0058] In the embodiments of the present application, the receiving link processes Miller codes differently from FM0 codes. Since the m value of the inventory command in the transmitting link determines the subcarrier of the baseband Miller code, before decoding the received Miller code, the receiving link must first extract the Miller subcarrier from the received data to restore the original Miller baseband coding.

[0059] Specifically, the Miller decoder first sets the pilot tone for counting the received data based on the Miller subcarrier in the receiving link. When the pilot tone reaches the counting requirement specified by the protocol, the subcarrier in the received signal is removed by the locally generated Miller subcarrier to restore the Miller baseband coding. Subsequently, the extracted baseband coding is decoded using the decoding table and the result is output. When the reader / writer performs tag inventory, the Miller decoder uses the same determination method as the FM0 decoding module to determine whether a collision occurs in the tag return data.

[0060] According to the calculation principle of the CRC checksum, the CRC checksum circuit performs binary division operations. All commands returned by the tag need to be subjected to CRC-16 check. The CRC-16 check result is affected by the initial value of the register when the tag calculates CRC-16: if the register is preset to all 1s, the correct check result finally obtained by the reader / writer is "0x1D0F"; if the register is initialized to all 0s, the correct CRC16 check result should be "0x0000".

[0061] The receiving control module coordinates the read and write operations of the decoding module, the CRC checksum module, the serial-to-parallel conversion module, and the RAM. The state machine is initially in the idle state. When the reader / writer completes the command transmission, the control circuit turns off the transmission enable and turns on the reception enable, causing the receiving link state machine to enter the decoding state. If an error occurs during the decoding process, the state machine sends an error signal to the reader / writer control module to prompt re-communication. When the decoding is successful, the state machine switches to the transmission state, writes the decoded data into the receive register through the AXI bus, and uses the register to simulate a software interrupt to notify the middleware. Subsequently, the middleware reads and parses the data in the receive register and instructs the reader / writer to perform the next operation according to the protocol-specified process.

[0062] As can be seen from the above, the reader in the embodiment of the present application designs the MCU by adopting the RISC-V architecture, so that the manufacturing cost of the reader can be reduced by using the characteristics of the RISC-V architecture, and the modular characteristics of the RISC-V instruction set architecture can be utilized. Furthermore, the capabilities of the processor can be customized according to requirements to design the MCU to meet the basic requirements of the operation of the ultra-high frequency reader, effectively reducing power consumption and area. At the same time, a design process of tightly coupling the RISC-V MCU and the ultra-high frequency read / write data module is adopted, avoiding the reader design form of discrete devices, further reducing the area of the reader, and effectively improving the integration degree of the reader.

[0063] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation to the embodiments of the present application, and may include more or fewer steps than those shown in the figures, or combine some steps, or different steps.

[0064] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware and their appropriate combinations.

[0066] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0067] The units described as separate components above may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, which do not limit the scope of rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of rights of the embodiments of the present application.

Claims

1. A digital processing circuit for an ultra-high frequency RFID reader based on RISC-V, characterized in that, The RISC-V based ultra-high frequency RFID reader digital processing circuit includes: A processing module, the processing module includes a controller core, and the controller core is constructed based on the RISC-V architecture; A memory module, and the memory module is used to cooperate with the processing module for data storage; An ultra-high frequency reading and writing data module, and the interaction process between the ultra-high frequency reading and writing data module and the controller core is coordinated and managed through a bus matrix; Wherein, the processing module, the memory module and the ultra-high frequency reading and writing data module are tightly coupled; the controller core is used to receive external control instructions sent by the host computer, and control the tag data reading process of the ultra-high frequency reading and writing data module according to the external control instructions.

2. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 1, wherein The controller core includes an instruction fetch module, a decoding module, an execution module, a memory access module and a write-back module; the output end of the instruction fetch module is connected to the input end of the decoding module, the output end of the decoding module is connected to the first input end of the execution module, and the first output end of the execution module is connected to the input end of the memory access module; the second output end of the execution module is connected to the input end of the instruction fetch module for branch prediction calibration; the first output end of the memory access module is connected to the input end of the write-back module; the output end of the write-back module is respectively connected to the second input end of the execution module and the interaction end of the memory access module.

3. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 2, characterized in that, A multiplier and a divider are integrated in the execution module; the controller core adopts a 32-bit instruction set, and the 32-bit instruction set includes a basic integer instruction set and a multiplication and division extension instruction set.

4. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 3, characterized in that, The multiplier includes a Wallace multiplier based on Booth encoding.

5. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 2, wherein The controller core further includes an interrupt module, and the interrupt module is used for software terminal control and hardware clock control.

6. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 1, characterized in that, The bus matrix integrates a bus bridge conversion circuit and has a built-in priority arbitration mechanism; the priority arbitration mechanism is used to adjust the data interaction sequence and resource access rights between the controller core and the peripherals.

7. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 1, characterized in that, The ultra-high frequency reading and writing data module includes a transmission link and a reception link; The transmission link includes a parallel-to-serial conversion module, a first verification module and an encoding module. The input end of the parallel-to-serial conversion module is connected to the output end of the processing module, the output end of the parallel-to-serial conversion module is connected to the input end of the first verification module, the output end of the first verification module is connected to the input end of the encoding module, and the output end of the encoding module is used to connect to an external radio frequency reading and writing module, and the external radio frequency reading and writing module reads the application data of the ultra-high frequency electronic tag; The reception link includes a serial-to-parallel conversion module, a second verification module and a decoding module. The input end of the decoding module is used to receive the application data of the external radio frequency reading and writing module, the output end of the decoding module is connected to the input end of the second verification module, the output end of the second verification module is connected to the input end of the serial-to-parallel conversion module, and the output end of the serial-to-parallel conversion module is connected to the input end of the processing module.

8. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 7, characterized in that The first verification module includes a CRC-16 verification module or a CRC-5 verification module; after reading a control signal from a peripheral register, the encoding module determines the working state of the CRC-16 verification module or the CRC-5 verification module according to the control signal.

9. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 7, characterized in that, The decoding module includes an FM0 decoder or a Miller decoder; the FM0 decoder decodes according to the first three bits of the received data; the Miller decoder sets a count of the pilot tone in the received data according to the Miller subcarrier in the receiving link, and when the pilot tone reaches a preset count requirement, removes the Miller subcarrier in the received signal according to the locally generated Miller subcarrier to restore the Miller baseband coding, and decodes the restored Miller baseband coding using a decoding table.

10. The digital processing circuit of the ultra-high frequency RFID reader / writer based on RISC-V according to claim 1, wherein The memory module includes an SRAM module, a SDRAM module or a ROM module.

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