Redundancy repair method, redundancy repair circuit and memory

Abstract

The invention relates to the technical field of semiconductors, and provides a redundancy repair method, a redundancy repair circuit and a memory, and the redundancy repair method comprises the steps: obtaining a redundancy resource address and a failure address; judging whether the redundancy repair operation has residual programming times or not, and generating a programming indication signal in response to the residual programming times of the redundancy repair operation; programming a redundant resource corresponding to the redundant resource address based on the programming indication signal and the failure address; reading a programming address of the redundant resource corresponding to the redundant resource address after programming; judging whether the programming address is the same as the failure address or not, and storing the failure address into a local register in response to the fact that the programming address is the same as the failure address; the redundancy repair method, the redundancy repair circuit and the memory provided by the invention aim at improving the redundancy repair execution effect of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a redundancy repair method, a redundancy repair circuit, and a memory. Background Art

[0002] There is a problem of word line failure in a dynamic random access memory (DRAM); if a word line fails, it is necessary to repair the address of the failed word line.

[0003] The DRAM stores the address of the failed word line (hereinafter referred to as: the failed address) into multiple anti-fuse memory cells in the same anti-fuse resource, and then uses the redundant word line (Redundancy Word Line, RWL) corresponding to the anti-fuse resource to replace the failed word line to achieve the repair of the failed address. Specifically, the redundant word lines and the anti-fuse resources correspond one by one. When repairing the failed address, the failed address is programmed into multiple anti-fuse memory cells in the anti-fuse resource. When decoding the current address, by comparing the current address with the failed addresses stored in different anti-fuse resources, once the failed address stored in a certain anti-fuse resource is the same as the current address, the redundant word line corresponding to the anti-fuse resource will be accessed, so as to achieve the replacement of the normal word line with the redundant word line.

[0004] The technical specification of DRAM JEDEC stipulates that the user can program the failed address into the anti-fuse resource through post package repair (PPR) to achieve patching; however, after the DRAM is shipped from the factory, the user cannot predict the fuse melting rate and patching rate of the anti-fuse memory cells in the anti-fuse resource, and the fuse failure or misreading of the anti-fuse memory cells in the anti-fuse resource will directly affect the effect of post package repair. Summary of the Invention

[0005] The present disclosure provides a redundancy repair method, a redundancy repair circuit, and a memory, which are at least used to improve the effect of the memory performing redundancy repair.

[0006] In a first aspect, an embodiment of the present disclosure provides a redundancy repair method, including: obtaining a redundancy resource address and a failure address; determining whether there is a remaining programming count for the current redundancy repair operation, and generating a programming indication signal in response to there being the remaining programming count for the current redundancy repair operation; programming the redundancy resource corresponding to the redundancy resource address based on the programming indication signal and the failure address; reading the programmed address of the redundancy resource corresponding to the redundancy resource address after programming; determining whether the programmed address is the same as the failure address, and storing the failure address in a local register in response to the programmed address being the same as the failure address.

[0007] In some embodiments, the redundancy repair method further includes: ending the redundancy repair operation in response to there being no remaining programming count for the current redundancy repair operation.

[0008] In some embodiments, the method for obtaining the redundancy resource address includes: obtaining the redundancy resource address in a repair storage block; determining whether the redundancy resource corresponding to the redundancy resource address is in use; and using the redundancy resource corresponding to the currently obtained redundancy resource address as the redundancy resource to be programmed in response to the redundancy resource not being in use.

[0009] In some embodiments, the redundancy repair method further includes: obtaining the next redundancy resource address in the repair storage block in response to the redundancy resource being in use.

[0010] In some embodiments, the method for determining whether the redundancy resource corresponding to the redundancy resource address is in use includes: determining whether the redundancy resource is in use based on a flag bit corresponding to the redundancy resource address, or determining whether the redundancy resource is in use based on the current data state of the redundancy resource corresponding to the redundancy resource address.

[0011] In some embodiments, the redundancy repair method further includes: obtaining the next redundancy resource address in response to the programmed address being different from the failure address, where the next redundancy resource address is used to re-execute the redundancy repair operation.

[0012] In some embodiments, before obtaining the next redundancy resource address, the redundancy repair method further includes: determining whether the current redundancy resource address is the last repair resource in the repair storage block; and obtaining the next redundancy resource address in response to the current redundancy resource address not being the last repair resource in the repair storage block.

[0013] In some embodiments, the redundancy repair method further includes: ending the redundancy repair operation in response to the current redundancy resource address being the last repair resource in the repair storage block.

[0014] Second aspect, embodiments of the present disclosure provide a redundant repair circuit, including: an address receiving module configured to obtain a redundant resource address and a failed address; an enabling module configured to determine whether there is a remaining programming count for the current redundant repair operation, and output a programming indication signal in response to there being a remaining programming count for the current redundant repair operation; a programming module connected to the address receiving module and the enabling module; the programming module being configured to program the redundant resource corresponding to the redundant resource address based on the programming indication signal and the failed address; an address verification module configured to read the programmed address after programming the redundant resource corresponding to the redundant resource address, and determine whether the programmed address is the same as the failed address; and a storage module configured to store the failed address in response to the programmed address being the same as the failed address.

[0015] In some embodiments, the address receiving module includes: a first obtaining unit configured to obtain the redundant resource address in a repair storage block; a first verification unit connected to the first obtaining unit; the first verification unit being configured to determine whether the redundant resource corresponding to the redundant resource address is in use, and in response to the redundant resource not being in use, use the redundant resource corresponding to the currently obtained redundant resource address as the redundant resource to be programmed.

[0016] In some embodiments, the first verification unit is further configured to, in response to the redundant resource being in use, instruct the first obtaining unit to obtain the next redundant resource address in the repair storage block, and determine whether the redundant resource corresponding to the next redundant resource address is in use.

[0017] In some embodiments, the address receiving module is further configured to, in response to the programmed address being different from the failed address, obtain the next redundant resource address, where the next redundant resource address is used to re - execute the redundant repair operation.

[0018] In some embodiments, the address receiving module further includes: a second verification unit connected to the first verification unit; the second verification unit being configured to, before obtaining the next redundant resource address, determine whether the current redundant resource address is the last repair resource in the repair storage block, and in response to the current redundant resource address not being the last repair resource in the repair storage block, instruct the first obtaining unit to obtain the next redundant resource address.

[0019] In some embodiments, the address verification module includes: a comparator, a first input terminal receiving the programming address, and a second input terminal receiving the failure address; the comparator is configured to output a trigger signal in response to the programming address being the same as the failure address, and the trigger signal is used to indicate that the storage module stores the corresponding failure address.

[0020] In some embodiments, the comparator includes: an exclusive - OR logic structure, a first input terminal of the exclusive - OR logic structure receiving the programming address, a second input terminal of the exclusive - OR logic structure receiving the failure address, and an output terminal of the exclusive - OR logic structure for outputting the trigger signal.

[0021] In some embodiments, the address verification module further includes: an AND logic structure, a first input terminal connected to the output terminal of the comparator, a second input terminal for receiving an indication signal, and an output terminal for outputting the trigger signal, where the indication signal is used to characterize whether the current redundant resource address is the last repair resource in the repaired storage block.

[0022] In some embodiments, the address verification module further includes: a counting unit, an input terminal connected to the output terminal of the AND logic structure; the counting unit is configured to count the trigger signal to generate and output a counting signal, and the counting signal is used to calculate whether there is a remaining programming number of times for this redundant repair operation.

[0023] In some embodiments, the address receiving module further includes: a second acquisition unit, configured to select a sampling mode based on a mode control signal and perform address sampling on the failure address based on the selected sampling mode, where the sampling mode is used to configure the number of address bits for sampling the failure address once.

[0024] In some embodiments, the number of address bits of the failure address is N, where N is a positive integer, and the second acquisition unit includes: a shift driving circuit, configured to output a driving signal of N bits, and the driving signal performs a carry operation based on a clock signal; a sampling circuit, connected to the shift driving circuit and receiving the failure address, configured to sample the corresponding bit of the failure address based on the corresponding bit of the driving signal; a mode control circuit, connected to the shift driving circuit, configured to add an initial working bit of the shift driving circuit based on the mode control signal.

[0025] In a third aspect, an embodiment of the present disclosure provides a memory, where the memory performs a redundant repair operation based on the redundant repair method provided in the first aspect above, or, the memory includes the redundant repair circuit provided in the second aspect above.

[0026] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: By judging whether there is a remaining programming count for the current redundancy repair operation, it is ensured that the redundancy repair operation can be executed smoothly; By reading and judging the programming address of the redundancy repair, it is determined whether the failed word line is effectively repaired. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 It is a schematic flow chart corresponding to each step in the first redundancy repair method provided by an embodiment of the present disclosure;

[0029] Figure 2 It is a schematic flow chart corresponding to each step in the second redundancy repair method provided by an embodiment of the present disclosure;

[0030] Figure 3 It is a schematic flow chart corresponding to each step in the method for obtaining the redundancy resource address provided by an embodiment of the present disclosure;

[0031] Figure 4 It is a schematic flow chart corresponding to determining whether the current redundancy resource address is the address corresponding to the last repair resource in the repair storage block provided by an embodiment of the present disclosure;

[0032] Figure 5 It is a schematic structural diagram of a redundancy repair circuit provided by another embodiment of the present disclosure;

[0033] Figure 6 It is a schematic structural diagram of an address receiving module provided by another embodiment of the present disclosure;

[0034] Figure 7 It is a schematic structural diagram of a second obtaining unit provided by another embodiment of the present disclosure;

[0035] Figure 8 provided by another embodiment of the present disclosure Figure 7 Timing diagram corresponding to the example sampling timing;

[0036] Figure 9 It is a schematic structural diagram of an address verification module provided by another embodiment of the present disclosure. Detailed implementation manners

[0037] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is more than two, unless otherwise clearly and specifically defined.

[0038] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. The phrase appearing in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0039] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: the existence of A, the simultaneous existence of A and B, and the existence of B. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0040] In the description of the embodiments of the present disclosure, the term "a plurality of" means more than two (including two). Similarly, "a plurality of groups" means more than two groups (including two groups), and "a plurality of pieces" means more than two pieces (including two pieces).

[0041] In the description of the embodiments of the present disclosure, technical terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the embodiments of the present disclosure.

[0042] In the description of the embodiments of the present disclosure, unless otherwise clearly defined and limited, technical terms such as "installation", "connection", "connection", "fixation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0043] In the corresponding drawings of the embodiments of the present disclosure, for better understanding and description, the thickness and area of the layer are enlarged. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a partial edge of the entire surface.

[0044] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when a component such as a layer, film, region, or plate is referred to as "on / located on" another component, it can be "directly on" the other component (that is, on the surface of the other component and there is no other component between the two), or there can be another component between them. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that there is no other component between them.

[0045] The terms used in the description of the various embodiments herein are only for describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form, unless the context clearly indicates otherwise. Among them, the component includes components such as layers, films, regions, or plates.

[0046] As can be seen from the background technology, after the DRAM leaves the factory, the user cannot predict the fuse melting rate and repair rate of the anti-fuse storage cells in the anti-fuse resources, and the fuse failure or misreading of the anti-fuse storage cells in the anti-fuse resources will directly affect the repair effect after packaging.

[0047] It should be noted that for the antifuse memory cell mentioned in the present disclosure, it is in a disconnected state when not programmed, and at this time, the antifuse memory cell represents the data "0"; the antifuse memory cell is in an electrically connected state after programming, and at this time, the antifuse memory cell represents the data "1".

[0048] The embodiments of the present disclosure provide a redundancy repair method, including: obtaining a redundant resource address and a failure address; determining whether there is a remaining programming count for this redundancy repair operation, and generating a programming indication signal in response to there being the remaining programming count for this redundancy repair operation; programming the redundant resource corresponding to the redundant resource address based on the programming indication signal and the failure address; reading the programming address after programming the redundant resource corresponding to the redundant resource address; determining whether the programming address is the same as the failure address, and storing the failure address in a local register in response to the programming address being the same as the failure address.

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0050] Reference Figure 1 , Figure 1 is a schematic flowchart corresponding to each step in the first redundancy repair method provided in this embodiment. The redundancy repair method provided in this embodiment includes steps 101 to 106; among them, in step 101, a redundant resource address and a failure address are obtained; in step 102, it is determined whether there is a remaining programming count for this redundancy repair operation; in step 103, the redundant resource corresponding to the redundant resource address is programmed; in step 104, the programming address after programming the redundant resource corresponding to the redundant resource address is read; in step 105, it is determined whether the programming address is the same as the failure address; in step 106, the failure address is stored in a local register.

[0051] For step 101, a redundant resource address and a failure address are obtained.

[0052] The memory obtains the failure address and the redundant resource address for performing redundancy repair on the failure address.

[0053] In one example, the failed address is the address of a failed word line (WL); where the failed word line address includes (can also be understood as): (1) a word line with poor quality formed due to reasons such as the formation process; (2) a word line that cannot be written / read normally based on the target word line after the memory selects the target word line during the test; (3) a word line with severely degraded performance after the memory has been used for a period of time.

[0054] In one example, the redundant resources include antifuse resources or other resources that can be used to store failed addresses, such as register resources and fuse cells. Each antifuse resource contains a group of antifuse memory cells (Anti-Fuse Cell) for storing failed addresses, and the antifuse resource address is the address of the corresponding group of antifuse memory cells; where one redundant resource corresponds to one redundancy word line (RWL). The antifuse memory cells can have various forms, for example, they can be capacitors, or various forms such as the gate and source / drain of a transistor.

[0055] Specifically, taking the redundant resource as the antifuse resource as an example, when repairing the failed address, the failed address is programmed into multiple antifuse memory cells in the antifuse resource. When decoding the current address, by comparing the current address with the failed addresses stored in different antifuse resources, once the failed address stored in a certain antifuse resource is the same as the current address, the redundancy word line corresponding to that antifuse resource will be accessed, thereby realizing the replacement of the normal word line with the redundancy word line.

[0056] For step 102, determine whether there is a remaining programming count for this redundancy repair operation.

[0057] Among them, the "redundancy repair operation" refers to an operation stage in which the memory can perform one or more programming operations to program the failed address into the redundant resource. If the failed address is successfully programmed into a certain redundant resource, the normal word line corresponding to the failed address is replaced by the redundancy word line corresponding to the redundant resource storing the failed address, and the repair is completed.

[0058] In one example, each redundancy repair operation is used to perform redundancy repair for one failed address. The time for the memory to perform the redundancy repair operation is limited by JEDEC, generally 1000ms - 3000ms, and different products also have different redundancy repair operation times.

[0059] In each redundancy repair operation, within a specified time, if the memory successfully executes a programming operation, that is, successfully programs the failed address into the redundant resource corresponding to the redundant resource address, the redundancy repair operation is successfully repaired; if one or more programming operations of the memory fail, it is determined whether a new redundant resource address can be obtained and a programming operation can be executed based on the remaining time of the redundancy repair operation. If the remaining time of the redundancy repair operation allows for continued execution of the programming operation, the programming operation is repeatedly executed until the failed address is successfully programmed into the redundant resource corresponding to the redundant resource address; if the remaining time of the redundancy repair operation is insufficient to continue the programming operation (or obtain a new redundant resource address and execute the programming operation), the current redundancy repair operation fails.

[0060] For a single programming operation, the programming process of the redundant resource is the main time-consuming part. Therefore, the overall time of a single programming operation or the average time for programming the redundant resource can be used to determine whether the remaining time of the redundancy repair operation can execute the programming operation again, that is, to determine whether there are remaining programming times for the current redundancy repair operation.

[0061] If there are remaining programming times for the current redundancy repair operation, it indicates that the remaining time of the current redundancy repair operation can execute the programming operation. At this time, a programming indication signal can be generated and step 103 is executed.

[0062] For step 103, the redundant resource corresponding to the redundant resource address is programmed.

[0063] The memory programs the redundant resource corresponding to the redundant resource address based on the programming indication signal and the failed address, where the programming indication signal is used to indicate programming of the redundant resource corresponding to the redundant resource address, and the failed address is the content for which the memory programs the redundant resource. In one example, the redundant resource obtained by the memory based on the redundant resource address is an anti-fuse resource including multiple anti-fuse memory cells, and the memory programs the anti-fuse memory cells in the anti-fuse resource based on the programming indication signal to program the failed address into the corresponding anti-fuse resource.

[0064] For steps 104 and 105, the programmed address after programming the redundant resource corresponding to the redundant resource address is read, and it is determined whether the programmed address is the same as the failed address.

[0065] Fusing of the anti-fuse memory cells by the memory may result in a fusing error. By reading the programmed address after programming the redundant resource corresponding to the redundant resource address, it can be determined whether the programmed address is the same as the failed address, thereby determining whether the failed word line is effectively repaired.

[0066] If the programmed address is the same as the failed address, that is, the data after programming the redundant resource is the same as the failed address, then the programming operation for the failed address is successful, the redundant repair operation is successful, and step 106 is continued.

[0067] For step 106, store the failed address in the local register.

[0068] After the failed address is successfully programmed into the redundant resource, it indicates that the current redundant repair operation is successfully completed. At this time, the failed address needs to be stored in the local register so that when the subsequent memory performs word line addressing, the word line address can be compared with the failed address stored in the local register. Thus, when one of the currently accessed word line address and the stored failed address is the same, the redundant word line corresponding to the redundant resource programmed with the currently accessed word line address is accessed.

[0069] For the redundant repair method provided in this embodiment, by judging whether there is a remaining programming count for the current redundant repair operation, it is ensured that the redundant repair operation can be executed smoothly; by reading and judging the programmed address of the redundant repair operation, it is determined whether the failed word line is effectively repaired.

[0070] Figure 2 This is the flowchart corresponding to each step in the second redundant repair method provided in this embodiment. In some embodiments, the redundant repair method further includes: in response to there being no remaining programming count for the current redundant repair operation, ending the redundant repair operation. Refer to Figure 2 , the redundant repair method further includes step 108, ending the redundant repair operation. Based on the foregoing, if there is a remaining programming count for the current redundant repair operation, it indicates that the remaining time of the current redundant repair operation can perform a programming operation. At this time, a programming indication signal is generated and step 103 is executed. Correspondingly, if there is no remaining programming count for the current redundant repair operation, it indicates that the remaining time of the current redundant repair operation cannot perform a programming operation. At this time, the current redundant repair operation fails and the redundant repair operation ends.

[0071] By judging whether there is a remaining programming count for the current redundant repair operation, when there is no remaining programming count for the current redundant repair operation, the redundant repair operation is directly ended to ensure that the time of the redundant repair operation meets the JEDEC regulations and to avoid the redundant repair operation being forcibly interrupted during execution.

[0072] In some embodiments, the redundant repair method further includes: in response to the programmed address being different from the failed address, obtaining the next redundant resource address, where the next redundant resource address is used to re - execute the redundant repair operation.

[0073] Refer to Figure 2, based on the foregoing, for step 105, if the programming address is the same as the failed address, that is, the data programmed into the redundant resource is the same as the failed address, then the failed address is successfully programmed into the redundant resource, and the redundant repair operation is successful. Then, step 106 is continued. In this embodiment, if the programming address is different from the failed address, that is, the data characterized after programming the redundant resource is different from the failed address, then the failed address is failed to be programmed into the redundant resource, this programming operation fails, and this redundant repair operation needs to re-obtain the redundant resource address to execute the programming operation, that is, step 101 is re-executed.

[0074] By reading and judging the programming address after the programming operation, it is ensured that the address programmed into the redundant resource is the failed address. If the programming of the failed address fails, then the redundant resource address is re-obtained to execute the programming operation, so as to determine whether the failed word line is effectively repaired.

[0075] Reference Figure 3 , Figure 3 FIG. 10 is a schematic flowchart corresponding to each step in the method for obtaining a redundant resource address provided in this embodiment. In some embodiments, the method for obtaining a redundant resource address includes: obtaining a redundant resource address in a repair storage block; determining whether the redundant resource corresponding to the redundant resource address is used; in response to the redundant resource not being used, using the redundant resource corresponding to the currently obtained redundant resource address as the redundant resource to be programmed.

[0076] In this embodiment, step 101 includes steps 201 to 203. Step 201 is to obtain a redundant resource address in a repair storage block; step 202 is to determine whether the redundant resource corresponding to the redundant resource address is used; step 203 is to use the redundant resource corresponding to the currently obtained redundant resource address as the redundant resource to be programmed.

[0077] For steps 201 and 202, a redundant resource address is obtained in the repair storage block, and it is determined whether the redundant resource corresponding to the redundant resource address is used.

[0078] The redundant resource address obtained in the repair storage block may have been used, including: being used during the redundant repair operation performed before the memory leaves the factory, or having been used in a previous redundant repair operation. By determining that the obtained redundant resource address is an unused resource, the effective execution of this redundant repair operation is ensured.

[0079] If the redundant resource corresponding to the obtained redundant resource address is not used, it indicates that the currently obtained redundant resource address can be used for the programming operation, and step 203 is executed.

[0080] For step 203, the redundant resource corresponding to the currently obtained redundant resource address is used as the redundant resource to be programmed.

[0081] In response to the redundant resource not being used, the redundant resource corresponding to the currently obtained redundant resource address is used as the redundant resource to be programmed.

[0082] In some embodiments, the redundant repair method further includes: in response to the redundant resource having been used, obtaining the next redundant resource address in the repair storage block.

[0083] Reference Figure 2 and Figure 3 , based on the foregoing, for step 202, if the redundant resource corresponding to the obtained redundant resource address is not used, it indicates that the currently obtained redundant resource address can be used for programming operations, and step 203 is executed. In this embodiment, if the redundant resource corresponding to the obtained redundant resource address has been used, it indicates that the currently obtained redundant resource address cannot be used for programming operations, and the current redundant repair operation needs to re-obtain the redundant resource address to execute the programming operation, that is, step 201 is re-executed.

[0084] For step 202, in some embodiments, the method for determining whether the redundant resource corresponding to the redundant resource address is used includes: determining whether the redundant resource is used based on the flag bit corresponding to the redundant resource address.

[0085] In one example, by setting a flag bit for the redundant resource address, the flag bit is used to indicate whether the redundant resource is used. For example, the flag bit "1" indicates that the redundant resource has been used, and the flag bit "0" indicates that the redundant resource is not used. By setting a flag bit for the redundant resource address, it is possible to quickly determine whether the redundant resource corresponding to the redundant resource address is used, improving the execution efficiency of the redundant repair operation.

[0086] In some embodiments, the method for determining whether the redundant resource corresponding to the redundant resource address is used includes: determining whether the redundant resource is used based on the current data state of the redundant resource corresponding to the redundant resource address.

[0087] If the redundant resource is used, then the redundant resource has been programmed; if the redundant resource is not used, then the redundant resource has not been programmed, and the data state of the redundant resource after being programmed is different from the data state before being programmed. Based on the data state corresponding to the redundant resource, it is possible to obtain whether the redundant resource is used. In one example, a logical operation is performed on the current data state of the redundant resource to obtain a representation value, and the representation value is used to indicate whether the redundant resource is used, so as to quickly determine whether the redundant resource is used based on the representation value corresponding to the redundant resource, improving the execution efficiency of the redundant repair operation.

[0088] It should be noted that the above-mentioned "logical operations" can be set to exclusive OR operations, AND operations, OR operations, etc., or combinations of some logical operations, based on the specific usage scenario, so as to obtain a representation value that fits the usage scenario based on the usage scenario.

[0089] Based on the foregoing, if the judgment result of step 105 indicates that the programming address is different from the failure address, step 101 needs to be re-executed to obtain the next redundant resource address. Or, if the judgment result of step 202 indicates that the redundant resource corresponding to the redundant resource has been used, step 101 needs to be re-executed to obtain the next redundant resource address. In some embodiments, before obtaining the next redundant resource address, the redundant repair method further includes: determining whether the current redundant resource address is the last repair resource in the repair storage block; in response to the current redundant resource address not being the last repair resource in the repair storage block, obtaining the next redundant resource address.

[0090] Reference Figure 4 And in combination with Figures 1 - 3 , Figure 4 is a schematic flowchart corresponding to determining whether the current redundant resource address is the last repair resource in the repair storage block provided in this embodiment. It should be noted that Figure 4 The steps 105, 202, and 108 shown are Figures 1 - 3 the corresponding steps in.

[0091] In the redundant repair method provided in this embodiment, between the process where step 202 points to step 101, or, between the process where step 105 points to step 101, there is also step 109 to determine whether the current redundant resource address is the last repair resource in the repair storage block.

[0092] For step 109, if the current redundant resource address is not the last repair resource in the repair storage block, it indicates that there are still available repair resources in the repair storage block, and step 101 is re-executed. By determining whether there are unused repair resources in the repair storage block to perform the programming operation, the effective execution of this redundant repair operation is ensured.

[0093] In some embodiments, the redundant repair method further includes: in response to the current redundant resource address being the last repair resource in the repair storage block, ending the redundant repair operation.

[0094] Based on the foregoing, for step 109, if the current redundant resource address is not the last repair resource in the repair storage block, it indicates that there are still available repair resources in the repair storage block, and step 101 is re-executed. In this embodiment, if the current redundant resource address is the last repair resource in the repair storage block, it indicates that there are no available repair resources in the repair storage block, and the memory cannot perform a programming operation anymore, that is, step 108 is executed. By directly ending the redundant repair operation when it is determined that there are no repair resources in the repair storage block, the loop of the memory repeatedly obtaining the used repair resources is avoided, thereby avoiding the impact of the redundant repair operation on the normal working process of the memory.

[0095] In some embodiments, the method for determining whether the current redundant resource address is the last repair resource in the repair storage block includes: determining whether the current redundant resource address is the last address. If so, it indicates that the current redundant resource address is the last repair resource; if not, it indicates that the current redundant resource address is not the last repair resource. In still other embodiments, it can be determined whether all the flag bits corresponding to the redundant resource address are "1". If so, it indicates that the current redundant resource address is the last repair resource, and if not, it indicates that the current redundant resource address is not the last repair resource.

[0096] In other embodiments, it can be determined whether the data state in each redundant resource address is different from the initial data state (the data state when not programmed). If they are all different, it indicates that the current redundant resource address is the last repair resource; if not, it indicates that the current redundant resource address is not the last repair resource. Among them, the data state in each redundant resource address includes the data states of all the anti-fuse storage units in each anti-fuse resource.

[0097] In some embodiments, since the overall flag bits are determined after each programming, or it is determined whether the data state in each redundant resource address is different from the data state under the unprogrammed condition, therefore, the redundant resources that meet the requirements of the flag bits can be directly obtained, or the repair resources with the initial data state can be obtained. At this time, it is no longer necessary to determine whether the redundant resources corresponding to the redundant resource address are used.

[0098] In summary, in the redundant repair method provided in this embodiment, by judging whether there are remaining programming times for the current redundant repair operation, it is ensured that the redundant repair operation can be smoothly executed; by reading and judging the programming address after the programming operation, it is determined whether the failed word line is effectively repaired.

[0099] It should be noted that, without conflict, the features disclosed in the redundant repair methods provided in the above embodiments can be randomly combined to obtain new embodiments of the redundant repair method.

[0100] Another embodiment of the present disclosure further provides a redundancy repair circuit, including: an address receiving module configured to obtain a redundancy resource address and a failure address; an enabling module configured to determine whether there is a remaining programming count for the current redundancy repair operation, and output a programming indication signal in response to there being a remaining programming count for the current redundancy repair operation; a programming module connected to the address receiving module and the enabling module; the programming module being configured to program the redundancy resource corresponding to the redundancy resource address based on the programming indication signal and the failure address; an address verification module configured to read the programmed address after programming the redundancy resource corresponding to the redundancy resource address, and determine whether the programmed address is the same as the failure address; and a storage module configured to store the failure address in response to the programmed address being the same as the failure address.

[0101] The redundancy repair circuit provided in this embodiment will be described below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts in the foregoing embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated hereinafter.

[0102] Reference Figure 5 , Figure 5 is a schematic structural diagram of the redundancy repair circuit provided in this embodiment. The redundancy repair circuit 300 includes: an address receiving module 301, an enabling module 302, a programming module 303, an address verification module 304, and a storage module 305.

[0103] The address receiving module 301 is configured to obtain a redundancy resource address and a failure address. Specifically, the address receiving module 301 is configured to obtain the failure address and the redundancy resource address for programming the failure address.

[0104] The enabling module 302 is configured to determine whether there is a remaining programming count for the current redundancy repair operation, and output a programming indication signal in response to there being a remaining programming count for the current redundancy repair operation.

[0105] The programming module 303, connected to the address receiving module 301 and the enabling module 302, is configured to program the redundancy resource corresponding to the redundancy resource address based on the programming indication signal and the failure address. Among them, the programming indication signal is used to instruct the programming module 303 to program the redundancy resource corresponding to the redundancy resource address, and the failure address is the content for the programming module 303 to program the redundancy resource. Specifically, the fusing of the antifuse memory cell by the programming module 303 may have a fusing error. By reading the programmed address after programming the redundancy resource corresponding to the redundancy resource address, it can be determined whether the programmed address is the same as the failure address, so as to determine whether the failed word line is effectively repaired.

[0106] The address verification module 304 is configured to read the programmed address after programming the redundant resource corresponding to the redundant resource address, and determine whether the programmed address is the same as the failed address.

[0107] For the storage module 305, in some embodiments, as Figure 5 shown, the storage module 305 is connected to the address receiving module 301. If the programmed address is the same as the failed address, the storage module 305 obtains the failed address from the address receiving module 301. If the storage module 305 successfully completes the storage of the failed address, it indicates the end of the redundant repair operation.

[0108] In some embodiments, the storage module 305 is connected to the address verification module 304. If the programmed address is the same as the failed address, the storage module 305 obtains the failed address from the address verification module 304. If the storage module 305 successfully completes the storage of the failed address, it indicates the end of the redundant repair operation.

[0109] In some embodiments, the address receiving module 301 and the storage module 305 directly obtain the failed address externally based on the redundant repair circuit 300. Among them, if the programmed address is the same as the failed address, the storage module 305 obtains the failed address externally. If the storage module 305 successfully completes the storage of the failed address, it indicates the end of the redundant repair operation.

[0110] For the redundant repair circuit 300 provided in this embodiment, the enable module 302 determines whether there is a remaining programming count for this redundant repair operation to ensure that the redundant repair operation can be executed smoothly; the address verification module 304 reads and determines the programmed address of the redundant repair to ensure that the address programmed into the redundant resource is the failed address, so as to determine whether the failed word line is effectively repaired.

[0111] In some embodiments, the enable module 302 is configured to end the redundant repair operation in response to there being no remaining programming count for this redundant repair operation. By the enable module 302 determining whether there is a remaining programming count for this redundant repair operation, if there is no remaining programming count for this redundant repair operation, the redundant repair operation is directly ended to ensure that the time of the redundant repair operation meets the JEDEC regulations and to avoid the redundant repair operation being forcibly interrupted during execution.

[0112] In some embodiments, the address receiving module 301 is further configured to obtain the next redundant resource address in response to the programmed address being different from the failed address, and the next redundant resource address is used to re-execute the redundant repair operation. By the address verification module 304 reading and determining the programmed address of the redundant repair to ensure that the address programmed into the redundant resource is the failed address. If the programming of the failed address fails, the redundant resource address is re-obtained to execute the programming operation, so as to determine whether the failed word line is effectively repaired.

[0113] Reference Figure 6 , Figure 6 is a schematic structural diagram of the address receiving module provided in this embodiment. In some embodiments, the address receiving module 301 includes a first obtaining unit 401 and a first verification unit 403. The first obtaining unit 401 is configured to obtain a redundant resource address from the repair storage block. The first verification unit 403 is connected to the first obtaining unit 401, and the first verification unit 403 is configured to determine whether the redundant resource corresponding to the redundant resource address is used, and in response to the redundant resource not being used, use the redundant resource corresponding to the currently obtained redundant resource address as the redundant resource to be programmed. By determining through the first verification unit 403 that the obtained redundant resource address is an unused resource, the effective execution of this redundant repair operation is ensured.

[0114] In some embodiments, the first verification unit 403 is further configured to, in response to the redundant resource being used, instruct the first obtaining unit 401 to obtain the next redundant resource address from the repair storage block, and determine whether the redundant resource corresponding to the next redundant resource address is used.

[0115] In some embodiments, the address receiving module 301 further includes a latching unit 402. The latching unit 402 is connected to the first obtaining unit 401 and is configured to latch the currently obtained redundant resource address of the first obtaining unit 401 if the redundant resource corresponding to the redundant resource address is not in use. If the first verification unit 403 verifies that the redundant resource corresponding to the redundant resource address is not in use, the currently obtained redundant resource address of the first obtaining unit 401 can be used for programming operations. At this time, the latching unit 402 latches the redundant resource address to facilitate obtaining the redundant resource address in subsequent redundant repair operations. Specifically, when the first verification unit 403 determines that the redundant resource corresponding to the redundant resource address is not in use, it can send a first flag signal to the first obtaining unit 401 so that the first obtaining unit 401 outputs the received redundant resource address. At this time, the latching unit 402 latches any redundant resource address output by the first obtaining unit 401; or, when the first verification unit 403 determines that the redundant resource corresponding to the redundant resource address is not in use, it can send a first flag signal to the latching unit 402 so that the latching unit 402 latches the redundant resource address output by the first obtaining unit 401. At this time, the latching unit 402 only performs the latching action under the enabling condition of the first flag signal. In some embodiments, the address receiving module 301 further includes a second verification unit 404. The second verification unit 404 is connected to the first verification unit 403 and is configured to, before obtaining the next redundant resource address, determine whether the current redundant resource address is the last repair resource in the repair storage block, and in response to the current redundant resource address not being the last repair resource in the repair storage block, instruct the first obtaining unit 401 to obtain the next redundant resource address. The second verification unit 404 determines whether there are still unused repair resources in the repair storage block to perform programming operations to ensure the effective execution of the current redundant repair operation. It can be understood that when the first verification unit 403 verifies that the redundant resource corresponding to the current redundant resource address has been used, it sends the current redundant resource address to the second verification unit 404 so that the second verification unit 404 determines whether the current redundant resource address is the last repair resource in the repair storage block, or sends a second flag signal to the second verification unit so that the second verification unit 404 obtains at least partial information of one or more or all redundant resource addresses required to determine whether the current redundant resource address is the last repair resource in the repair storage block. In some embodiments, the second verification unit 404 is further configured to end the redundant repair operation in response to the current redundant resource address being the last repair resource in the repair storage block. By the second verification unit 404 determining that there is no repair resource in the repair storage block, the redundant repair operation is directly ended, avoiding the loop of the memory repeatedly obtaining the used repair resources, thereby avoiding the impact of the redundant repair operation on the normal working process of the memory.

[0116] As can be seen from the foregoing, the address receiving module 301 is used to obtain redundant resource addresses and failed addresses, and the first obtaining unit 401 in the address receiving module 301 is used to obtain redundant resource addresses. In some embodiments, the address receiving module 301 further includes a second obtaining unit 405, and the second obtaining unit 405 is configured to select a sampling mode based on a mode control signal and sample the failed address based on the sampling mode, where the sampling mode is used to configure the number of address bits for sampling the failed address once.

[0117] Reference Figure 7 , Figure 7 is a schematic structural diagram of the second obtaining unit provided in this embodiment. In some embodiments, it is assumed that the number of address bits of the failed address is N, and N is a positive integer. The second obtaining unit 405 includes: a shift driving circuit 410 configured to output a driving signal of N bits, and the driving signal carries a carry based on a clock signal; a sampling circuit 420 connected to the shift driving circuit 410 and receiving the failed address, configured to sample the corresponding bit of the failed address based on the corresponding bit of the driving signal; a mode control circuit 430 connected to the shift driving circuit 410, configured to add an initial working bit of the shift driving circuit based on the mode control signal.

[0118] It is assumed that the number of address bits of the failed address is 4. The driving signal output by the shift driving circuit 410 in the initial state is "0000", the driving signal output based on the first clock signal is "0001", the driving signal output based on the second clock signal is "0011", the driving signal output based on the third clock signal is "0111", and the driving signal output based on the fourth clock signal is "1111".

[0119] For the mode control circuit 430, if no mode control signal participates in the adjustment, the initial working bit of the shift driving circuit 410 defaults to the first bit, that is, the shift driving circuit 410 carries a carry backward in sequence based on the first bit; if a mode control signal participates in the adjustment, an initial working bit of the shift driving circuit 410 is added. For example, if the mode control signal controls the initial working bit in the driving signal to add the third bit. At this time, the driving signal output by the shift driving circuit 410 in the initial state is "0000", the driving signal output based on the first clock signal is "0101", and the driving signal output based on the second clock signal is "1111". After the mode control circuit 420 adds an initial working bit to the shift driving circuit 410, the sampling time of the second obtaining unit 405 for the failed address can be greatly shortened.

[0120] For the sampling circuit 420, in the above example, if the corresponding bit of the drive signal is "1", the sampling circuit samples the corresponding bit of the failure address. If all drive signals are "1", the sampling circuit completes the sampling of the failure address. It should be noted that the above example of performing sampling with the drive signal being "1" does not limit this embodiment.

[0121] Reference Figure 8 , Figure 8 is the schematic diagram of the specific circuit structure of the second acquisition unit given in this embodiment, as well as the corresponding working timing diagram. It should be noted that Figure 8 exemplarily illustrates when the number of address bits N = 4, which does not limit this embodiment.

[0122] In some embodiments, the shift drive circuit includes N cascaded D flip-flops, and the control terminal of each stage of D flip-flop is used to receive the clock signal Clk. In Figure 8 the example, N = 4, and the N D flip-flops are respectively the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, and the fourth flip-flop D4. The input terminal of the first flip-flop D1 is used to receive a high level, and the output terminal is used to output the first bit b<0> of the drive signal; the input terminal of the second flip-flop D2 is connected to the output terminal of the first flip-flop D1, and the output terminal is used to output the second bit b<1> of the drive signal; the input terminal of the third flip-flop D3 is connected to the output terminal of the second flip-flop D2, and the output terminal is used to output the third bit b<2> of the drive signal; the input terminal of the fourth flip-flop D4 is connected to the output terminal of the third flip-flop D3, and the output terminal is used to output the fourth bit b<3> of the drive signal. The first bit b<0>, the second bit b<1>, the third bit b<2>, and the fourth bit b<3> of the drive signal constitute the drive signal b<3:0>.

[0123] In some embodiments, the sampling circuit includes corresponding N sampling sub-circuits. The first input terminal of each sampling sub-circuit is used to receive the corresponding bit of the drive signal, and the second input terminal is used to receive the corresponding bit of the failure address, so as to realize sampling the corresponding bit of the failure address based on the corresponding bit of the drive signal. In Figure 8 the example, each sampling sub-circuit is set based on an AND logic structure, where the first input terminal of the AND logic structure is connected to the output terminal of the corresponding D flip-flop, and the second input terminal is used to receive the corresponding bit of the failure address. Specifically, the sampling circuit includes a first AND logic structure Y0, a second AND logic structure Y1, a third AND logic structure Y2, and a fourth AND logic structure Y3.

[0124] The first input terminal of the first AND logic structure Y0 is connected to the output terminal of the first flip-flop D1. The second input terminal is used to receive the first bit RA<0> of the failure address RA<3:0>. The output terminal outputs the first bit BA<0> of the sampling address BA<3:0>. The first input terminal of the second AND logic structure Y1 is connected to the output terminal of the second flip-flop D2. The second input terminal is used to receive the second bit RA<1> of the failure address RA<3:0>. The output terminal outputs the second bit BA<1> of the sampling address BA<3:0>. The first input terminal of the third AND logic structure Y2 is connected to the output terminal of the third flip-flop D3. The second input terminal is used to receive the third bit RA<2> of the failure address RA<3:0>. The output terminal outputs the third bit BA<2> of the sampling address BA<3:0>. The first input terminal of the fourth AND logic structure Y3 is connected to the output terminal of the fourth flip-flop D4. The second input terminal is used to receive the fourth bit RA<3> of the failure address RA<3:0>. The output terminal outputs the fourth bit BA<3> of the sampling address BA<3:0>.

[0125] In some embodiments, the mode control circuit is a selection circuit adaptively connected to the input terminal of the corresponding D flip-flop. One input terminal of the selection circuit is connected to the output terminal of the previous D flip-flop to form a cascaded circuit between D flip-flops. The other input terminal of the selection circuit receives a high level to add an initial working bit in the driving signal, without waiting for the high-level signal to be transmitted step by step based on the clock signal. In Figure 8 the example, the mode control circuit includes a selection circuit corresponding to the third flip-flop D3. The output terminal of the selection circuit is connected to the input terminal of the third flip-flop D3. The first input terminal of the selection circuit is connected to the output terminal of the second flip-flop D2. The second input terminal of the selection circuit is used to receive a high level.

[0126] The selection circuit selects to output the level of the first input terminal or the level of the second input terminal based on the mode control signal TM. If the mode control signal TM selects to output the level of the first input terminal at the output terminal, the initial working bit of the shift driving circuit is the first bit at this time, and the second acquisition unit completes the sampling of the failure address RA<3:0> based on 4 clock signals. If the mode control signal TM selects to output the level of the second input terminal at the output terminal, the initial working bits of the shift driving circuit are the first bit and the third bit at this time, and the second acquisition unit completes the sampling of the failure address RA<3:0> based on 2 clock signals.

[0127] In some embodiments, for an 8-bit failed address, the selection circuit can be adaptively connected to the input end of the fifth-stage flip-flop. When the selection circuit controls the initial working bits of the shift driving circuit to be the first bit and the fifth bit based on the mode control signal TM, the sampling time of the second acquisition unit for the failed address is halved; if the mode control circuit further includes connections corresponding to the third-stage flip-flop and the seventh-stage flip-flop, when the selection circuit controls the initial working bits of the shift driving circuit to be the first bit, the third bit, the fifth bit, and the seventh bit based on the mode control signal TM, the sampling time of the second acquisition unit for the failed address is reduced to 1 / 4.

[0128] In some embodiments, the address verification module 304 includes: a comparator, the first input end of the comparator receives the programmed address, and the second input end receives the failed address; the comparator is configured to output a trigger signal in response to the programmed address being the same as the failed address. The trigger signal is used to instruct the storage module to store the corresponding failed address.

[0129] Reference Figure 9 , Figure 9 is the structural schematic diagram of the address verification module provided in this embodiment. In some embodiments, the comparator 501 includes an exclusive-OR logic structure Q1. The first input end of the exclusive-OR logic structure Q1 receives the programmed address Fsbit_new, and the second input end of the exclusive-OR logic structure Q1 receives the failed address Row address. The output end of the exclusive-OR logic structure Q1 is used to output the trigger signal Match_result. It should be noted that for Figure 9 the shown exclusive-OR logic structure Q1, for an N-bit programmed address, there are N corresponding exclusive-OR logic structures Q1, and the outputs of the N exclusive-OR logic structures Q1 are OR-operated to output the trigger signal Match_result. Specifically, based on the working principle of the exclusive-OR logic structure Q1, if the programmed address Fsbit_new is different from the failed address Row address, the trigger signal Match_result is "1"; if the programmed address Fsbit_new is the same as the failed address Row address, the trigger signal Match_result is "0".

[0130] In some embodiments, the address verification module 304 further includes: a logic structure Q2, a first input terminal connected to the output terminal of the comparator 501 to receive the trigger signal Match_result, a second input terminal for receiving the indication signal Lastresourse, and the logic structure Q2 is configured to output a trigger signal in response to the effective indication signal, wherein the effective indication signal is used to characterize that the current redundant resource address is not the last repair resource in the repaired storage block. Specifically, when the current redundant resource address is not the last repair resource in the repaired storage block, the indication signal Last resourse is "1"; when the current redundant resource address is the last repair resource in the repaired storage block, the indication signal Last resourse is "0".

[0131] In some embodiments, there is also a comparison indication signal compare. When the memory compares the programmed address Fsbit_new and the failed address Row address, the comparison indication signal compare is at a high level. When Figure 9 The circuit needs to combine the judgment of the indication signal Last resourse. At this time, the comparison indication signal compare is used to sample the output signal of the logic structure Q2; when Figure 9 The circuit does not need to combine the judgment of the indication signal Last resourse. At this time, the comparison indication signal compare is used to sample the output signal of the exclusive-OR logic structure Q1.

[0132] Continue to refer to Figure 9 In some embodiments, the address verification module 304 further includes: a sampling flip-flop Q3, an input terminal D connected to the output terminal of the logic structure Q2 or the output terminal of the exclusive-OR logic structure Q1, a clock terminal clk for receiving the comparison indication signal compare, a reset terminal Reset for receiving the reset signal rst, and an output terminal for outputting a count enable signal ChangEn. Based on the foregoing, if the programmed address Fsbit_new is different from the failed address Row address and the current redundant resource address is not the last repair resource in the repaired storage block, the count enable signal ChangEn is "1" (the count enable signal is effective).

[0133] In some embodiments, the address verification module 304 further includes a counting unit 502, an input terminal connected to the output terminal of the logic structure Q2, and the counting unit 502 is configured to count the trigger signal to generate a counting signal, and the counting signal is used to calculate whether there is a remaining programming times for the current redundant repair operation.

[0134] Continue to refer to Figure 9, the address verification module 304 further includes a second AND logic structure Q4. The second AND logic structure Q4 is used to output a counting clock ChangClk according to a counting enable signal ChangEn and a comparison indication signal compare. Based on Figure 9 the logic of Figure 9 , the signal of the counting clock ChangClk is consistent with the counting enable signal ChangEn. A counting unit (Selfestcnt) Q5 counts based on the counting clock ChangClk to output a counting signal Cnt_over. The counting signal Cnt_over is used to calculate the number of differences between the programmed address Fsbit_new and the failed address Row address, combined with the time of a single fuse or the pre-stored maximum number of programming times, to determine whether there are remaining programming times for this redundancy repair operation.

[0135] In some embodiments, the reset terminal Reset of the counting unit 502 is further used to receive a reset signal rst. If the memory starts to perform a redundancy repair operation each time, or when ending the current redundancy repair operation, the reset signal rst is provided to reset the counting signal Cnt_over.

[0136] In summary, in the redundancy repair circuit 300 provided in this embodiment, the enable module 302 determines whether there are remaining programming times for this redundancy repair operation to ensure that the redundancy repair operation can be successfully executed; the address verification module 304 reads and judges the programmed address after the programming operation to ensure that the address programmed into the redundant resource is the failed address, so as to determine whether the failed word line can be effectively repaired.

[0137] It should be noted that, without conflict, the features disclosed in the redundancy repair circuit provided in the above embodiments can be randomly combined to obtain a new embodiment of the redundancy repair circuit.

[0138] Another embodiment of the present disclosure further provides a memory. The memory performs a redundancy repair operation based on the redundancy repair method provided in the above embodiment, or the memory includes the redundancy repair circuit provided in the above embodiment.

[0139] In some embodiments, the memory may be a storage unit or device based on semiconductor devices or components. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0140] In some embodiments, the memory provided by the present application can be applied to storage devices, smart phones, computers, tablets, artificial intelligence devices, wearable devices or mobile power supplies.

[0141] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the detailed descriptions of other embodiments above, and details will not be repeated here.

[0142] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present application. Such modifications, improvements and corrections are proposed in the present application, so such modifications, improvements and corrections still fall within the spirit and scope of the exemplary embodiments of the present application.

[0143] The above has introduced in detail a redundancy repair method, a redundancy repair circuit and a memory provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be understood as a limitation to the present application.

Claims

1. A redundant repair method, characterized in that, Including: Obtaining redundant resource addresses and invalid addresses; Determining whether there is a remaining programming count for the current redundant repair operation, and generating a programming indication signal in response to the existence of the remaining programming count for the current redundant repair operation; Programming the redundant resource corresponding to the redundant resource address based on the programming indication signal and the invalid address; Reading the programmed address after programming the redundant resource corresponding to the redundant resource address; Determining whether the programmed address is the same as the invalid address, and storing the invalid address in a local register in response to the programmed address being the same as the invalid address.

2. The redundant repair method according to claim 1, wherein Also including: Ending the redundant repair operation in response to the non-existence of the remaining programming count for the current redundant repair operation.

3. The redundant repair method according to claim 1, wherein The method for obtaining the redundant resource address includes: obtaining the redundant resource address in a repair storage block; Determining whether the redundant resource corresponding to the redundant resource address is in use; In response to the redundant resource not being in use, using the redundant resource corresponding to the currently obtained redundant resource address as the redundant resource to be programmed.

4. The redundant repair method according to claim 3, wherein Also including: In response to the redundant resource being in use, obtaining the next redundant resource address in the repair storage block.

5. The redundant repair method according to claim 3, wherein The method for determining whether the redundant resource corresponding to the redundant resource address is in use includes: determining whether the redundant resource is in use based on the flag bit corresponding to the redundant resource address, or determining whether the redundant resource is in use based on the current data state of the redundant resource corresponding to the redundant resource address.

6. The redundant repair method according to claim 3, wherein Also including: In response to the programmed address being different from the invalid address, obtaining the next redundant resource address, where the next redundant resource address is used to re-execute the redundant repair operation.

7. The redundant repair method according to claim 4 or 6, characterized in that, Before obtaining the next redundant resource address, the redundant repair method further includes: Determining whether the current redundant resource address is the last repair resource in the repair storage block; In response to the current redundant resource address not being the last repair resource in the repair storage block, obtaining the next redundant resource address.

8. The redundant repair method according to claim 7, wherein Also including: Ending the redundant repair operation in response to the current redundant resource address being the last repair resource in the repair storage block.

9. A redundant repair circuit, characterized in that, Including: An address receiving module configured to obtain redundant resource addresses and invalid addresses; An enabling module configured to determine whether there is a remaining programming count for the current redundant repair operation, and output a programming indication signal in response to the existence of the remaining programming count for the current redundant repair operation; A programming module connected to the address receiving module and the enabling module; The programming module is configured to program the redundant resource corresponding to the redundant resource address based on the programming indication signal and the invalid address; An address verification module configured to read the programmed address after programming the redundant resource corresponding to the redundant resource address, and determine whether the programmed address is the same as the invalid address; A storage module configured to store the invalid address in response to the programmed address being the same as the invalid address.

10. The redundant repair circuit according to claim 9, wherein The address receiving module includes: A first obtaining unit configured to obtain the redundant resource address in a repair storage block; The first verification unit is connected to the first acquisition unit; the first verification unit is configured to determine whether the redundant resource corresponding to the redundant resource address is used, and in response to the redundant resource not being used, use the redundant resource corresponding to the currently acquired redundant resource address as the redundant resource to be programmed.

11. The redundant repair circuit according to claim 10, wherein The first verification unit is further configured to, in response to the redundant resource being used, instruct the first acquisition unit to acquire the next redundant resource address in the repair storage block and determine whether the redundant resource corresponding to the next redundant resource address is used.

12. The redundant repair circuit according to claim 10, wherein The address receiving module is further configured to, in response to the programming address being different from the failure address, acquire the next redundant resource address, and the next redundant resource address is used to re-perform the redundant repair operation.

13. The redundant repair circuit according to claim 11 or 12, wherein The address receiving module further includes: a second verification unit connected to the first verification unit; the second verification unit is configured to, before acquiring the next redundant resource address, determine whether the current redundant resource address is the last repair resource in the repair storage block, and in response to the current redundant resource address not being the last repair resource in the repair storage block, instruct the first acquisition unit to acquire the next redundant resource address.

14. The redundant repair circuit according to claim 9, wherein The address verification module includes: a comparator, a first input terminal receives the programming address, and a second input terminal receives the failure address; the comparator is configured to, in response to the programming address being the same as the failure address, output a trigger signal, and the trigger signal is used to instruct the storage module to store the corresponding failure address.

15. The redundant repair circuit according to claim 14, wherein The comparator includes: an exclusive OR logic structure, a first input terminal of the exclusive OR logic structure receives the programming address, a second input terminal of the exclusive OR logic structure receives the failure address, and an output terminal of the exclusive OR logic structure is used to output the trigger signal.

16. The redundant repair circuit according to claim 14, wherein The address verification module further includes: an AND logic structure, a first input terminal is connected to the output terminal of the comparator, a second input terminal is used to receive an indication signal, and an output terminal is used to output the trigger signal, and the indication signal is used to represent whether the current redundant resource address is the last repair resource in the repair storage block.

17. The redundant repair circuit according to any one of claims 16, characterized in that, The address verification module further includes: a counting unit, an input terminal is connected to the output terminal of the AND logic structure; the counting unit is configured to count the trigger signal to generate and output a counting signal, and the counting signal is used to calculate whether there is a remaining programming count for this redundant repair operation.

18. The redundant repair circuit according to claim 10, wherein The address receiving module further includes: a second acquisition unit configured to select a sampling mode based on a mode control signal and perform address sampling on the failure address based on the selected sampling mode, where the sampling mode is used to configure the number of address bits for sampling the failure address once.

19. The redundant repair circuit according to claim 18, wherein The number of address bits of the failure address is N, where N is a positive integer, and the second acquisition unit includes: a shift driving circuit configured to output a driving signal of N bits, and the driving signal is carried based on a clock signal; A sampling circuit, connected to the shift driving circuit and receiving a failure address, is configured to sample corresponding bits of the failure address based on corresponding bits of the driving signal; A mode control circuit, connected to the shift driving circuit, is configured to add initial working bits of the shift driving circuit based on a mode control signal.

20. A memory, characterized in that, The memory performs a redundant repair operation based on the redundant repair method according to any one of claims 1 to 8, or the memory includes the redundant repair circuit according to any one of claims 9 to 19.

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