Test board card, test method and test system

Abstract

The embodiment of the invention provides a test board card, a test method and a test system. The test board card is connected with an external chip and a target analysis instrument. The external chip is used for sending an initial signal and a clock to the tested memory and the test board card; the test board card is configured to receive an initial signal and a clock sent by an external chip; performing frequency reduction on the initial signal and the clock to obtain a target signal and a target clock, and sending the target signal and the target clock to a target analysis instrument; wherein the frequency reduction processing enables the target signal and the target clock to meet the sampling rate range of the target analysis instrument, and the sampling data rate of the target analysis instrument is lower than the data rate of the tested memory when the tested memory works.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a test board, a test method, and a test system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. As a standard device, DRAM is used in conjunction with various different System on Chip (SOC). When compatibility issues occur between DRAM and SOC, it is usually necessary to analyze the command sequence of SOC.

[0003] Currently, a logic analyzer can be used to capture the command sequence between SOC and DRAM for analysis. However, there is a problem of mismatch between the clock frequency and data rate supported by the logic analyzer and SOC and DRAM, which may lead to capture failure.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] Embodiments of the present disclosure provide a test board, a test method, and a test system.

[0006] In a first aspect, embodiments of the present disclosure provide a test board that is respectively connected to an external chip and a target analysis instrument; the external chip is used to send an initial signal and a clock to the memory under test and the test board.

[0007] The test board is configured to: receive the initial signal and the clock sent by the external chip; reduce the frequency of both the initial signal and the clock to obtain a target signal and a target clock, and send the target signal and the target clock to the target analysis instrument.

[0008] Wherein, the frequency reduction process enables the target signal and the target clock to meet the samplable rate range of the target analysis instrument, and the samplable data rate of the target analysis instrument is lower than the data rate when the memory under test operates.

[0009] In some embodiments, the test board includes:

[0010] An RCD module, configured to receive the initial signal and the clock, drive and slow down the initial signal to obtain the target signal and send it to the target analysis instrument; and drive the clock to obtain an enhanced clock and send it to a frequency division circuit;

[0011] The frequency division circuit is configured to receive the enhanced clock, perform frequency division processing on the enhanced clock to obtain the target clock and send it to the target analysis instrument.

[0012] In some embodiments, the RCD module receives the initial signal in parallel through a first number of pins, and the RCD module outputs the target signal in parallel through a second number of pins, where the second number is greater than the first number.

[0013] In some embodiments, the test board further includes: a power management module, connected to the RCD module, for providing a stable power supply to the RCD module.

[0014] In some embodiments, the RCD module is connected to a configuration device based on the Inter-Integrated Circuit (I2C) bus, and the configuration device configures the RCD module through an I2C interface.

[0015] In some embodiments, the test board and the external chip communicate based on a first data channel and a second data channel; the frequency division circuit includes a first frequency division circuit corresponding to the first data channel and a second frequency division circuit corresponding to the second data channel; the test board further includes a first test interface corresponding to the first data channel and a second test interface corresponding to the second data channel;

[0016] The RCD module is configured to receive the initial signal and / or the clock through the first data channel or the second data channel;

[0017] The RCD module and the first frequency division circuit are connected to the target analysis instrument through the first test interface;

[0018] The RCD module and the second frequency division circuit are connected to the target analysis instrument through the second test interface.

[0019] In some embodiments, the RCD module includes:

[0020] A clock enhancement circuit, configured to receive the clock, drive the clock to obtain the enhanced clock;

[0021] A command amplification circuit, configured to receive the initial signal, perform amplification processing and logic processing on the initial signal, and sample the initial signal using the enhanced clock to obtain the target signal.

[0022] In some embodiments, the frequency division circuit includes:

[0023] A counting circuit, configured to receive the enhanced clock, count according to the enhanced clock, and send the count value to a comparison circuit;

[0024] The comparison circuit is configured to output a comparison signal according to the count value. Wherein, the comparison circuit determines whether the count value meets a preset frequency division condition, and when the preset frequency division condition is met, the comparison signal flips;

[0025] A sampling circuit, configured to receive the enhanced clock and the comparison signal, and sample the comparison signal based on the enhanced clock to obtain the target clock.

[0026] In some embodiments, the target analysis instrument includes a logic analyzer and / or a protocol analyzer.

[0027] In some embodiments, the memory under test is an RDIMM.

[0028] In some embodiments, the initial signal is a CA sequence.

[0029] In a second aspect, embodiments of the present disclosure provide a testing method, which is applied to the test board as described in any item of the first aspect. The method includes:

[0030] Receiving the initial signal and the clock sent by the external chip;

[0031] Reducing the frequency of both the initial signal and the clock to obtain a target signal and a target clock;

[0032] Sending the target signal and the target clock to the target analysis instrument;

[0033] Wherein, the frequency reduction process enables the target signal and the target clock to meet the sampleable rate range of the target analysis instrument, and the sampleable data rate of the target analysis instrument is lower than the data rate when the memory under test operates.

[0034] In a third aspect, embodiments of the present disclosure provide a testing system, including: an external chip, a memory under test, a target analysis instrument, and the test board as described in any item of the first aspect;

[0035] The external chip is configured to send an initial signal and a clock to the memory under test and the test board;

[0036] The test board is configured to process the initial signal and the clock into the target signal and the target clock and then send them to the target analysis instrument;

[0037] The target analysis instrument is used to perform signal analysis based on the target signal and the target clock. In some embodiments, the test system further includes a motherboard; both the test board card and the external chip are connected to the motherboard.

[0038] In some embodiments, the memory under test is connected to the test board card through a gold finger. The initial signal and the clock sent by the external chip reach the memory under test through the motherboard and the test board card in sequence. The initial signal and the clock sent by the external chip reach the target analysis instrument through the motherboard and the test board card in sequence.

[0039] Embodiments of the present disclosure provide a test board card, a test method, and a test system. The test board card is configured to: receive an initial signal and a clock sent by an external chip; down-convert both the initial signal and the clock to obtain a target signal and a target clock, and send the target signal and the target clock to a target analysis instrument; wherein, the down-conversion process enables the target signal and the target clock to meet the samplable rate range of the target analysis instrument, and the samplable data rate of the target analysis instrument is lower than the data rate when the memory under test operates. In this way, for a high-speed command sequence, by down-converting the signal, the signal can fall within the support range of the target analysis instrument, realizing the capture and analysis of high-speed signals using a low-speed target analysis instrument, and avoiding the expensive cost of designing and developing a new analysis instrument that meets the requirements. Description of the Drawings

[0040] Figure 1 Schematic diagram of a test system provided by an embodiment of the present disclosure Figure 1 ;

[0041] Figure 2 Schematic diagram of a test system provided by an embodiment of the present disclosure Figure 2 ;

[0042] Figure 3 Schematic diagram of a test system provided by an embodiment of the present disclosure Figure 3 ;

[0043] Figure 4 Schematic diagram of signal comparison provided by an embodiment of the present disclosure;

[0044] Figure 5 Exemplary circuit schematic diagram of an RCD and a frequency division circuit provided by an embodiment of the present disclosure;

[0045] Figure 6 Schematic diagram of a test system provided by an embodiment of the present disclosure Figure 4 。 Detailed Embodiments

[0046] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than limiting the disclosure. Additionally, it should be noted that for the sake of convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0048] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0049] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0050] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure will be described. The nouns and terms involved in the embodiments of the present disclosure are applicable to the following explanations:

[0051] Dynamic Random Access Memory (DRAM);

[0052] System on Chip (SOC);

[0053] Command sequence;

[0054] Double Data Rate (DDR);

[0055] Command / Address (CA);

[0056] Megabits per second (Mbps);

[0057] Gigahertz (GHz);

[0058] Dual Inline Memory Modules (DIMM);

[0059] Registered Dual In-line Memory Module (RDIMM);

[0060] Logic Analyzer (LA);

[0061] Protocol Analyzer (PA);

[0062] Printed Circuit Board (PCB);

[0063] Register Clock Driver (RCD);

[0064] Power Management Integrated Circuit (PMIC);

[0065] Inter-Integrated Circuit Bus;

[0066] Universal Serial Bus (USB);

[0067] Decision Feedback Equalization (DFE);

[0068] D Flip-Flop (DFF);

[0069] Data Strobe (DQS);

[0070] Input / Output path (IO path).

[0071] DRAM, as a standard device, can be used with various different SOCs. Although the protocols and state machines of DRAM interfaces are usually standard, when the memory controller of the SOC accesses the DRAM, the command sequences vary greatly.

[0072] When compatibility issues occur between DRAM and SOC (such as read / write failures, read / write data errors, etc.), it is usually necessary to analyze the command sequence sent by the SOC to find the differences between different SOCs. The prerequisite for analyzing the command sequence is to collect the command sequence, and how to accurately and low-costly obtain the command sequence becomes the key issue in the entire analysis process. In the design and improvement of chips, it is usually necessary to understand how the SOC applies DRAM to better focus on some circuits; and it is also necessary to measure the command sequence sent by the SOC to the DRAM for problem debugging, granular power consumption decomposition, etc., and there is also a need to capture the command sequence.

[0073] See Figure 1 , which shows a schematic diagram of a test system capable of capturing command sequences provided by an embodiment of the present disclosure Figure 1 . As Figure 1 shown, the test system consists of an SOC, a mother board, an interposer, DRAM, a logic analyzer, and a protocol analyzer. The mother board connects the SOC and the interposer, and the traces of the interposer can be connected to the measurement points of the DRAM. During the test, the SOC sends signals to the DRAM through the mother board. At the same time, the signals will be collected by the interposer and sent to the logic analyzer and the protocol analyzer for relevant analysis.

[0074] As the data rate of DRAM is getting higher and higher, the following problems exist in this test system: The protocol analyzer supports a maximum of DDR5 6400Mbps. Since only the CA signal is measured, the actual rate is 3200Mbps; The logic analyzer theoretically supports a maximum of 8000+Mbps. However, due to reasons such as signal quality, the actual maximum supported rate is only 6400Mbps, and since only the CA signal is measured, the actual rate is 3200Mbps; The logic analyzer supports a maximum clock frequency of 2.5GHz.

[0075] That is to say, when the rate of DRAM is higher than 6400Mbps, it exceeds the rate range supported by the protocol analyzer and the logic analyzer, and the protocol analyzer and the logic analyzer will not be able to successfully capture the high-speed signals, thus unable to analyze the signals. And if a new design and production are carried out, the cost will be expensive and too high.

[0076] Based on this, embodiments of the present disclosure provide a test board and a test system including the test board. The test board is respectively connected to an external chip and a target analysis instrument. The external chip is used to send an initial signal and a clock to the memory under test and the test board. The test board is configured to: receive the initial signal and the clock sent by the external chip; reduce the frequency of both the initial signal and the clock to obtain a target signal and a target clock, and send the target signal and the target clock to the target analysis instrument. Among them, the frequency reduction process enables the target signal and the target clock to meet the samplable rate range of the target analysis instrument, and the samplable data rate of the target analysis instrument is lower than the data rate when the memory under test operates.

[0077] In this way, for a high-speed command sequence, by reducing the frequency of the signal, the signal can fall within the support range of the target analysis instrument, enabling the use of a low-speed target analysis instrument to capture and analyze high-speed signals, avoiding the high cost of designing and developing a new analysis instrument that meets the requirements.

[0078] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0079] In one embodiment of the present disclosure, refer to Figure 2 , which shows a schematic diagram of a test system provided by an embodiment of the present disclosure Figure 2 . As Figure 2 shown, the test system includes: an external chip 10, a memory under test 20, a test board 30, and a target analysis instrument 40;

[0080] The external chip 10 is used to send an initial signal and a clock to the memory under test 20 and the test board 30;

[0081] The test board 30 is respectively connected to the external chip 10 and the target analysis instrument 40, and is used to process the initial signal and the clock into a target signal and a target clock and then send them to the target analysis instrument 40;

[0082] The target analysis instrument 40 is used to perform signal analysis based on the target signal and the target clock.

[0083] The test board 30 is configured to: receive the initial signal and the clock sent by the external chip 10; reduce the frequency of both the initial signal and the clock to obtain a target signal and a target clock, and send the target signal and the target clock to the target analysis instrument 40;

[0084] Among them, the frequency reduction process enables the target signal and the target clock to meet the samplable rate range of the target analysis instrument 40, and the samplable data rate of the target analysis instrument 40 is lower than the data rate when the memory under test 20 operates.

[0085] It should be noted that, in the embodiments of the present disclosure, the external chip 10 may be a SOC, and the memory under test 20 may be a RDIMM, specifically, a DRAM chip in the RDIMM, such as a DDR5 chip. The initial signal may be a command address CA sequence. For example, the initial signal is a command sequence, where the command sequence may refer to a sequence of commands issued by the SOC within an operation cycle, and may be a linear queue formed by splicing several commands in sequence. The target analysis instrument 40 may include a logic analyzer and / or a protocol analyzer. Among them, the logic analyzer can be used to capture and display the real-time high and low level changes of multiple digital signals, helping to analyze the timing relationship, such as the rise time, fall time, pulse width, signal delay, glitch, etc. of the signal, so as to verify whether the read and write timing between the SOC and the memory meets the specifications. The protocol analyzer can then check whether the data exchange is carried out correctly according to the provisions of the protocol.

[0086] It should also be noted that the sampleable data rate of the target analysis instrument 40, that is, the maximum sampling rate of the target analysis instrument 40. If the data rate exceeds this maximum sampling rate, the target analysis instrument 40 will not be able to sample data.

[0087] As described above, the sampleable data rate of the target analysis instrument 40 is lower than the data rate when the memory under test 20 is working, that is, lower than the data rate of the signal sent by the external chip 10, resulting in the target analysis instrument 40 being unable to capture the high-speed initial signal sent by the external chip 10, and thus unable to perform analysis. To solve this problem, the embodiments of the present disclosure perform a downsampling process on the high-speed signal sent by the external chip 10 through the test board 30. Specifically, it can be a downsampling or frequency division process on the high-frequency clock sent by the external chip 10, and a downspeed process on the high-speed signal, so that the rate and frequency of the processed signal fall within the sampleable frequency range and rate range of the target analysis instrument 40, and then the signal can be captured by the target analysis instrument 40 for analysis. Among them, the test board 30 is usually a PCB board.

[0088] Assume that the maximum sampling rate supported by the target analysis instrument 40 is 6400 Mbps, and the maximum supported clock frequency is 2.5 GHz. That is, if the frequency of the clock exceeds 2.5 GHz or the rate of signals such as CA exceeds 6400 Mbps, the target analysis instrument 40 will not be able to perform sampling analysis. Assume that the clock frequency sent by the external chip 10 is 3.6 GHz. Due to double data rate, the rate of the initial signal is 7200 Mbps. The clock frequency and the rate of the initial signal exceed the range supported by the target analysis instrument 40. The test board 30 reduces the frequency of the clock and the rate of the initial signal. For example, the clock frequency is reduced from 3.6 GHz to 1.8 GHz, and the data rate of the initial signal is reduced from 7200 Mbps to 3600 Mbps, so that the obtained target clock and target signal fall within the range of the target analysis instrument 40, so that the target analysis instrument 40 can capture the target signal and perform analysis.

[0089] In this way, when there are compatibility issues between the DRAM and the SOC, for high-speed command sequences, by reducing the frequency of the commands and the speed of the clock, the low-speed target analysis instrument 40 is used to capture and analyze the high-speed command sequences. It avoids the expensive cost of designing and developing a new logic analyzer / protocol analyzer that meets the requirements.

[0090] It can be seen that the logic analyzer / protocol analyzer cannot capture high-speed signals. If the logic analyzer / protocol analyzer is still used as the measurement device, at least the following problems need to be solved: The logic analyzer supports a maximum CK of 2.5 GHz and does not support higher-frequency clocks; currently, the logic analyzer supports a maximum product rate of 6400 Mbps and does not support higher-speed data. And the embodiment of the present disclosure uses the test board 30 to reduce the speed and frequency of the data and the clock. In this way, when the DRAM rate is higher than 6400 Mbps, in the case where the logic analyzer and the protocol analyzer are unavailable, through the solution provided by the embodiment of the present disclosure, the command sequence sent by the SOC to the DRAM can still be obtained. It can be applied to products such as DDR5 7200 and 8800 Mbps (CA rate is 3600 Mbps and 4400 Mbps).

[0091] In some embodiments, refer to Figure 3 , which shows a schematic diagram of a test system provided by an embodiment of the present disclosure Figure 3 . As Figure 3 shown, the test board 30 includes:

[0092] The RCD module 301 is configured to receive the initial signal CA1 and the clock CK1, drive and reduce the speed of the initial signal CA1 to obtain the target signal CA2 and send it to the target analysis instrument 40; and drive the clock CK1 to obtain the enhanced clock CK2 and send it to the frequency division circuit 302;

[0093] The frequency division circuit 302 is configured to receive the enhanced clock CK2, perform frequency division processing on the enhanced clock CK2, and send the obtained target clock CK3 to the target analysis instrument 40.

[0094] It should be noted that, in Figure 3 , the external chip 10 is an SOC, the memory under test 20 is an RDIMM, and the target analysis instrument 40 is a logic analyzer (LA).

[0095] It should also be noted that the RCD module 301, namely the register clock driver RCD, is a key component for timing control in digital circuits. Typical application scenarios of the RCD include DDR4 / DDR5 memory modules, such as RDIMM or LRDIMM, which can implement functions such as signal driving and synchronization. The RCD receives the clock and CA signal from the memory controller, buffers and amplifies them, and then distributes them to all DRAM chips of the memory module to ensure timing synchronization and signal integrity. In the embodiments of the present disclosure, the RCD is applied to the test board 30, and the clock CK1 is optimally driven through the driving and signal distribution capabilities of the RCD, and the initial signal CA1 is optimally driven and decelerated to match the rate range of the target analysis instrument 40.

[0096] As Figure 3 shown, still assuming that the frequency of the clock CK1 is 3.6 GHz and the rate of the initial signal CA1 is 7200 Mbps, the RCD module 301 decelerates the initial signal CA1 to obtain the target signal CA2 with a rate of 3600 Mbps. At the same time, the driving is enhanced to ensure that the signal quality of the target signal CA2 sent to the target analysis instrument 40 is not affected by the processing process, and to avoid the adverse impact on the analysis caused by the deterioration of the signal quality. As shown by the arrow ① in Figure 3 , through the driving (Re-Driver) of the RCD module, the eye diagram of the signal is enlarged, effectively avoiding information loss.

[0097] It should also be noted that the way for the RCD module 301 to decelerate the initial signal CA1 to obtain CA2 can be: the RCD module 301 receives the initial signal CA1 in parallel through the first number of pins, and the RCD module 301 outputs the target signal in parallel through the second number of pins, and the second number is greater than the first number.

[0098] For example: assume that the first number is 7 and the second number is 14. As Figure 4As shown, 00 to 13 therein represent different command signals. The numbers are only used for distinction as numbers and have no actual meaning. The initial signal CA1 includes 7 parallel sub-signals of CA1[0], CA1[1]... CA1[6], which are combined and denoted as CA1[0:7]. CA1[0:7] are respectively transmitted into the RCD module 301 through 7 input pins. The data transmission sequence is parallel input of 00 to 06, parallel input of 07 to 13,...; after being processed by the RCD module 301, the obtained target signal CA2 includes 14 parallel sub-signals of CA2[0], CA2[1]... CA2

[13] , which are combined and denoted as CA2[0:13]. CA2[0:13] are respectively transmitted out from the RCD module 301 through 14 output pins. The data transmission sequence is parallel output of 00 to 13,...

[0099] Compared with the initial signal CA1, the number of parallel transmissions of the target signal CA2 has doubled, so the rate can be halved. That is, before entering the RCD module 301, 7 parallel sub-signals are transmitted at a high speed (such as 7200 Mbps). After being processed by the RCD module 301, 14 parallel sub-signals are transmitted at a low speed (such as 3600 Mbps). Although the data transmission rate of each sub-signal is reduced, the number of parallel transmissions increases, which will not have an adverse impact on the actual data transmission.

[0100] It should also be noted that based on the working principle of the RCD, it usually does not reduce the frequency of the clock CK1, but can optimize the drive of the clock CK1 to enhance the drive ability of the clock. The clock enhanced by the RCD module 301 is denoted as the enhanced clock CK2. The frequency of the enhanced clock CK2 is still 3.6 GHz, but the drive ability is stronger. Then, the frequency division circuit 302 can perform frequency division processing on the enhanced clock CK2. For example Figure 3 perform frequency division by two in it, that is, the frequency of the target clock CK3 is one-half of the frequency of the enhanced clock CK2, and the obtained target clock CK3 has a frequency of 1.8 GHz.

[0101] Such as Figure 3 As indicated by the arrow ② in it, compared with the clock CK1 and the initial signal CA1 sent by the SOC, the frequency of the target clock CK3 received by the LA is halved, the rate of the target signal CA2 is halved, and the eye diagram is enlarged. Thus, the signal quality is not damaged and will not be distorted, and the LA can perform relevant analysis.

[0102] In some embodiments, as Figure 3 shown, the test board 30 may further include:

[0103] A power management module 303, connected to the RCD module 301, for providing a stable power supply for the RCD module 301.

[0104] It should be noted that the power management module 303 can specifically be a PMIC, which is responsible for power conversion, distribution, monitoring, and optimization. It can convert the input voltage into the voltages required by different loads through buck, boost, or buck-boost circuits. In the embodiments of the present disclosure, it can provide a stable power supply of, for example, 1.1V for the RCD module 301, ensuring that the RCD module 301 operates stably and normally under the stable power supply.

[0105] In some embodiments, as Figure 5 shown, the RCD module 301 is connected to the configuration device based on I2C, and the configuration device configures the RCD module through the I2C interface.

[0106] It should be noted that I2C is a two-wire synchronous serial bus for short-distance communication, and only two wires are required to transmit information between the devices connected to the bus. In the embodiments of the present disclosure, the configuration device is an external device for configuring the RCD module 301. The specific configuration content can include the relevant configuration of the registers inside the RCD module 301 to ensure that the RCD module 301 operates as required. Furthermore, the plug-and-play configuration can be achieved through the I2C to USB interface, further increasing the convenience.

[0107] Exemplarily, refer to Figure 5 , which shows an exemplary structural schematic diagram of an RCD module and a frequency division circuit provided by the embodiments of the present disclosure. As Figure 5 shown, in some embodiments, the RCD module 301 includes:

[0108] A clock enhancement circuit 3011, configured to receive a clock CK1, drive the clock CK1, and obtain an enhanced clock CK2;

[0109] A command amplification circuit 3012, configured to receive an initial signal CA1, perform amplification processing and logic processing on the initial signal CA1, and sample the initial signal CA1 using the enhanced clock CK2 to obtain a target signal CA2.

[0110] It should be noted that the clock enhancement circuit 3011 can specifically be a clock generation circuit (Clock Generation Circuits), and the clock generation circuit can generate stable and accurate clock signals. The clock enhancement circuit 3011 can include or incorporate an oscillator, a phase-locked loop, etc., but is not limited thereto. In the embodiments of the present disclosure, the clock enhancement circuit 3011 is used to optimize the drive of the clock CK1 to enhance its drive ability for further frequency division.

[0111] It should also be noted that the command amplification circuit 3012 is used to enhance and slow down the initial signal CA1. As Figure 5As shown, the command amplification circuit 3012 can be composed of an amplifier 501, a decision feedback equalization circuit (DFE) 502, a first flip-flop (DFF1) 502, a digital logic circuit 504, a second flip-flop (DFF2) 505, a buffer 506, etc. Through the processing of this series of circuits, the signal is enhanced.

[0112] Among them, VrefCA is a reference signal. The amplification circuit 501 amplifies the initial signal CA1 based on the reference signal VrefCA and then outputs it to the decision feedback equalization circuit 502. The DFE has functions such as suppressing signal interference and improving the stability of the receiving end. It eliminates various interferences through a feedback mechanism and improves the signal transmission quality.

[0113] The first flip-flop 503 and the second flip-flop 505 can both be DFFs. As Figure 5 shown, in the DFF, D represents the input terminal, CK represents the clock terminal, Q represents the positive-phase output terminal, represents the inverted output terminal. Both the first flip-flop 503 and the second flip-flop 505 can sample the input signal at the rising edge of the clock signal. In other types of flip-flops, the input signal can also be sampled at the falling edge of the clock signal, and no specific limitation is made in this regard. The digital logic circuit 504 is composed of various types of logic gates and is used to perform relevant logic processing on the signal to meet the required requirements. Finally, the buffer 506 further drives and enhances the signal to ensure the signal quality.

[0114] It should also be noted that Figure 5 the RCD module 301 in is a schematic diagram of a simplified RCD chip. The initial signal CA1 and the clock CK1, as input signals, are processed by the amplification circuit 501, the DFE circuit 502 in the RCD chip, and may also pass through a differential-to-single-ended circuit, and then are sampled by the clock signal CK1.1, then undergo digital logic processing, and then are sampled by the clock signal CK1.2 and output the target signal CA2, thereby realizing the amplification of the clock CK1 and the initial signal CA1. Among them, the clock signal CK1.1 and the clock signal CK1.2 are respectively the clocks provided to the first flip-flop 503 and the second flip-flop 505, and both the clock signal CK1.1 and the clock signal CK1.2 can be the same clock as the enhanced clock CK2.

[0115] As Figure 5 shown, in some embodiments, the frequency division circuit 302 includes:

[0116] A counting circuit 3021, which is used to receive the enhanced clock CK2 and perform counting according to the enhanced clock CK2 to obtain a count value and send it to the comparison circuit 3022;

[0117] A comparison circuit 3022 is configured to output a comparison signal according to a count value. The comparison circuit 3022 determines whether the count value meets a preset frequency division condition. When the preset frequency division condition is met, the comparison signal flips.

[0118] A sampling circuit 3033 is configured to receive an enhanced clock CK2 and the comparison signal, and sample the comparison signal based on the enhanced clock to obtain a target clock CK3.

[0119] It should be noted that the counting circuit 3021 can be a synchronous or asynchronous counter composed of cascaded DFFs, which can accumulate and count the rising edges of the input enhanced clock CK2, and send the obtained count value to the comparison circuit 3032.

[0120] The comparison circuit 3032 can be a comparator configured to compare the count value with a preset threshold. Here, the preset threshold is related to the required frequency division ratio. For example, the first threshold corresponds to a divide-by-two frequency division, and the second threshold corresponds to a divide-by-four frequency division (i.e., the frequency of the target clock CK3 is half of the frequency of the clock CK1). The preset frequency division condition can be that the count value is greater than the preset threshold. Whenever the count value is greater than the preset threshold, the output of the comparison circuit 3032 flips once. At the same time, the comparison circuit 3032 can also output a reset signal to the comparator when the comparison signal flips, so that the counting circuit 3031 restarts counting for comparison with the preset threshold by the comparison circuit 3032.

[0121] In this way, the comparison signal is actually a clock signal with a period, and its frequency is less than the enhanced clock CK2, specifically related to the preset threshold. The sampling circuit 3033 can be a DFF, which samples the comparison signal output by the comparison circuit 3022 using the enhanced clock CK2, realizes the timing alignment of the frequency-divided clock (i.e., the comparison signal) with the enhanced clock CK2, and improves the instability of the comparison signal for subsequent use by the target analysis instrument 40.

[0122] It should also be noted that in Figure 5 , this embodiment of the present disclosure provides a frequency division circuit 302 based on a counter (or clock frequency divider, CK Divider). The enhanced clock CK2 output by the RCD module 301 is sent as an input signal to the frequency division circuit 302 for clock frequency division to obtain the final required target clock CK3. In other embodiments, the enhanced clock CK2 can also be frequency-divided in any feasible manner, which is not specifically limited herein.

[0123] Further, referring to Figure 6 , which shows a schematic diagram of a test system provided by an embodiment of the present disclosure Figure 4 . As Figure 6 shown, in some embodiments, the test board 30 and the external chip 10 (Figure 6 communicates based on a first data channel CHA (Channel A) and a second data channel CHB (Channel B) (not shown in the figure); the frequency division circuit 302 includes a first frequency division circuit 302-1 corresponding to the first data channel CHA and a second frequency division circuit 302-2 corresponding to the second data channel CHB; the test board 30 further includes a first test interface 304 corresponding to the first data channel CHA and a second test interface 305 corresponding to the second data channel CHB;

[0124] The RCD module 301 is configured to receive an initial signal CA1 and / or a clock CK1 through the first data channel CHA or the second data channel CHB;

[0125] The RCD module 301 and the first frequency division circuit 302-1 are connected to the target analysis instrument 40 through the first test interface 304;

[0126] The RCD module 301 and the second frequency division circuit 302-2 are connected to the target analysis instrument 40 through the second test interface 305.

[0127] As Figure 6 shown, the test system may further include a motherboard 50; the test board 30 and the external chip 10 ( Figure 6 not shown in the figure) are both connected to the motherboard 50. With reference to Figure 1 , the SOC therein is the external chip 10, and the DRAM is the memory under test 20. As Figure 6 and Figure 1 shown, the initial signal CA1 and the clock CK1 sent by the external chip 10 reach the memory under test 20 through the motherboard 50 and the test board 30 in sequence, and the initial signal CA1 and the clock CK1 sent by the external chip 10 reach the target analysis instrument 40 through the motherboard 50 and the test board 30 in sequence.

[0128] It should be noted that the memory under test 20 can be an RDIMM. The test board 30 has a socket for inserting the memory under test 20, such as Figure 6 the RDIMM socket in

[0129] . During the test, the memory under test 20 is directly inserted into this socket. Based on the internal traces of the test board 30, the connection can be achieved, and then the test points can be led out. The memory under test 20 has a gold finger, and the connection with the test board 30 is realized by inserting the gold finger into the test board 30. The motherboard 50 also has a socket for inserting the test board 30. The test board 30 can also have a gold finger, and the connection is realized by inserting the gold finger into the corresponding socket of the motherboard 50. Figure 6As shown, there are two paths, path A (CHA) and path B (CHB). Path A includes a data path CHA DQ and a command address path CHA CA, and path B includes a data path CHB DQ and a command address path CHA CA. Additionally, it may also include Figure 6 a clock path, a data strobe (DQS) path, etc. not shown in Figure 6 . Here, only the Figure 6 partial structure shown in Figure 6 is taken as an example. Among them, a path is an IO path.

[0130] Corresponding to the two data paths, the connections between the test board 30 and the target analysis instrument 40 also pass through their respective test interfaces. As Figure 6 shown, the first data channel CHA corresponds to the first test interface 304. After the RCD module 301 processes the initial signal corresponding to the first data channel CHA into a target signal, it is sent to the target analysis instrument 40 through the first test interface 304. The RCD module 301 drives the clock corresponding to the first data channel CHA and sends it to the first frequency division circuit 302-1. The first frequency division circuit 302-1 performs frequency division according to the required frequency division ratio to obtain the corresponding target clock, and then sends it to the target analysis instrument 40 through the first test interface 304. The second data channel CHB corresponds to the second test interface 305. After the RCD module 301 processes the initial signal corresponding to the second data channel CHB into a target signal, it is sent to the target analysis instrument 40 through the second test interface 305. The RCD module 301 drives the clock corresponding to the second data channel CHB and sends it to the second frequency division circuit 302-2. The second frequency division circuit 302-2 performs frequency division according to the required frequency division ratio to obtain the corresponding target clock, and then sends it to the target analysis instrument 40 through the second test interface 305. Among them, the first test interface 304 and the second test interface 305 can both be soft touch (or low-invasive contact) interfaces to ensure signal integrity and improve the test yield.

[0131] In this way, for scenarios where the SOC issues a command sequence to the DRAM, etc., the embodiments of the present disclosure ensure the high-fidelity transmission of signals by accurately capturing signals such as command sequences on the IO path. The captured data such as clocks / commands is first optimized and driven by the RCD, so as to ensure that the data transmitted to the logic analyzer or protocol analyzer is not affected by signal quality. Given that the command rate of DDR5 RDIMM has reached 7200Mbps or higher, logic analyzers and protocol analyzers usually cannot directly decode it. Therefore, while this solution cleverly uses the RCD for signal driving, the command signal is divided in frequency to 3600Mbps (or 4400Mbps). This processing not only preserves the integrity of the data, but also enables the clock signal after being driven by the RCD to be further divided in frequency through a frequency division circuit for accurate analysis by the logic analyzer or protocol analyzer. In addition, a PMIC is also provided to supply a stable power of 1.1V to support the operation of the RCD, and the I2C interface is used to configure the RCD to ensure its operation in the best mode. Through this efficient and advanced solution, the analysis ability and signal processing accuracy for high-speed DDR5 memory systems are greatly improved.

[0132] In summary, the embodiments of the present disclosure provide a command capture solution that can be applied but is not limited to the DDR5 RDIMM IO path, which can be used for the measurement of DDR5 command sequences, such as the capture of command sequences of high-speed data (such as rates of 7200Mbps and 8800Mbps, or even higher) of DDR5 RDIMM. Based on the solution provided by the embodiments of the present disclosure, a low-speed target analysis instrument can successfully capture the high-speed command sequence data sent by the SOC to the DDR5 RDIMM.

[0133] Based on the foregoing test system and test board 30, the embodiments of the present disclosure also provide a test method applied to the test board 30, and the test method includes the following steps:

[0134] S701: Receive an initial signal and a clock sent by an external chip.

[0135] S702: Down-convert the initial signal and the clock to obtain a target signal and a target clock.

[0136] S703: Send the target signal and the target clock to a target analysis instrument.

[0137] It should be noted that this test method is implemented based on the foregoing test system and test board 30. For details not described in this embodiment, reference can be made to the description of the foregoing embodiments for understanding, and details will not be elaborated here.

[0138] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0139] It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including such element.

[0140] The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments.

[0141] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0142] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0143] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0144] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A test board, characterized in that, Connect to the external chip and the target analysis instrument respectively; the external chip is used to send an initial signal and a clock to the memory under test and the test board; The test board is configured to: receive the initial signal and the clock sent by the external chip; Reduce the frequency of both the initial signal and the clock to obtain a target signal and a target clock, and send the target signal and the target clock to the target analysis instrument; Wherein, the frequency reduction process enables the target signal and the target clock to meet the samplable rate range of the target analysis instrument, and the samplable data rate of the target analysis instrument is lower than the data rate when the memory under test operates.

2. The test board according to claim 1, wherein The test board includes: A register clock driver (RCD) module, configured to receive the initial signal and the clock, drive and slow down the initial signal to obtain the target signal and send it to the target analysis instrument; and drive the clock to obtain an enhanced clock and send it to a frequency division circuit; The frequency division circuit is configured to receive the enhanced clock, perform frequency division processing on the enhanced clock, and obtain the target clock and send it to the target analysis instrument.

3. The test board according to claim 2, wherein The RCD module receives the initial signal in parallel through a first number of pins, and the RCD module outputs the target signal in parallel through a second number of pins, and the second number is greater than the first number.

4. The test board according to claim 2, wherein The test board further includes: A power management module, connected to the RCD module, for providing a stable power supply for the RCD module.

5. The test board according to claim 2, wherein The RCD module is connected to a configuration device based on the Inter-Integrated Circuit (I2C) bus, and the configuration device configures the RCD module through the I2C interface.

6. The test board according to claim 2, characterized in that, The test board and the external chip communicate based on a first data channel and a second data channel; the frequency division circuit includes a first frequency division circuit corresponding to the first data channel and a second frequency division circuit corresponding to the second data channel; the test board further includes a first test interface corresponding to the first data channel and a second test interface corresponding to the second data channel; The RCD module is configured to receive the initial signal and / or the clock through the first data channel or the second data channel; The RCD module and the first frequency division circuit are connected to the target analysis instrument through the first test interface; The RCD module and the second frequency division circuit are connected to the target analysis instrument through the second test interface.

7. The test board according to claim 2, wherein The RCD module includes: A clock enhancement circuit, configured to receive the clock, drive the clock, and obtain the enhanced clock; A command amplification circuit, configured to receive the initial signal, perform amplification processing and logic processing on the initial signal, and sample it using the enhanced clock to obtain the target signal.

8. The test board according to claim 2, wherein The frequency division circuit includes: A counting circuit, configured to receive the enhanced clock, count according to the enhanced clock, and obtain a count value and send it to a comparison circuit; The comparison circuit is configured to output a comparison signal according to the count value. Wherein, the comparison circuit determines whether the count value meets a preset frequency division condition, and when the preset frequency division condition is met, the comparison signal is inverted; The sampling circuit is configured to receive the enhanced clock and the comparison signal, and sample the comparison signal based on the enhanced clock to obtain the target clock.

9. The test board according to any one of claims 1 to 8, characterized in that, The target analyzer includes a logic analyzer and / or a protocol analyzer.

10. The test board according to any one of claims 1 to 8, characterized in that, The memory under test is a dual in-line memory module with register (RDIMM).

11. The test board according to any one of claims 1 to 8, characterized in that, The initial signal is a command address (CA) sequence.

12. A testing method, characterized in that, Applied to the test board according to any one of claims 1 to 11, the method includes: Receiving the initial signal and the clock sent by the external chip; Reducing the frequency of both the initial signal and the clock to obtain a target signal and a target clock; Sending the target signal and the target clock to the target analyzer; Wherein, the frequency reduction process enables the target signal and the target clock to meet the sampleable rate range of the target analyzer, and the sampleable data rate of the target analyzer is lower than the data rate when the memory under test operates.

13. A test system, characterized in that, Including: An external chip, a memory under test, a target analyzer, and the test board according to any one of claims 1 to 11; The external chip is configured to send an initial signal and a clock to the memory under test and the test board; The test board is configured to process the initial signal and the clock into the target signal and the target clock and then send them to the target analyzer; The target analyzer is configured to perform signal analysis based on the target signal and the target clock.

14. The test system according to claim 13, wherein, The test system further includes a motherboard; both the test board and the external chip are connected to the motherboard.

15. The test system according to claim 14, characterized in that The memory under test is connected to the test board through a gold finger. The initial signal and the clock sent by the external chip reach the memory under test through the motherboard and the test board in sequence, and the initial signal and the clock sent by the external chip reach the target analyzer through the motherboard and the test board in sequence.

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