Semiconductor packaging structure

Abstract

A semiconductor package structure includes a substrate, a semiconductor chip, an interposer, a heat sink, and an adhesive layer. The semiconductor chip is disposed on the substrate. The interposer is disposed on the semiconductor chip and has a recess. The heat sink is embedded in the interposer and vertically overlaps the semiconductor chip. The bonding layer is arranged in the groove and is connected with the semiconductor chip and the radiating fin.

Description

Technical Field

[0001] The present invention relates to semiconductor packaging technology, and particularly to a semiconductor packaging structure. Background Art

[0002] Semiconductor packaging structures can not only provide protection for semiconductor chips to avoid the invasion of environmental pollutants, but also provide electrical connections between the semiconductor chips encapsulated therein and a substrate (such as a printed circuit board (PCB)). With the increasing demand for small devices capable of performing more functions, the package-on-package (PoP) technology has become increasingly popular. The PoP technology vertically stacks two or more packaging structures, thereby reducing the area occupied on the main board.

[0003] Although existing semiconductor packaging structures can generally meet the requirements, they are not satisfactory in some aspects. For example, if the heat generated during the operation of the semiconductor chip is not removed sufficiently, the increased temperature will cause damage to the semiconductor components. Heat dissipation is a key problem that needs to be solved because it affects the performance of the semiconductor packaging structure. Therefore, there is a need to further improve the semiconductor packaging structure. Summary of the Invention

[0004] A semiconductor packaging structure is provided. An exemplary embodiment of the semiconductor packaging structure includes a substrate, a semiconductor chip, an interposer, a heat sink, and an adhesive layer. The semiconductor chip is disposed on the substrate. The interposer is disposed on the semiconductor chip and has a groove. The heat sink is embedded in the interposer and vertically overlaps the semiconductor chip. The adhesive layer is disposed in the groove and connects the semiconductor chip and the heat sink.

[0005] In some embodiments, the semiconductor packaging structure further includes: a molding material that surrounds the semiconductor chip and the adhesive layer and extends into the groove.

[0006] In some embodiments, the semiconductor packaging structure further includes: a plurality of conductive structures disposed between the substrate and the interposer and surrounded by the molding material.

[0007] In some embodiments, a part of the conductive structure is disposed in the interposer.

[0008] In some embodiments, the conductive structure includes conductive pillars, solder balls, copper-core solder balls, or a combination thereof.

[0009] In some embodiments, the substrate includes a packaging substrate.

[0010] In some embodiments, the substrate includes a redistribution structure.

[0011] In some embodiments, the semiconductor package structure further includes: a plurality of thermal vias embedded in the interposer and thermally coupled to the heat sink.

[0012] Another exemplary embodiment of a semiconductor package structure includes a substrate, a semiconductor chip, an interposer, a heat sink, and a conductive structure. The semiconductor chip is disposed on the substrate. The interposer includes a first portion covering the semiconductor chip and a second portion connecting the first portion. The second portion is thicker than the first portion. The heat sink is disposed in the first portion of the interposer. The conductive structure is partially disposed in the second portion of the interposer and electrically couples the substrate and the interposer.

[0013] In some embodiments, the semiconductor package structure further includes: a plurality of thermal vias disposed in the first portion of the interposer and thermally coupled to the heat sink.

[0014] In some embodiments, the thermal vias and the heat sink are made of metal.

[0015] In some embodiments, a top surface of the thermal via is substantially aligned with a top surface of the first portion of the interposer and a top surface of the second portion of the interposer.

[0016] In some embodiments, a bottom surface of the heat sink is substantially aligned with a bottom surface of the first portion of the interposer.

[0017] In some embodiments, the semiconductor package structure further includes: an adhesive layer in contact with the semiconductor chip and the heat sink.

[0018] In some embodiments, the heat sink has a projected area that is substantially equal to or greater than that of the adhesive layer and / or the semiconductor chip.

[0019] Yet another exemplary embodiment of a semiconductor package structure includes a first redistribution structure, a semiconductor chip, an adhesive layer, a heat sink, a second redistribution structure, and a molding compound. The semiconductor chip is disposed on the first redistribution structure. The adhesive layer is disposed on the semiconductor chip. The heat sink is disposed on the adhesive layer and vertically overlaps the semiconductor chip. The second redistribution structure is disposed on the heat sink. The molding compound surrounds the semiconductor chip, the adhesive layer, and the heat sink.

[0020] In some embodiments, the semiconductor package structure further includes: a plurality of conductive structures thermally coupling the heat sink and the second redistribution structure and surrounded by the molding compound.

[0021] In some embodiments, the semiconductor package structure further includes: conductive pillars electrically coupling the first redistribution structure and the second redistribution structure and surrounded by the molding compound.

[0022] In some embodiments, the heat sink has a projected area larger than that of the adhesive layer and / or the semiconductor chip.

[0023] In some embodiments, the semiconductor package structure further includes: a plurality of conductive terminals disposed below the first redistribution structure; a plurality of conductive structures disposed between the semiconductor chip and the first redistribution structure; and an underfill material surrounding the plurality of conductive structures.

[0024] Those skilled in the art can undoubtedly understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the drawings. The detailed description will be given in the following embodiments with reference to the drawings. Description of the Drawings

[0025] The present invention can be more comprehensively understood by reading the subsequent detailed description and referring to the examples given in the drawings.

[0026] Figures 1A to 1C is a cross-sectional view of a semiconductor package structure at various manufacturing stages according to some embodiments of the present disclosure.

[0027] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure.

[0028] Figures 8A to 8B is a cross-sectional view of a semiconductor package structure at various manufacturing stages according to some embodiments of the present disclosure.

[0029] Figures 9A to 9B is a cross-sectional view of a semiconductor package structure at various manufacturing stages according to some embodiments of the present disclosure.

[0030] Figures 10A to 10C is a cross-sectional view of a semiconductor package structure at various manufacturing stages according to some embodiments of the present disclosure.

[0031] Figures 11A to 11B is a cross-sectional view of a semiconductor package structure at various manufacturing stages according to some embodiments of the present disclosure.

[0032] In the following detailed description, for the purpose of illustration, numerous specific details are set forth in order for those skilled in the art to more thoroughly understand the embodiments of the present invention. However, it is obvious that one or more embodiments can be implemented without these specific details, and different embodiments can be combined according to requirements and should not be limited to the embodiments listed in the drawings. Detailed Implementation Modes

[0033] The following description is of the preferred embodiments for implementing the present invention, which is only used to illustrate the technical features of the present invention and not to limit the scope of the present invention. Throughout the specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names to refer to the same element. Therefore, the specification and claims do not use the difference in names as a way to distinguish elements, but rather use the difference in the functions of elements as the basis for distinction. The terms "element", "system" and "device" used in the present invention may be entities related to a computer, where the computer may be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" mentioned in the following description and claims are open-ended terms and should be interpreted as meaning "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as being coupled to another device in the text, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0034] Wherein, unless otherwise indicated, corresponding numbers and symbols in different drawings of the various figures generally refer to corresponding parts. The drawn figures clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0035] This disclosure will be described with reference to specific embodiments and certain figures, but this disclosure is not limited thereto and is only limited by the claims. The described figures are illustrative and not restrictive. In the figures, for illustrative purposes, the sizes of some elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the practice of this disclosure. The term "substantially" or "approximately" used in the text means within an acceptable range, where those skilled in the art can solve the technical problems to be solved and substantially achieve the technical effects to be achieved. For example, "substantially perpendicular" means a way with a certain error from "completely perpendicular" that those skilled in the art can accept without affecting the correctness of the result.

[0036] Based on the embodiments described below, additional elements may be added. For example, the description of "forming a first element on a second element" may include embodiments where the first element is in direct contact with the second element, or may also include embodiments where additional elements are provided between the first element and the second element such that the first element and the second element are not in direct contact.

[0037] The spatial relative descriptors of the first and second elements may change with the operation of the device or its use in different orientations. Additionally, the present disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments discussed.

[0038] According to certain embodiments of the present disclosure, a semiconductor package structure with improved heat dissipation efficiency is described. The thermal dissipation path can be shortened, thereby improving the performance of the semiconductor package structure. For example, the present disclosure can be adopted as a thermal solution for mobile phones.

[0039] Figures 1A to 1C FIG. is a cross-sectional view depicting the semiconductor package structure 100 at various manufacturing stages according to certain embodiments of the present disclosure. Additional features can be added to the semiconductor package structure 100. For different embodiments, some of the features described below can be replaced or eliminated. To simplify the drawings, only a portion of the semiconductor package structure 100 is shown.

[0040] As Figure 1A shown, according to some embodiments, a package substrate 102 is provided. The package substrate 102 may have a wiring structure therein. In some embodiments, the wiring structure of the package substrate 102 includes a conductive layer, conductive vias, conductive posts, etc. or a combination thereof. The wiring structure of the package substrate 102 can be made of metal, including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0041] The wiring structure of the package substrate 102 can be disposed in a passivation layer. The passivation layer can be made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the passivation layer can be made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0042] It should be noted that the configuration of the package substrate 102 shown in the figures is merely exemplary and is not intended to limit the present disclosure. Any desired semiconductor element can be formed on and within the package substrate 102. However, to simplify the drawings, only the flat substrate 102 is shown.

[0043] As Figure 1AAs shown, according to some embodiments, the semiconductor package structure 100 includes a plurality of conductive terminals 104 disposed under the package substrate 102 and electrically coupled to the wiring structure of the package substrate 102. The conductive terminals 104 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc. or a combination thereof. In some embodiments, the conductive terminals 104 are made of a conductive material including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0044] As Figure 1A As further shown, according to some embodiments, the semiconductor package structure 100 includes a semiconductor die 112 disposed on the package substrate 102. In some embodiments, the semiconductor die 112 includes a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, etc. or any combination thereof. For example, the semiconductor die 112 may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a radio frequency front end (RFFE) die, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (IO) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) die, etc. or any combination thereof.

[0045] According to some embodiments, the semiconductor package structure 100 may include more than one semiconductor chip. In addition, the semiconductor package structure 100 may further include one or more passive components (not shown), adjacent to the semiconductor chip 112, such as resistors, capacitors, inductors, etc. or combinations thereof.

[0046] The semiconductor chip 112 may be electrically coupled to the wiring structure of the package substrate 102 through a plurality of conductive structures 108 and a plurality of connectors 106. As Figure 1A shown, the conductive structure 108 may be disposed under the semiconductor chip 112 and connected to (be bonded to) the package substrate 102 through the connector 106.

[0047] In some embodiments, the conductive structure 108 includes conductive pads, conductive pillars, etc. or combinations thereof. The conductive structure 108 may be made of a conductive material, including copper, aluminum, tungsten, titanium, tantalum, etc., their alloys, or combinations thereof. The conductive structure 108 may be formed by electroplating, electroless plating (also described as "chemical plating"), or other suitable processes.

[0048] In some embodiments, the connector 106 is made of a solder material, including tin, SnAg, SnPb, etc. or combinations thereof. The connector 106 may be formed by electroplating, electroless plating, or other suitable processes.

[0049] As Figure 1A shown, according to some embodiments, the semiconductor package structure 100 includes an underfill material 110, located between the package substrate 102 and the semiconductor chip 112. The underfill material 110 may fill the gap between the conductive structure 108 and the connector 106 and surround each of them to provide structural support. In some embodiments, the underfill material 110 is made of a polymer, such as an epoxy resin. The underfill material 110 may be dispensed using capillary force and then cured by any suitable curing process.

[0050] As Figure 1AAs shown, according to some embodiments, the semiconductor package structure 100 includes an adhesive layer 114 disposed on the semiconductor chip 112. The adhesive layer 114 may cover the entire top surface of the semiconductor chip 112. In some embodiments, the adhesive layer 114 includes a conductive paste (CP), a non-conductive paste (NCP), a high-k film, an epoxy resin, or other suitable materials. The sidewall of the adhesive layer 114 may be substantially coplanar with the sidewall of the semiconductor chip 112.

[0051] As Figure 1B As shown, according to some embodiments, the interposer 118 is bonded to the semiconductor chip 112 through the adhesive layer 114. The thickness of the semiconductor chip 112 is increased to obtain enhanced power budget. In addition, the semiconductor chip 112 is thick enough to connect to the interposer 118 such that heat from a heat source (e.g., the semiconductor chip 112) can be transferred to the interposer 118 through the adhesive layer 114. Thus, the heat dissipation path can be shortened.

[0052] According to some embodiments, in a direction substantially perpendicular to the top surface of the package substrate 102, the ratio of the thickness T1 of the semiconductor chip 112 to the distance D1 between the interposer 118 and the package substrate 102 is in the range of about 0.5 to about 0.95, for example, about 0.9.

[0053] The adhesive layer 114 may be disposed on the semiconductor chip 112 before bonding the interposer 118 to the semiconductor chip 112, as shown, but the present disclosure is not limited thereto. For example, the adhesive layer 114 may be disposed on the interposer 118 before bonding the interposer 118 to the semiconductor chip 112. Another example, the adhesive layer 114 may be disposed on both the interposer 118 and the semiconductor chip 112 before bonding the interposer 118 to the semiconductor chip 112.

[0054] The interposer 118 may have a wiring structure therein. In some embodiments, the wiring structure of the interposer 118 includes a conductive layer, a conductive via, a conductive pillar, etc. or a combination thereof. The wiring structure of the interposer 118 may be made of a metal, including copper, aluminum, tungsten, etc., an alloy, or a combination thereof.

[0055] The wiring structure of the interposer 118 may be disposed in a passivation layer. The passivation layer may be made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the passivation layer may be made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0056] As Figure 1B shown, according to some embodiments, the semiconductor package structure 100 includes a plurality of conductive structures 116 disposed between the package substrate 102 and the interposer 118. The wiring structure of the interposer 118 can be electrically coupled to the wiring structure of the package substrate 102 through the conductive structures 116. In some embodiments, the conductive structures 116 include conductive posts, solder balls, copper-core solder balls, etc. or combinations thereof. The conductive structures 116 can be made of conductive materials, including copper, aluminum, tungsten, etc., alloys or combinations thereof.

[0057] As Figure 1C shown, according to some embodiments, the semiconductor package structure 100 includes a molding material 120 that surrounds the semiconductor chip 112, the adhesive layer 114, the underfill material 110, and the conductive structures 116. The molding material 120 can include non-conductive materials, such as moldable polymers, epoxy resins, resins, etc. or combinations thereof.

[0058] The molding material 120 can protect the semiconductor chip 112, the adhesive layer 114, and the conductive structures 116 from the environment, thereby preventing these components from being damaged due to stress, chemicals, and moisture. As Figure 1C shown, the sidewall of the molding material 120 can be substantially coplanar with the sidewall of the package substrate 102 and the sidewall of the interposer 120.

[0059] In some embodiments, if the semiconductor chip is not thick enough to be bonded (also interchangeably described as joined) to the interposer, a portion of the molding material is disposed between the semiconductor chip and the interposer. In these embodiments, due to the narrow gap between the semiconductor chip and the interposer, some voids may be formed therein. In addition, the low thermal conductivity of the molding material makes heat dissipation difficult. In contrast, the present disclosure includes a thicker semiconductor chip 112 and uses an adhesive layer 114 to connect the semiconductor chip 112 to the interposer 118. Therefore, the voids between the semiconductor chip 112 and the interposer 118 can be reduced or avoided. In addition, since the adhesive layer 114 has a higher thermal conductivity than the molding material 120, the heat dissipation efficiency can be further improved.

[0060] In addition, the semiconductor chip 112 can provide stronger support than the molding material 120, so that the semiconductor package structure 100 can have better warpage behavior.

[0061] As described above, the sidewall of the adhesive layer 114 can be substantially coplanar with the sidewall of the semiconductor chip 112, as Figure 1Cas shown, but the present disclosure is not limited thereto. For example, the semiconductor package structure 200 includes an adhesive layer 114a, which may extend beyond the sidewalls of the semiconductor chip 112, such as Figure 2 as shown. The sidewalls of the adhesive layer 114a may be tapered. In particular, the adhesive layer 114a may have a larger projection area than the semiconductor chip 112.

[0062] As another example, the semiconductor package structure 300 includes an adhesive layer 114b, and the sidewalls of the adhesive layer 114b may be located between the sidewalls of the semiconductor chip 112, such as Figure 3 as shown. The sidewalls of the adhesive layer 114b may be rounded. In particular, the semiconductor chip 112 may have a larger projection area than the adhesive layer 114b.

[0063] Figure 4 is a cross-sectional view illustrating a semiconductor package structure 400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 400 includes components that are the same as or similar to those of the semiconductor package structure 100 Figure 1C as shown, and for simplicity, these components will not be discussed in detail. In the following embodiments, the encapsulation substrate has a recess for accommodating a thicker semiconductor chip.

[0064] such as Figure 4 as shown, according to some embodiments, the encapsulation substrate 102 has a recess 202, and the semiconductor chip 112 is directly disposed above the recess 202. In particular, the semiconductor chip 112 may be disposed in a thinner region of the encapsulation substrate 102. Therefore, the thickness of the semiconductor chip 112 can be further increased to enhance heat dissipation.

[0065] such as Figure 4 as shown, the encapsulation substrate 102 has a first top surface (i.e., the bottom surface of the recess 202) directly below the semiconductor chip 112 and a second top surface in contact with the conductive structure 116. The first top surface and the second top surface of the encapsulation substrate 102 form a stepped shape.

[0066] According to some embodiments, in the region without the groove 202, in a direction substantially perpendicular to the top surface of the encapsulation substrate 102, the thickness T2 of the semiconductor chip 112 and the distance D1 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.5 to about 0.98, for example, about 0.9. According to some embodiments, in the region with the groove 202, the thickness T2 of the semiconductor chip 112 and the distance D2 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.5 to about 0.95, for example, about 0.9. The distance D2 is greater than the distance D1. According to some embodiments, the ratio of the distance D2 to the distance D1 is in the range of about 1.05 to about 1.5, for example, about 1.07.

[0067] As Figure 4 Further shown, the sidewall of the groove 202 is substantially perpendicular to the second top surface of the encapsulation substrate 102, but the present disclosure is not limited thereto. For example, at least one sidewall of the groove 202 can be tapered or ramp-shaped.

[0068] As Figure 4 Shown, the conductive structure 108, the connector 106, and the underfill material 110 are disposed in the groove 202, and a part of the molding material 120 extends into the groove 202. However, this can vary according to the size or shape of the groove 202. For example, in some other embodiments, the underfill material 110 completely fills the groove 202, and the molding material 120 does not extend into the groove 202.

[0069] Figure 5 is a cross-sectional view illustrating a semiconductor package structure 500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 500 includes components identical or similar to those Figure 1C shown in the semiconductor package structure 100, and for simplicity, these components will not be discussed in detail. In the following embodiments, both the encapsulation substrate and the interposer have grooves for accommodating a thicker semiconductor chip.

[0070] As Figure 5 Shown, according to some embodiments, the encapsulation substrate 102 has a groove 202, the interposer 118 has a groove 302, and the groove 302 is directly above the groove 202. The semiconductor chip 112 is disposed between the groove 202 and the groove 302. In particular, the semiconductor chip 112 is disposed between a thinner region of the encapsulation substrate 102 and a thinner region of the interposer 118. Therefore, the thickness of the semiconductor chip 112 can be further increased to improve heat dissipation.

[0071] As Figure 5As shown, the interposer 118 has a first bottom surface (i.e., the bottom surface of the recess 302) that contacts the adhesive layer 114 and a second bottom surface that contacts the conductive structure 116. The first bottom surface and the second bottom surface of the interposer 118 form a stepped shape.

[0072] As Figure 5 Further shown, the encapsulation substrate 102 has a first top surface (i.e., the bottom surface of the recess 202) directly below the semiconductor chip 112 and a second top surface that contacts the conductive structure 116. The first top surface and the second top surface of the encapsulation substrate 102 form a stepped shape.

[0073] As Figure 5 As shown, the recess 302 has a larger projected area than the recess 202, but the present disclosure is not limited thereto. For example, the recess 202 has a larger projected area than the recess 302. Alternatively, the size of the recess 202 is substantially equal to the size of the recess 302.

[0074] According to some embodiments, in the region without the recesses 202 and 302, in a direction substantially perpendicular to the top surface of the encapsulation substrate 102, the thickness T3 of the semiconductor chip 112 and the distance D1 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.5 to about 1.5, such as about 1. According to some embodiments, in the region with the recesses 202 and 302, the thickness T3 of the semiconductor chip 112 and the distance D3 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.5 to about 0.95, such as about 0.85. The distance D3 is greater than the distance D1. According to some embodiments, the ratio of the distance D3 to the distance D1 is in the range of about 1.05 to about 1.5, such as about 1.07.

[0075] As Figure 5 As shown, the sidewall of the recess 202 is substantially perpendicular to the second top surface of the encapsulation substrate 102, and the sidewall of the recess 302 is substantially perpendicular to the second bottom surface of the interposer 118, but the present disclosure is not limited thereto. For example, at least one sidewall of the recess 202 and the sidewall of the recess 302 may be tapered or ramp-shaped.

[0076] As Figure 5 Further shown, the conductive structure 108, the connector 106, and the underfill 110 may be disposed in the recess 202. A portion of the molding material 120 may extend into the recess 202 and may cover the sidewall of the recess 202. However, this may vary depending on the size or shape of the recess 202. For example, in some other embodiments, the underfill 110 may completely fill the recess 202, and the molding material 120 may not extend into the recess 202.

[0077] As Figure 5As shown, the bottom surface of the groove 302 may have a larger projected area than the adhesive layer 114. A part of the molding material 120 may extend into the groove 302 and cover the sidewall of the groove 302. However, this may vary according to the size or shape of the groove 302. For example, in some other embodiments, the adhesive layer 114 completely fills the groove 302 and the molding material 120 does not extend into the groove 302.

[0078] Figure 6 FIG. 4 is a cross-sectional view illustrating a semiconductor package structure 600 in accordance with some embodiments of the present disclosure. It should be noted that the semiconductor package structure 600 may include components that are the same as or similar to those of the semiconductor package structure 100 shown in FIG. 1, and for simplicity, these components will not be discussed in detail herein. In the following embodiments, the interposer has a mesa structure to facilitate heat dissipation of the semiconductor chip. Figure 1C As shown in FIG. 5, in accordance with some embodiments, the interposer 118 has a mesa structure 402, and the semiconductor chip 112 is directly disposed below the mesa structure 402. In particular, the semiconductor chip 112 may be disposed in a thicker region of the interposer 118.

[0079] As Figure 6 shown in FIG. 6, in accordance with some embodiments, the interposer 118 has a mesa structure 402, and the semiconductor chip 112 is directly disposed below the mesa structure 402. In particular, the semiconductor chip 112 may be disposed in a thicker region of the interposer 118.

[0080] In accordance with some embodiments, the mesa structure 402 includes an embedded heat sink. The mesa structure 402 may be made of a metal, including copper, aluminum, tungsten, etc., alloys thereof, or combinations thereof. In some embodiments, the mesa structure 402 is part of the wiring structure of the interposer 118 and is formed during the formation of the wiring structure of the interposer 118. In some other embodiments, the mesa structure 402 is formed after the formation of the wiring structure of the interposer 118.

[0081] As Figure 6 shown in FIG. 7, the interposer 118 has a first bottom surface (i.e., the bottom surface of the mesa structure 402) directly above the semiconductor chip 112 and a second bottom surface in contact with the conductive structure 116. The first bottom surface and the second bottom surface of the interposer 118 form a stepped shape.

[0082] According to some embodiments, in a region without the mesa structure 402, in a direction substantially perpendicular to the top surface of the encapsulation substrate 102, the thickness T4 of the semiconductor chip 112 and the distance D1 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.2 to about 0.95, for example, about 0.8. According to some embodiments, in a region with the mesa structure 402, the thickness T4 of the semiconductor chip 112 and the distance D4 between the interposer 118 and the encapsulation substrate 102 are in the range of about 0.25 to about 0.95, for example, about 0.85. The distance D4 is less than the distance D1. According to some embodiments, the ratio of the distance D4 to the distance D1 is in the range of about 0.65 to about 0.98, for example, about 0.95.

[0083] As Figure 6 Further shown, the sidewall of the mesa structure 402 is substantially perpendicular to the second bottom surface of the interposer 118, but the present disclosure is not limited thereto. For example, at least one sidewall of the mesa structure 402 may be tapered or ramped.

[0084] The mesa structure 402 may be surrounded by the molding material 120. As Figure 6 shown, the mesa structure 402 may have a larger projected area than the adhesive layer 114 and the semiconductor chip 112, but the present disclosure is not limited thereto. For example, the adhesive layer 114 and / or the semiconductor chip 112 may have a larger projected area than the mesa structure 402. Another example, the sidewalls of the mesa structure 402 may be aligned with the sidewalls of the adhesive layer 114 and / or the semiconductor chip 112.

[0085] Figure 7 is a cross-sectional view illustrating a semiconductor package structure 700 according to certain embodiments of the present disclosure. It should be noted that the semiconductor package structure 700 may include components that are the same as or similar to those of the Figure 1C semiconductor package structure 100 shown, and for the sake of simplicity of description, these components will not be discussed in detail. In the following embodiments, the interposer has a groove for accommodating a thicker semiconductor chip.

[0086] As Figure 7 shown, according to some embodiments, the interposer 118 has a groove 502, and the semiconductor chip 112 is disposed in the groove 502. The thickness of the semiconductor chip 112 can be further increased to improve heat dissipation.

[0087] According to some embodiments, in a region without the recess 502, in a direction substantially perpendicular to the top surface of the package substrate 102, the ratio of the thickness T5 of the semiconductor chip 112 to the distance D1 between the interposer 118 and the package substrate 102 is in the range of about 0.85 to about 1.5, such as about 1.2. According to some embodiments, in a region with the recess 502, the ratio of the thickness T5 of the semiconductor chip 112 to the distance D5 between the interposer 118 and the package substrate 102 is in the range of about 0.75 to about 0.95, such as about 0.85. The distance D5 is greater than the distance D1. According to some embodiments, the ratio of the distance D5 to the distance D1 is in the range of about 1.15 to about 1.5, such as about 1.45.

[0088] As Figure 7 shown, the recess 502 may extend through the interposer 118. In particular, the recess 502 extends from the bottom surface to the top surface of the interposer 118. The side walls of the recess 502 are substantially perpendicular to the bottom surface of the interposer 118, but the present disclosure is not limited thereto. For example, at least one side wall of the recess 502 may be tapered or sloped. The molding material 120 may extend into the recess 502 and cover the side walls of the recess 502. The top surface of the interposer 118 and the top surface of the molding material 120 are substantially coplanar.

[0089] In some embodiments, as Figure 7 shown, the top surface of the semiconductor chip 112 is exposed to increase the heat dissipation efficiency. The top surface of the semiconductor chip 112 may be substantially coplanar with the top surface of the interposer 118 and the top surface of the molding material 120. The size (e.g., width) of the recess 502 may be greater than the size (e.g., width) of the semiconductor chip 112.

[0090] Figures 8A to 8B is a cross-sectional view of a semiconductor package structure 800 at different manufacturing stages according to certain embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 800. Some of the features described below may be replaced or omitted to accommodate different embodiments. For simplicity of illustration, only a part of the semiconductor package structure 800 is shown.

[0091] As Figure 8A shown, according to some embodiments, a substrate 802 is provided. The substrate 802 may be a package substrate. For example, the substrate 802 is a printed circuit board (PCB). The interior of the substrate 802 has a wiring structure 802M. In some embodiments, the wiring structure 802M includes a conductive layer, conductive vias, conductive posts, etc., or a combination thereof. The wiring structure 802M may be made of metal, including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0092] The wiring structure 802M is disposed in the dielectric layer 802D. The dielectric layer 802D is made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc., or a combination thereof. Alternatively, the dielectric layer 802D is made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc., or a combination thereof.

[0093] It should be noted that the configuration of the substrate 802 shown in the figure is only exemplary and is not intended to limit the present disclosure. Any desired semiconductor components can be formed on and in the substrate 802. However, for simplicity of illustration, only the flat substrate 802 is shown.

[0094] According to some embodiments, a plurality of conductive terminals 804 are disposed under the substrate 802. The conductive terminals 804 are electrically coupled to the wiring structure 802M. The conductive terminals 804 include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or a combination thereof. In some embodiments, the conductive terminals 804 are made of a conductive material, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., their alloys, or a combination thereof.

[0095] According to some embodiments, the semiconductor chip 112 is disposed on the substrate 802. In some embodiments, the semiconductor chip 112 includes a system-on-chip (SoC) chip, a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. For example, the semiconductor chip 112 may include a microcontroller unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input / output (IO) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, etc., or any combination thereof.

[0096] According to some embodiments, more than one semiconductor chip may be disposed on the substrate 802. In addition, one or more passive components (not shown) may be disposed on the substrate 802 and adjacent to the semiconductor chip 112, including resistors, capacitors, inductors, etc., or a combination thereof.

[0097] The semiconductor chip 112 can be electrically coupled to the wiring structure 802M through a plurality of conductive structures 108 and a plurality of connectors 106. The conductive structures 108 can be disposed under the semiconductor chip 112 and connected to the substrate 802 through the connectors 106.

[0098] In some embodiments, the conductive structure 108 includes conductive pads, conductive pillars, etc. or a combination thereof. The conductive structure 108 is made of a conductive material, including copper, aluminum, tungsten, titanium, tantalum, etc., their alloys or a combination thereof. The conductive structure 108 can be formed by electroplating, electroless plating or other suitable processes.

[0099] In some embodiments, the connector 106 is made of a solder material, including tin, SnAg, SnPb, etc. or a combination thereof. The connector 106 can be formed by electroplating, electroless plating or other suitable processes.

[0100] According to some embodiments, the underfill material 110 is formed between the substrate 802 and the semiconductor chip 112. The underfill material 110 fills the gap between the conductive structure 108 and the connector 106 and surrounds each of them to provide structural support. In some embodiments, the underfill material 110 is made of a polymer, such as epoxy resin. The underfill material 110 can be dispensed by capillary action and then cured through any suitable curing process. The underfill material 110 can partially cover the sidewalls of the semiconductor chip 112.

[0101] According to some embodiments, the adhesive layer 114 is formed on the semiconductor chip 112. The adhesive layer 114 can cover the entire top surface of the semiconductor chip 112. In some embodiments, the adhesive layer 114 includes conductive paste (CP), non-conductive paste (NCP), high dielectric constant film (high-k film), epoxy resin or other suitable materials. The sidewalls of the adhesive layer 114 can be substantially coplanar with the sidewalls of the semiconductor chip 112.

[0102] The present disclosure is not limited thereto. Similar to the previous discussion, according to one embodiment, the adhesive layer 114 can extend beyond the sidewalls of the semiconductor chip 112, such as in Figure 2 the semiconductor package structure 200. Or, according to another example, the sidewalls of the adhesive layer 114 are between the sidewalls of the semiconductor chip 112, such as in Figure 3 the semiconductor package structure 300.

[0103] Then, as Figure 8B shown, according to some embodiments, the interposer 806 is connected to the semiconductor chip 112. The interposer 806 is in direct contact with the adhesive layer 114 so that heat can be transferred from the heat source (e.g., the semiconductor chip 112) through the adhesive layer 114 to the interposer 806.

[0104] As shown above, the adhesive layer 114 may be disposed on the semiconductor chip 112 before the interposer 806 is connected to the semiconductor chip 112. However, the present disclosure is not limited thereto. For example, the adhesive layer 114 may be disposed on the interposer 806 before the interposer 118 is connected to the semiconductor chip 112. As another example, the adhesive layer 114 may be disposed on both the interposer 806 and the semiconductor chip 112 before the interposer 806 is connected to the semiconductor chip 112.

[0105] The interior of the interposer 806 has a wiring structure 806M. In some embodiments, the wiring structure 806M includes a conductive layer, conductive vias, conductive pillars, etc. or a combination thereof. The wiring structure 806M may be made of metal, including copper, aluminum, tungsten, etc., their alloys or combinations thereof.

[0106] The wiring structure 806M may be disposed in a dielectric layer 806D. The dielectric layer 806D may be made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the dielectric layer 806D may be made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0107] The interposer 806 has a recess 810. The semiconductor chip 112 and the adhesive layer 114 may be disposed in the recess 810 so that the thickness of the semiconductor chip 112 can be increased without increasing the total thickness of the semiconductor package structure 800. With a thicker semiconductor chip 112, the heat dissipation efficiency can be improved. In addition, a thicker semiconductor chip 112 can provide stronger support to improve the warpage behavior of the semiconductor package structure 800.

[0108] The recess 810 may have a depth D6. In some embodiments, the depth D6 ranges from about 20 micrometers (μm) to about 80 micrometers, such as about 50 micrometers. The depth D6 is greater than the thickness T6 of the adhesive layer 114 and less than the sum of the thickness T6 of the adhesive layer 114 and the thickness T7 of the semiconductor chip 112. The sidewall of the recess 810 is substantially perpendicular to the bottom surface of the interposer 806, but the present disclosure is not limited thereto. For example, at least one sidewall of the recess 810 may be tapered or ramp-shaped.

[0109] The interposer 806 has a first portion 806a and a second portion 806b. In a direction substantially perpendicular to the top surface of the interposer 806, the thickness T8 of the first portion 806a is less than the thickness T9 of the second portion 806b. In particular, the distance between the bottom surface of the second portion 806b and the bottom surface of the first portion 806a is equal to the depth D6.

[0110] The second part 806b is connected to and surrounds the first part 806a. The first part 806a vertically overlaps the semiconductor chip 112 and the adhesive layer 114. In some embodiments, the ratio of the thickness T8 of the first part 806a to the thickness T9 of the second part 806b is in the range of about 0.19 to about 0.29, such as about 0.23. Thus, not only the total height requirement of the package structure is met, but also the electrical characteristics and reasonable cost are considered simultaneously.

[0111] According to some embodiments, a heat spreader 812 is embedded in the first part 806a of the interposer 806. The bottom surface of the heat spreader 812 is exposed, and the heat spreader 812 is in direct contact with the adhesive layer 114. Thus, the heat from a heat source (such as the semiconductor chip 112) can be transferred to the heat spreader 812 through the adhesive layer 114.

[0112] The heat spreader 812 can be made of a metal, including copper, aluminum, tungsten, etc., their alloys or combinations thereof. Since the heat spreader 812 is made of a material with a higher thermal conductivity than the interposer 806, the heat dissipation efficiency can be further improved.

[0113] The bottom surface of the heat spreader 812 is substantially aligned with the bottom surface of the first part 806a of the interposer 806. The heat spreader 812 vertically overlaps the hot spot of the adhesive layer 114 and the semiconductor chip 112. The heat spreader 812 has a projection area that is substantially equal to or larger than the hot spot of the semiconductor chip 112. In some embodiments, the heat spreader 812 has a projection area that is substantially equal to or larger than the projection area of the adhesive layer 112 and / or the semiconductor chip 112. By increasing the area of the heat spreader 812, the heat dissipation efficiency can be further improved.

[0114] According to some embodiments, a plurality of thermal vias 814 are embedded in the first part 806a of the interposer 806. The thermal vias 814 are disposed above and in direct contact with the heat spreader 812. The heat spreader 812 and the thermal vias 814 are thermally coupled to the semiconductor chip 112. Thus, the heat transferred from the semiconductor chip 112 to the heat spreader 812 is also transferred to the thermal vias 814.

[0115] The thermal vias 814 are made of a metal, including copper, aluminum, tungsten, etc., their alloys or combinations thereof. The material of the thermal vias 814 is similar to that of the heat spreader 812. The materials of the heat spreader 812 and the thermal vias 814 are similar to the material of the wiring structure 806M. In some embodiments, the heat spreader 812 and the thermal vias 814 are formed together during the formation of the wiring structure 806M.

[0116] The top surface of the thermal vias 814 is exposed. The top surface of the thermal vias 814 is substantially aligned with the top surface of the first portion 806a of the interposer 806 and is also substantially aligned with the top surface of the second portion 806b of the interposer 806.

[0117] According to some embodiments, a plurality of conductive structures 808 are disposed between the substrate 802 and the interposer 806. The wiring structure 806M of the interposer 806 is electrically coupled to the wiring structure 802M of the substrate 802 through the conductive structures 808. In some embodiments, the conductive structures 808 include copper core solder balls. In some other embodiments, the conductive structures 808 include conductive posts, solder balls, any suitable structure, or a combination thereof. The conductive structures 808 are made of conductive materials, including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0118] The conductive structures 808 are partially disposed in the second portion 806b of the interposer 806 to reduce the total thickness of the semiconductor package structure 800. According to some embodiments, a plurality of openings (not shown) are formed in the interposer 806 by laser drilling or any suitable method, and then the conductive structures 808 are formed in the openings.

[0119] In particular, the bottommost surface of the interposer 806 (or the bottom surface of the second portion 806b) is disposed between the top surface and the bottom surface of the conductive structures 808. In some embodiments, along a direction substantially perpendicular to the top surface of the substrate 802, the ratio of the thickness T11 of the portion of the conductive structures 808 located in the second portion 806b to the thickness T10 of the conductive structures 808 is in the range of about 0.1 to about 0.3, for example, about 0.2. Thus, the total height requirement of the package structure can be met while also considering the electrical characteristics and reasonable cost.

[0120] Then, according to some embodiments, a molding material 120 is formed between the interposer 806 and the substrate 802. The molding material 120 can extend into the grooves 810. In particular, the thickness of the molding material 120 directly under the first portion 806a of the interposer 806 can be greater than the thickness of the molding material 120 directly under the second portion 806b of the interposer 806.

[0121] The molding material 120 can be made of non-conductive materials, including plastic polymers, epoxy resins, resins, etc., or a combination thereof. The molding material 120 can surround the semiconductor chip 112, the adhesive layer 114, the underfill material 110, and the conductive structures 808 to protect these components from the environment, thereby protecting them from stress, chemicals, and moisture damage.

[0122] In some embodiments, the molding material 120 is in direct contact with the bottom surface of the heat sink 812. The side walls of the molding material 120 are substantially coplanar with the side walls of the substrate 802 and the side walls of the interposer 806.

[0123] Figures 9A to 9B FIG. 4 is a cross-sectional view of a semiconductor package structure 900 at different manufacturing stages in accordance with certain embodiments of the present disclosure. It should be noted that the semiconductor package structure 900 may include components that are the same as or similar to those of the semiconductor package structure 800 shown, and for simplicity, these components will not be discussed in detail. In the following embodiments, a semiconductor chip is disposed on a redistribution structure. Figure 8B As shown, a substrate 902 is provided in accordance with some embodiments. The substrate 902 is a redistribution structure. The substrate 902 has a wiring structure 902M therein. In some embodiments, the wiring structure 902M includes a conductive layer, conductive vias, conductive pillars, etc. or a combination thereof. The wiring structure 902M is made of a metal, including copper, aluminum, tungsten, etc., its alloys, or a combination thereof.

[0124] As Figure 9A shown, a dielectric layer 902D is provided in accordance with some embodiments. The dielectric layer 902D is made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the dielectric layer 902D is made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0125] The wiring structure 902M is disposed in the dielectric layer 902D. The dielectric layer 902D is made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the dielectric layer 902D is made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0126] Then, in accordance with some embodiments, a semiconductor chip 112, a plurality of connectors 106, a plurality of conductive structures 108, underfill 110, and an adhesive layer 114 are formed on the substrate 902.

[0127] The interposer 806 may have a groove 810. The semiconductor chip 112 and the adhesive layer 114 are disposed in the groove 810 so as to increase the thickness of the semiconductor chip 112, thereby improving the heat dissipation efficiency.

[0128] After that, as Figure 9B shown, in accordance with some embodiments, the interposer 806 is bonded to the semiconductor chip 112. The interposer 806 is in direct contact with the adhesive layer 114 so that the heat of a heat source (e.g., the semiconductor chip 112) can be transferred to the interposer 806 through the adhesive layer 114. Similar to that discussed above, the adhesive layer 114 may be disposed on the semiconductor chip 112 and / or the interposer 806 before the interposer 806 is bonded to the semiconductor chip 112.

[0129] According to some embodiments, the heat sink 812 and the plurality of thermal vias 814 may be embedded in the first portion 806a of the interposer 806. The heat sink 812 is in direct contact with the adhesive layer 114, and the thermal vias 814 are in direct contact with the heat sink 812. The heat sink 812 vertically overlaps the semiconductor chip 112 and has a projected area that is approximately equal to or greater than the hot spot of the semiconductor chip 112.

[0130] The heat sink 812 and the thermal vias 814 are thermally coupled to the semiconductor chip 112. Accordingly, the heat of the semiconductor chip 112 can be transferred to the heat sink 812 through the adhesive layer 114 and can further be transferred to the thermal vias 814. Since the heat sink 812 and the thermal vias 814 are made of materials having a higher thermal conductivity than the interposer 806, the efficiency of heat dissipation can be further improved.

[0131] According to some embodiments, a plurality of conductive structures 808 are formed between the substrate 902 and the interposer 806. The wiring structure 806M of the interposer 806 is electrically coupled to the wiring structure 902M of the substrate 902 through the conductive structures 808. The conductive structures 808 are partially disposed in the second portion 806b of the interposer 806 to reduce the total thickness of the semiconductor package structure 800.

[0132] Then, according to some embodiments, a molding material 120 is formed between the interposer 806 and the substrate 902. The molding material 120 surrounds the semiconductor chip 112, the adhesive layer 114, the underfill material 110, and the conductive structures 808. The sidewalls of the molding material 120 are substantially coplanar with the sidewalls of the substrate 902 and the interposer 806.

[0133] Subsequently, according to some embodiments, a plurality of conductive terminals 904 are formed under the substrate 902. The conductive terminals 904 are electrically coupled to the wiring structure 902M. The conductive terminals 904 include micro-bumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc. or a combination thereof. In some embodiments, the conductive terminals 904 are made of a conductive material, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., their alloys, or a combination thereof.

[0134] Figures 10A to 10C is a cross-sectional view of the semiconductor package structure 1000 at various manufacturing stages according to certain embodiments of the present disclosure. It should be noted that the semiconductor package structure 1000 may include components that are the same as or similar to those of the Figure 8B semiconductor package structure 800 shown, and for simplicity, these components will not be discussed in detail. In the following embodiments, the semiconductor chip is disposed on the interposer before the interposer is bonded to the substrate.

[0135] As Figure 10AAs shown, an interposer 1002 is provided according to some embodiments. The interposer 1002 has a wiring structure 1002M. In some embodiments, the wiring structure 1002M includes conductive layers, conductive vias, conductive posts, etc., or combinations thereof. The wiring structure 1002M is made of metal, including copper, aluminum, tungsten, etc., their alloys, or combinations thereof.

[0136] The wiring structure 1002M is disposed in a dielectric layer 1002D. The dielectric layer 1002D is made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc., or combinations thereof. Alternatively, the dielectric layer 1002D is made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc., or combinations thereof.

[0137] The interposer 1002 includes a groove 1004. The groove 1004 has a depth D7. In some embodiments, the depth D7 ranges from about 30 microns to about 90 microns, such as about 50 microns. The sidewalls of the groove 1004 are substantially perpendicular to the top surface of the interposer 1002, but the present disclosure is not limited thereto. For example, at least one sidewall of the groove 1004 may be tapered or ramp-shaped.

[0138] The interposer 1002 has a first portion 1002a and a second portion 1002b. Along a direction substantially perpendicular to the top surface of the interposer 1002, the thickness T12 of the first portion 1002a is less than the thickness T13 of the second portion 1002b. In particular, the distance between the top surface of the second portion 1002b and the top surface of the first portion 1002a is equal to the depth D7. The second portion 1002b connects and surrounds the first portion 1002a. In some embodiments, the ratio of the thickness T12 of the first portion 1002a to the thickness T13 of the second portion 1002b ranges from about 0.5 to about 0.65, such as about 0.62.

[0139] According to some embodiments, a heat sink 1006 and a plurality of thermal vias 1008 are embedded in the first portion 1002a of the interposer 1002. The thermal vias 1008 are in direct contact with the heat sink 1006. The top surface of the heat sink 1006 is exposed by the groove 1004. In particular, the top surface of the heat sink 1006 is substantially aligned with the top surface of the first portion 1002a of the interposer 1002.

[0140] The heat sink 1006 is made of metal, including copper, aluminum, tungsten, etc., their alloys, or combinations thereof. The thermal vias 1008 are made of metal, including copper, aluminum, tungsten, etc., their alloys, or combinations thereof. The material of the thermal vias 1008 is similar to the material of the heat sink 1006. The materials of the heat sink 1006 and the thermal vias 1008 are similar to the wiring structure 1002M of the interposer 1002. The heat sink 1006 and the thermal vias 1008 are formed together during the formation of the wiring structure 1002M.

[0141] The bottom surface of the thermal vias 1008 is exposed. The bottom surface of the thermal vias 814 is substantially aligned with the bottom surface of the first part 1002a and is also substantially aligned with the bottom surface of the second part 1002b of the interposer 1002.

[0142] In some embodiments, the adhesive layer 1012 and the semiconductor chip 1010 are disposed in the groove 1004. The adhesive layer 1012 and the semiconductor chip 1010 are respectively similar to Figure 8A the adhesive layer 114 and the semiconductor chip 112 in the semiconductor package structure 800 in [reference], and thus will not be described in detail.

[0143] The adhesive layer 1012 and the semiconductor chip 1010 are disposed in the groove 1004, thereby increasing the thickness of the semiconductor chip 1010 to improve the heat dissipation efficiency. In a direction substantially perpendicular to the top surface of the interposer 1002, the depth D7 of the groove 1004 is greater than the thickness T14 of the adhesive layer 1012 and less than the sum of the thickness T14 of the adhesive layer 1012 and the thickness T15 of the semiconductor chip 1010.

[0144] The adhesive layer 1012 and the semiconductor chip 1010 vertically overlap the first part 1002a of the interposer 1002. The adhesive layer 1012 is in direct contact with the heat sink 1006. The heat sink 1006 and the thermal vias 1008 are thermally coupled to the semiconductor chip 1010. Therefore, the heat from the heat source (e.g., the semiconductor chip 1010) is transferred to the heat sink 1006 through the adhesive layer 1012 and can be further transferred to the thermal vias 1008. Since the heat sink 1006 and the thermal vias 1008 are made of materials with higher thermal conductivity than the interposer 1002, the heat dissipation efficiency can be improved.

[0145] The hot spot of the semiconductor chip 1010 is directly above the heat sink 1006. The heat sink 1006 has a projection area that is substantially equal to or larger than the hot spot of the semiconductor chip 1010. In some embodiments, the heat sink 1006 has a projection area that is substantially equal to or larger than the projection area of the adhesive layer 1012 and / or the semiconductor chip 1010. By increasing the area of the heat sink 1006, the heat dissipation efficiency can be further improved. In addition, the number of the thermal vias 1008 can also be increased accordingly.

[0146] It should be noted that, similar to the discussion above, before bonding the interposer 1002 to the semiconductor chip 1010, the bonding layer 1012 is disposed on the semiconductor chip 1010 and / or the interposer 1002. Additionally, as shown in the figure, the sidewalls of the bonding layer 1012 are substantially coplanar with the sidewalls of the semiconductor chip 1010. Alternatively, the bonding layer 1012 may extend beyond the sidewalls of the semiconductor chip 1010, or the sidewalls of the bonding layer 1012 may be located between the sidewalls of the semiconductor chip 1010.

[0147] Then, as Figure 10B shown, according to some embodiments, a plurality of conductive structures 1014 are partially disposed in the second portion 1002b of the interposer 1002. Thus, the total thickness of the semiconductor package structure 1000 can be further reduced. For example, by laser drilling or any suitable method, a plurality of openings (not shown) can be formed in the interposer 1002, and then the conductive structures 1014 can be formed in the openings.

[0148] In some embodiments, the conductive structure 1014 includes conductive pillars to achieve a fine via pitch and a high number of input / output (I / O) pins. In some other embodiments, the conductive structure 1014 includes copper-core solder balls, solder balls, any suitable structure, or a combination thereof. The conductive structure 1014 is made of a conductive material, including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0149] The topmost surface of the interposer 1002 (or the top surface of the second portion 1002b) is disposed between the top surface and the bottom surface of the conductive structure 1014. In some embodiments, in a direction substantially perpendicular to the top surface of the interposer 1002, the ratio of the thickness T17 of a portion of the conductive structure 1014 in the second portion 1002b to the thickness T16 of the conductive structure 1014 is in the range of about 0.1 to about 0.35, for example, about 0.15. Thus, the thermal performance can be improved.

[0150] Then, according to some embodiments, the molding material 1016 is formed on the interposer 1002 and extends into the recess 1006. In some embodiments, the molding material 1016 is in direct contact with the top surface of the heat sink 1006. The molding material 1016 is made of a non-conductive material, including a moldable polymer, an epoxy resin, a resin, etc., or a combination thereof. The molding material 1016 surrounds the semiconductor chip 1010, the bonding layer 1012, and the conductive structure 1014 to protect these components from the environment, thereby protecting them from stress, chemicals, and moisture damage.

[0151] Thereafter, according to some embodiments, the molding material 1016 is subjected to a planarization process until the top surfaces of the conductive structure 1014 and the semiconductor chip 1010 are exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a mechanical grinding process, etc. or a combination thereof. The top surface of the molding material 1016, the top surface of the conductive posts 1014, and the top surface of the semiconductor chip 1010 are substantially coplanar. The thickness of the molding material 1016 directly above the first portion 1002a of the interposer 1002 is greater than the thickness of the molding material 1016 directly above the second portion 1002b of the interposer 1002.

[0152] Next, as Figure 10C shown, according to some embodiments, a substrate 1018 is formed on the molding material 1016. The substrate 1018 may be a redistribution structure. The substrate 1018 has a wiring structure 1018M therein. In some embodiments, the wiring structure 1018M includes a conductive layer, a conductive via, a conductive post, etc. or a combination thereof. The wiring structure 1018M may be made of metal, including copper, aluminum, tungsten, etc., its alloy, or a combination thereof.

[0153] The wiring structure 1018M may be disposed in a dielectric layer 1018D. The dielectric layer 1018D may be made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof. Alternatively, the dielectric layer 1018D may be made of a dielectric material, including silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0154] The wiring structure 1002M of the interposer 1002 may be electrically coupled to the wiring structure 1018M of the substrate 1018 through the conductive structure 1014. The sidewalls of the molding material 1016 may be substantially coplanar with the sidewalls of the substrate 1018 and the sidewalls of the interposer 1002.

[0155] Thereafter, according to some embodiments, a plurality of conductive terminals 1020 are disposed on the substrate 1018. The conductive terminals 1020 are electrically coupled to the wiring structure 1018M. The conductive terminals 1020 may include micro-bumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc. or a combination thereof. In some embodiments, the conductive terminals 1020 are made of a conductive material, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., its alloy, or a combination thereof.

[0156] Figures 11A to 11B is a cross-sectional view of a semiconductor package structure 1100 at various manufacturing stages according to certain embodiments of the present disclosure.Figure 11A subsequent to the process steps shown in Figure 9A Figure 9A and use the same or similar reference numbers to depict components that are the same as or similar to those of the semiconductor package structure 900. For simplicity, these components will not be discussed in detail again. In the following embodiments, a heat sink is disposed between the redistribution structures.

[0157] As Figure 11A shown, according to some embodiments, a heat sink 1102 is formed on an adhesive layer 114. The adhesive layer 114 may be disposed on the semiconductor chip 112 and / or the heat sink 1102 before bonding the heat sink 1102 to the semiconductor chip 112. The heat sink 1102 may vertically overlap the hot spot of the semiconductor chip 112. Thus, heat can be transferred from the heat source (e.g., the semiconductor chip 112) to the heat sink 1102 through the adhesive layer 114.

[0158] In some embodiments, the heat sink 1102 includes a metal plate, a virtual semiconductor chip, or a combination thereof. For example, the heat sink 1102 may be made of copper, aluminum, silicon, germanium, or any suitable material. Since the heat sink 1102 is made of a material having a higher thermal conductivity than the molding material formed later, the heat dissipation efficiency can be improved. In addition, the heat sink 1102 can provide stronger support than the molding material. Thus, the semiconductor package structure 1100 can have better warpage behavior.

[0159] In some embodiments, the heat sink 1102 has a projected area that is substantially equal to or larger than that of the adhesive layer 114a and / or the semiconductor chip 112. By increasing the area of the heat sink 1102, the heat dissipation efficiency can be further improved.

[0160] Then, according to some embodiments, a plurality of conductive structures 1104 are formed on the heat sink 1102 and are thermally coupled to the heat sink 1102. The conductive structures 1104 may include conductive pads, conductive pillars, etc. or a combination thereof. The conductive structures 1104 may be made of a conductive material, including copper, aluminum, tungsten, titanium, tantalum, etc., their alloys, or a combination thereof. The conductive structures 1104 may be formed by electroplating, electroless plating, or other suitable processes.

[0161] After that, according to some embodiments, a plurality of conductive structures 1106 are disposed on the substrate 902. In some embodiments, the conductive structures 1106 include conductive pillars. In other embodiments, the conductive structures 1106 include copper-core solder balls, solder balls, any suitable structure, or a combination thereof. The conductive structures 1106 may be made of a conductive material, including copper, aluminum, tungsten, etc., their alloys, or a combination thereof.

[0162] Then, according to some embodiments, a molding material 1108 is formed on a substrate 902. The molding material 1108 can surround the semiconductor chip 112, the adhesive layer 114, the heat sink 1102, the conductive structure 1104, and the conductive structure 1106 to protect these components from the environment, thereby protecting them from stress, chemicals, and moisture. The molding material 1108 can be made of a non-conductive material, including a moldable polymer, an epoxy resin, a resin, etc., or a combination thereof. The molding material 1108 can cover the top surface and the sidewalls of the heat sink 1102.

[0163] Subsequently, according to some embodiments, the molding material 1108 is planarized until the top surfaces of the conductive structure 1104 and the conductive structure 1106 are exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a mechanical grinding process, a similar process, or a combination thereof. The top surface of the molding material 1016, the top surface of the conductive structure 1104, and the top surface of the conductive structure 1106 are substantially coplanar.

[0164] Then, as Figure 11B shown, according to some embodiments, a redistribution structure 1110 is formed on the molding material 1108. In an embodiment where the substrate 902 is a redistribution structure, the substrate 902 can be referred to as a first redistribution structure, and the redistribution structure 1110 can be referred to as a second redistribution structure. The sidewalls of the molding material 1118 are substantially coplanar with the sidewalls of the substrate 902 and the sidewalls of the redistribution structure 1110.

[0165] The redistribution structure 1110 is thermally coupled to the semiconductor chip 112 through the heat sink 1102 and the conductive structure 1104. Therefore, the heat transferred from a heat source (e.g., the semiconductor chip 112) to the heat sink 1102 can be further transferred to the redistribution structure 1110.

[0166] The redistribution structure 1110 has a wiring structure 1110M disposed in a dielectric layer 1110D. The wiring structure 1110M and the dielectric layer 1110D are similar to the wiring structure 902M and the dielectric layer 902D, and thus will not be described in detail. The wiring structure 1110M of the redistribution structure 1110 is electrically coupled to the wiring structure 902M of the substrate 902 through the conductive structure 1106.

[0167] Subsequently, according to some embodiments, a plurality of conductive terminals 1112 are disposed under the substrate 902. The conductive terminals 1112 are electrically coupled to the wiring structure 902M. The conductive terminals 1112 are similar to the conductive terminals 904 of the semiconductor package structure 900 in Figure 9B and thus will not be described in detail.

[0168] In summary, according to some embodiments, the semiconductor package structure of the present disclosure increases the thickness of the semiconductor chip (that is, a thicker semiconductor chip can be accommodated) to obtain enhanced power budget. Therefore, the heat dissipation efficiency can be improved, thereby improving the performance of the semiconductor package structure.

[0169] According to some embodiments, the semiconductor chip to the interposer shortens the heat dissipation path. Similarly, better warpage behavior and fewer (or no) voids can be achieved. In addition, according to some embodiments, the interposer has a mesa structure to facilitate heat transfer from the semiconductor chip. According to some embodiments, the top surface of the semiconductor chip is exposed to obtain better heat dissipation.

[0170] In some embodiments, the semiconductor package structure of the present disclosure includes a heat sink disposed in the interposer. The heat sink vertically overlaps with the heat source. Therefore, the heat dissipation efficiency can be improved.

[0171] According to some embodiments, the interposer includes a groove, thereby increasing the thickness of the semiconductor chip. Therefore, the heat dissipation efficiency can be further improved, and the warpage behavior of the semiconductor package structure can be improved. According to some embodiments, a plurality of conductive structure portions are disposed in the interposer, thereby reducing the total thickness of the semiconductor package structure.

[0172] Although the present invention has been described by way of examples and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar structures (as would be apparent to those skilled in the art), for example, combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A semiconductor package structure, comprising: A substrate; A semiconductor chip disposed on the substrate; An interposer disposed on the semiconductor chip and having a groove; A heat sink embedded in the interposer and vertically overlapping with the semiconductor chip; An adhesive layer disposed in the groove and connecting the semiconductor chip and the heat sink.

2. The semiconductor package structure as described in claim 1, wherein, The semiconductor package structure further comprises: a molding material surrounding the semiconductor chip and the adhesive layer and extending into the groove.

3. The semiconductor package structure as claimed in claim 2, wherein, The semiconductor package structure further comprises: a plurality of conductive structures disposed between the substrate and the interposer and surrounded by the molding material.

4. The semiconductor package structure as described in claim 3, wherein, Part of the conductive structure is disposed in the interposer.

5. The semiconductor package structure as described in claim 3, wherein, The conductive structure includes conductive pillars, solder balls, copper-core solder balls or a combination thereof.

6. The semiconductor package structure according to claim 1, wherein, The substrate includes a package substrate.

7. The semiconductor package structure according to claim 1, wherein, The substrate includes a redistribution structure.

8. The semiconductor package structure as described in claim 1, wherein, The semiconductor package structure further comprises: a plurality of thermal vias embedded in the interposer and thermally coupled to the heat sink.

9. A semiconductor package structure, comprising: A substrate; A semiconductor chip disposed on the substrate; The interposer comprises: A first part covering the semiconductor chip; and A second part connecting the first part and thicker than the first part; A heat sink disposed in the first part of the interposer; and A conductive structure partially disposed in the second part of the interposer and electrically coupling the substrate and the interposer.

10. The semiconductor package structure as described in claim 9, wherein, The semiconductor package structure further comprises: a plurality of thermal vias disposed in the first part of the interposer and thermally coupled to the heat sink.

11. The semiconductor package structure as described in claim 10, wherein, The thermal vias and the heat sink are made of metal.

12. The semiconductor package structure as described in claim 10, wherein, The top surface of the thermal via is substantially aligned with the top surface of the first part of the interposer and the top surface of the second part of the interposer.

13. The semiconductor package structure according to claim 9, wherein, The bottom surface of the heat sink is substantially aligned with the bottom surface of the first part of the interposer.

14. The semiconductor package structure as claimed in claim 9, wherein, The semiconductor package structure further comprises: an adhesive layer in contact with the semiconductor chip and the heat sink.

15. The semiconductor package structure according to claim 9, wherein, The heat sink has a projected area substantially equal to or larger than that of the adhesive layer and / or the semiconductor chip.

16. A semiconductor package structure, comprising: A first redistribution structure; A semiconductor chip disposed on the first redistribution structure; An adhesive layer disposed on the semiconductor chip; A heat sink disposed on the adhesive layer and vertically overlapping with the semiconductor chip; A second redistribution structure disposed on the heat sink; And A molding material surrounding the semiconductor chip, the adhesive layer and the heat sink.

17. The semiconductor package structure according to claim 16, wherein, The semiconductor package structure further comprises: a plurality of conductive structures thermally coupling the heat sink and the second redistribution structure and surrounded by the molding material.

18. The semiconductor package structure as described in claim 16, wherein, The semiconductor package structure further comprises: conductive pillars electrically coupling the first redistribution structure and the second redistribution structure and surrounded by the molding material.

19. The semiconductor package structure according to claim 16, wherein, The heat sink has a projected area larger than that of the adhesive layer and / or the semiconductor chip.

20. The semiconductor package structure as described in claim 16, wherein, The semiconductor package structure further comprises: A plurality of conductive terminals disposed below the first redistribution structure; A plurality of conductive structures disposed between the semiconductor chip and the first redistribution structure; and Underfill material surrounding the plurality of conductive structures.

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