Semiconductor structure and forming method thereof
By forming a columnar capacitor unit in the semiconductor structure and embedding a second metal layer, the problem of insufficient space utilization of the capacitor structure in the prior art is solved, and more efficient space utilization and electrical connection are achieved.
Patent Information
- Application Number
- CN202410064267.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-16
- Publication Date
- 2025-07-18
AI Technical Summary
The existing 3D capacitor structure cannot fully utilize the space of the through-hole structure in the semiconductor rear-stage process, resulting in the inability to construct a high-deep aspect ratio capacitor structure.
By forming an etch stop layer on the substrate, a bottom electrode is formed through the layer, and a capacitance dielectric layer and a top electrode are formed on its top surface and side walls, a columnar capacitor unit is formed, and an opening is formed in the second interlayer dielectric layer and a second metal layer is embedded to electrically connect the capacitor unit to improve space utilization.
The vertical space utilization of the capacitor structure is improved, the circuit connection between capacitor units is enhanced, the space in the vertical direction is saved and the contact area is increased.
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Figure CN120341210A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art
[0002] Currently, 3D capacitor structures are generally embedded in the back-end semiconductor process. Specifically, they are located in the same layer as the via structure in the back-end metal interconnect layer, and the upper and lower metal layers of the via structure are used to electrically connect the upper and lower electrodes of the capacitor structure. However, this structure cannot fully utilize the space of this layer of the via structure, which is not conducive to constructing a capacitor structure with a high aspect ratio.
[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the vertical space utilization rate of the capacitor structure. Summary of the Invention
[0004] This application provides a semiconductor structure and a method for forming the same, which can improve the vertical space utilization rate of the capacitor structure.
[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region, and a plurality of first metal layers are formed in the substrate in the first region and the second region respectively; forming an etch stop layer on the surface of the substrate and the first metal layers; forming a plurality of bottom electrodes on the surface of the etch stop layer, the plurality of bottom electrodes penetrating the etch stop layer and electrically connecting the plurality of first metal layers in the first region respectively; sequentially forming a capacitor dielectric layer and a top electrode on the top surface and side walls of the plurality of bottom electrodes, and each bottom electrode and the capacitor dielectric layer and the top electrode on its top and side walls form a capacitor unit; forming a second interlayer dielectric layer on the etch stop layer to cover the capacitor unit and the etch stop layer; forming a first opening in the second interlayer dielectric layer to expose at least part of the top surface and side walls of the capacitor unit and a second opening to expose the first metal layer in the second region; forming a second metal layer in the first opening and the second opening, the second metal layer in the first opening electrically connecting at least part of the side walls and the top surface of the top electrode of the capacitor unit, and the second metal layer in the second opening electrically connecting the first metal layer in the second region.
[0006] In some embodiments of this application, the method for forming the semiconductor structure further includes: using a chemical mechanical polishing process to polish the second metal layer and the second interlayer dielectric layer until the top electrode or the capacitor dielectric layer is exposed.
[0007] In some embodiments of this application, the substrate includes a semiconductor substrate and a first interlayer dielectric layer on the surface of the semiconductor substrate, and the plurality of first metal layers are located in the first interlayer dielectric layer.
[0008] In some embodiments of the present application, the capacitor unit includes a columnar bottom electrode, a dielectric layer covering the top surface and side walls of the bottom electrode, and a top electrode covering the top surface and side walls of the capacitive dielectric layer.
[0009] In some embodiments of the present application, the height of the portion of the side wall of the top electrode electrically connected to the second metal layer is 10% to 80% of the total height of the top electrode.
[0010] Another aspect of the present application further provides a semiconductor structure, including: a substrate, the substrate includes a first region and a second region, and a plurality of first metal layers are formed in the substrate and are respectively located in the first region and the second region; an etch stop layer located on the surfaces of the substrate and the first metal layers; a plurality of bottom electrodes located on the surface of the etch stop layer and penetrating the etch stop layer to electrically connect the plurality of first metal layers in the first region respectively; a capacitive dielectric layer and a top electrode sequentially located on the top surface and side walls of the plurality of bottom electrodes, and each bottom electrode and the capacitive dielectric layer and the top electrode on its top and side walls form a capacitor unit; a second interlayer dielectric layer located on the etch stop layer to cover the capacitor unit and the etch stop layer; a second metal layer located in the second interlayer dielectric layer, the second metal layer in the first region electrically connects the side walls of at least a part of the top electrodes of the capacitor units simultaneously, and the second metal layer in the second region electrically connects the first metal layer in the second region.
[0011] In some embodiments of the present application, the top surfaces of the second metal layer and the second interlayer dielectric layer are flush with the top surface of the top electrode or the capacitive dielectric layer.
[0012] In some embodiments of the present application, the substrate includes a semiconductor substrate and a first interlayer dielectric layer located on the surface of the semiconductor substrate, and the plurality of first metal layers are located in the first interlayer dielectric layer.
[0013] In some embodiments of the present application, the capacitor unit includes a columnar bottom electrode, a dielectric layer covering the top surface and side walls of the bottom electrode, and a top electrode covering the top surface and side walls of the capacitive dielectric layer.
[0014] In some embodiments of the present application, the height of the portion of the side wall of the top electrode electrically connected to the second metal layer is 10% to 80% of the total height of the top electrode.
[0015] The present application provides a semiconductor structure and a method for forming the same, which can improve the vertical space utilization rate of the capacitive structure. Description of the Drawings
[0016] The following drawings detail the exemplary embodiments disclosed in the present application. The same reference numerals denote similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.
[0017] Wherein:
[0018] Figures 1 to 9 are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to an embodiment of the present application. Detailed Description of Specific Embodiments
[0019] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but has the broadest scope consistent with the claims.
[0020] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.
[0021] Figures 1 to 9 are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below in conjunction with the drawings.
[0022] Referring to Figure 1 as shown, a substrate is provided. The substrate includes a first region 101 and a second region 102, and a plurality of first metal layers 120 are formed in the substrate and are respectively located in the first region 101 and the second region 102.
[0023] In some embodiments of the present application, the substrate includes a semiconductor substrate 100 and a first interlayer dielectric layer 110 on the surface of the semiconductor substrate 100, and the plurality of first metal layers 120 are located in the first interlayer dielectric layer 110. The semiconductor substrate 100 may include active devices formed in the front-end semiconductor process.
[0024] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.
[0025] In some embodiments of the present application, the first region 101 is used to form a capacitor structure, and the second region 102 is used to form a metal interconnect structure.
[0026] In some embodiments of the present application, the material of the first interlayer dielectric layer 110 includes silicon oxide, etc. The first interlayer dielectric layer 110 is used to form a metal interconnect structure in a part of the back-end process. Among them, the metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any one of the metal layers of the metal interconnect structure in the back-end process. The first metal layer 120 can be electrically connected to the active device in the front-layer metal or the semiconductor substrate through a via structure.
[0027] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. Here, the present application only takes two first metal layers 120 in the first region 101 and one first metal layer 120 in the second region 102 as an example. The first metal layer 120 in the first region 101 is set according to the number of capacitor structures.
[0028] Reference Figure 2 As shown, an etch stop layer 130 is formed on the surface of the substrate (specifically, the first interlayer dielectric layer 110) and the first metal layer. The material of the etch stop layer 130 includes silicon nitride.
[0029] Reference Figure 3 As shown, a plurality of bottom electrodes 141 are formed on the surface of the etch stop layer 130 in the first region 101, and the plurality of bottom electrodes 141 respectively penetrate the etch stop layer 130 and are electrically connected to the plurality of first metal layers 120 in the first region 101. The main body of the bottom electrode 141 is columnar, and a part of the bottom electrode 141 penetrates the etch stop layer 130 and is electrically connected to the first metal layer 120.
[0030] In some embodiments of the present application, the material of the bottom electrode 141 includes titanium nitride.
[0031] Reference Figure 4 As shown, a capacitor dielectric layer 142 and a top electrode 143 are sequentially formed on the top surface and side walls of the plurality of bottom electrodes 141. Each bottom electrode 141 and the capacitor dielectric layer 142 and the top electrode 143 on its top and side walls form a capacitor unit 140.
[0032] In some embodiments of the present application, the capacitor unit 140 includes a columnar bottom electrode 141, a capacitor dielectric layer 142 covering the top surface and side walls of the bottom electrode 141, and a top electrode 143 covering the top surface and side walls of the capacitor dielectric layer 142.
[0033] In some embodiments of the present application, the specific structure of the capacitor unit 140 can be arbitrary, as long as the capacitive dielectric layer 142 covers the top surface and sidewalls of the bottom electrode 141, and the top electrode 143 covers the top surface and sidewalls of the capacitive dielectric layer 142. For example, both the capacitive dielectric layer 142 and the top electrode 143 can partially extend to the surface of the etch stop layer 130, or they may not extend to the surface of the etch stop layer 130.
[0034] In some embodiments of the present application, the material of the top electrode 143 includes titanium nitride. The material of the capacitive dielectric layer 142 can be arbitrary according to the type of the capacitor unit 140, such as the ferroelectric material HZO.
[0035] In some embodiments of the present application, the method for forming the capacitive dielectric layer 142 and the top electrode 143 includes: first depositing the dielectric layer material and the top electrode material by atomic layer deposition process; then etching to form the capacitive dielectric layer 142 and the top electrode 143.
[0036] In some embodiments of the present application, the lateral dimension of the capacitor unit 140 can be the same as that of the first metal layer 120 in the first region 101.
[0037] Reference Figure 5 As shown, a second interlayer dielectric layer 150 covering the capacitor unit 140 and the etch stop layer 130 is formed on the etch stop layer 130.
[0038] In some embodiments of the present application, the material of the second interlayer dielectric layer 150 includes silicon oxide.
[0039] Reference Figure 6 As shown, a first opening 161 that simultaneously exposes at least part of the top and sidewalls of the capacitor unit 140 and a second opening 162 that penetrates the second interlayer dielectric layer 150 and the etch stop layer 130 to expose the first metal layer 120 in the second region 102 are formed in the second interlayer dielectric layer 150. Among them, the first opening 161 and the second opening 162 can be formed separately or synchronously.
[0040] Reference Figure 7 As shown, a second metal layer 170 is formed in the first opening 161 and the second opening 162. Among them, the second metal layer 170 in the first opening 161 is electrically connected to at least part of the sidewalls and the top surface of the top electrode 143 of the capacitor unit 140, and the second metal layer 170 in the second opening 162 is electrically connected to the first metal layer 120 in the second region 102. The at least part of the capacitor unit 140 refers to the part of the capacitor units that need to be electrically connected in parallel in the circuit design.
[0041] In some embodiments of the present application, the material of the second metal layer 170 includes copper. The method of forming the second metal layer 170 includes electroplating (ECP).
[0042] In some embodiments of the present application, the height of the portion of the sidewall of the top electrode 143 to which the second metal layer 170 in the first region 101 is electrically connected is 10% to 80% of the total height of the top electrode 143.
[0043] Reference Figure 8 and Figure 9 As shown, in some embodiments of the present application, the method of forming the semiconductor structure further includes: using a chemical mechanical polishing process to polish the second metal layer 170 and the second interlayer dielectric layer 150 until the top electrode 143 (reference Figure 8 shown) or the capacitor dielectric layer 142 (reference Figure 9 shown) is exposed, so that the second metal layer 170 in the first region 101 is electrically connected to the sidewalls of at least a part of the top electrodes 143 of the capacitor units 140 at the same time.
[0044] In the technical solution of the present application, reference Figure 7 , Figure 8 and Figure 9 shown, a capacitive structure is provided in a metal layer of a back-end process metal interconnect structure. The capacitor unit thereof is a columnar sleeve layer structure, which includes a bottom electrode, a dielectric layer, and a top electrode of the capacitor unit from the inside to the outside. The bottom electrode is electrically connected to the first metal layer in the lower layer, and the top electrode is directly electrically connected to the second metal layer in the same layer.
[0045] In the technical solution of the present application, the sidewalls and the top of the top electrode of the capacitor unit are directly electrically connected to the second metal layer, which is equivalent to directly embedding the capacitor unit in the second metal layer, saving space in the vertical direction, improving space utilization, and directly connecting adjacent capacitor units in series, so that the circuit between the capacitor units is shorter, increasing the contact area between the second metal layer and the top electrode, and helping to improve the electrical connection.
[0046] In the technical solution of the present application, the manufacturing of the capacitor unit is compatible with the conventional back-end process of integrated circuits, facilitating the implementation of this solution.
[0047] The present application provides a semiconductor structure and a method for forming the same, which can improve the space utilization in the vertical direction of the capacitive structure.
[0048] The present application also provides a semiconductor structure, reference Figure 7As shown, it includes: a substrate, the substrate includes a first region 101 and a second region 102, and a plurality of first metal layers 120 are formed in the substrate and are respectively located in the first region 101 and the second region 102; an etch stop layer 130, located on the surfaces of the substrate and the first metal layers 120; a plurality of bottom electrodes 141, located on the surface of the etch stop layer 130 and penetrating the etch stop layer 130 to be respectively electrically connected to the plurality of first metal layers 120 in the first region 101; a dielectric layer 142 and a top electrode 143 that are sequentially located on the top surface and side walls of the plurality of bottom electrodes 141, and each bottom electrode 141 and the dielectric layer 142 and the top electrode 143 on its top and side walls form a capacitor unit 140; a second interlayer dielectric layer 150, located on the etch stop layer 130 to cover the capacitor units 140 and the etch stop layer 130; a second metal layer 170, located in the second interlayer dielectric layer 150, the second metal layer 170 in the first region 101 is simultaneously electrically connected to at least part of the side walls of the top electrodes 143 of at least part of the capacitor units 140 or is simultaneously electrically connected to at least part of the side walls and the top surface of the top electrodes 143 of at least part of the capacitor units 140, and the second metal layer 170 in the second region 102 is electrically connected to the first metal layers 120 in the second region 102. The at least part of the capacitor units 140 refers to the part of the capacitor units that need to be electrically connected in parallel in the circuit design.
[0049] In some embodiments of the present application, the substrate includes a semiconductor substrate 100 and a first interlayer dielectric layer 110 located on the surface of the semiconductor substrate 100, and the plurality of first metal layers 120 are located in the first interlayer dielectric layer 110. The semiconductor substrate 100 may include active devices formed in the front-end semiconductor process.
[0050] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above.
[0051] In some embodiments of the present application, the first region 101 is used to form a capacitive structure, and the second region 102 is used to form a metal interconnect structure.
[0052] In some embodiments of the present application, the material of the first interlayer dielectric layer 110 includes silicon oxide, etc. The first interlayer dielectric layer 110 is used to form part of the metal interconnect structure in the back-end process. Among them, the metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any metal layer of the metal interconnect structure in the back-end process. The first metal layer 120 can be electrically connected to the active devices in the previous layer metal or the semiconductor substrate through the via structure.
[0053] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. Here, the present application only takes two first metal layers 120 in the first region 101 and one first metal layer 120 in the second region 102 as an example. The first metal layer 120 in the first region 101 is set according to the number of the capacitor structures.
[0054] Continue to refer to Figure 7 As shown, the material of the etch stop layer 130 includes silicon nitride.
[0055] Continue to refer to Figure 7 As shown, the several bottom electrodes 141 are specifically located on the surface of the etch stop layer 130 in the first region 101, penetrate through the etch stop layer 130 in the first region 101, and are respectively electrically connected to the several first metal layers 120 in the first region 101. The main body of the bottom electrode 141 is columnar, and a part of the bottom electrode 141 penetrates through the etch stop layer 130 to be electrically connected to the first metal layer 120.
[0056] In some embodiments of the present application, the material of the bottom electrode 141 includes titanium nitride.
[0057] Continue to refer to Figure 7 As shown, in some embodiments of the present application, the capacitor unit 140 includes a columnar bottom electrode 141, a capacitor dielectric layer 142 covering the top surface and side walls of the bottom electrode 141, and a top electrode 143 covering the top surface and side walls of the capacitor dielectric layer 142.
[0058] In some embodiments of the present application, the specific structure of the capacitor unit 140 can be arbitrary, as long as the capacitor dielectric layer 142 covers the top surface and side walls of the bottom electrode 141, and the top electrode 143 covers the top surface and side walls of the capacitor dielectric layer 142. For example, both the capacitor dielectric layer 142 and the top electrode 143 can partially extend to the surface of the etch stop layer 130, or may not extend to the surface of the etch stop layer 130.
[0059] In some embodiments of the present application, the material of the top electrode 143 includes titanium nitride. The material of the capacitor dielectric layer 142 can be arbitrary according to the type of the capacitor unit 140, such as the ferroelectric material HZO.
[0060] In some embodiments of the present application, the lateral dimension of the capacitor unit 140 can be the same as that of the first metal layer 120 in the first region 101.
[0061] Continuing to refer to Figure 7 As shown, in some embodiments of the present application, the material of the second interlayer dielectric layer 150 includes silicon oxide.
[0062] Refer to Figure 7 As shown, the second metal layer 170 in the first region 101 electrically connects at least a part of the sidewalls and the top surface of the top electrode 143 of the capacitor unit 140, or refer to Figure 8 and Figure 9 As shown, the second metal layer 170 in the first region 101 electrically connects at least a part of the sidewalls of the top electrode 143 of the capacitor unit 140. The second metal layer 170 in the second region 102 electrically connects the first metal layer 120 in the second region 102.
[0063] In some embodiments of the present application, the material of the second metal layer 170 includes copper.
[0064] In some embodiments of the present application, the height at which the second metal layer 170 in the first region 101 electrically connects to a part of the sidewall of the top electrode 143 is 10% to 80% of the total height of the top electrode 143.
[0065] Refer to Figure 8 and Figure 9 As shown, in some embodiments of the present application, the top surfaces of the second metal layer 170 and the second interlayer dielectric layer 150 are flush with the top surface of the top electrode 143 (refer to Figure 8 as shown) or the top surface of the capacitor dielectric layer 142 (refer to Figure 9 as shown).
[0066] In the technical solution of the present application, refer to Figure 7 、 Figure 8 and Figure 9 As shown, a capacitive structure is provided in a metal layer of an embedded back-end process metal interconnect structure. The capacitor unit has a columnar sleeve layer structure, which includes a bottom electrode, a capacitor dielectric layer, and a top electrode of the capacitor unit from the inside out. The bottom electrode is electrically connected to the first metal layer in the lower layer, and the top electrode is directly electrically connected to the second metal layer in the same layer.
[0067] In the technical solution of this application, the side walls and the top of the top electrode of the capacitor unit are directly electrically connected to the second metal layer. It is equivalent to directly embedding the capacitor unit into the second metal layer, saving space in the vertical direction, improving space utilization, and directly connecting adjacent capacitor units in series. The circuit between the capacitor units is shorter, increasing the contact area between the second metal layer and the top electrode, which helps to improve electrical connection.
[0068] In the technical solution of this application, the manufacturing of the capacitor unit is compatible with the conventional back-end process of integrated circuits, facilitating the implementation of this solution.
[0069] This application provides a semiconductor structure and a method for forming the same, which can improve the space utilization rate in the vertical direction of the capacitance structure.
[0070] In summary, after reading the content of this application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0071] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.
[0072] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.
[0073] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.
[0074] In addition, the specification of the present application describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will generally have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate includes a first region and a second region, and a plurality of first metal layers are formed in the substrate and are respectively located in the first region and the second region; Forming an etch stop layer on the surface of the substrate and the first metal layer; Forming a plurality of bottom electrodes on the surface of the etch stop layer, the bottom electrodes penetrating through the etch stop layer and respectively electrically connecting the plurality of first metal layers in the first region; Sequentially forming a capacitor dielectric layer and a top electrode on the top surface and sidewalls of the plurality of bottom electrodes, and each bottom electrode and the capacitor dielectric layer and the top electrode on its top and sidewalls form a capacitor unit; Forming a second interlayer dielectric layer on the etch stop layer to cover the capacitor units and the etch stop layer; Forming a first opening in the second interlayer dielectric layer to simultaneously expose at least a part of the top surface and sidewalls of the top electrodes of the capacitor units and a second opening to expose the first metal layer in the second region; Forming a second metal layer in the first opening and the second opening, the second metal layer in the first opening simultaneously electrically connecting at least a part of the sidewalls and the top surface of the top electrodes of the capacitor units, and the second metal layer in the second opening electrically connecting the first metal layer in the second region.
2. The method for forming a semiconductor structure as claimed in claim 1, wherein, Further comprising: Using a chemical mechanical polishing process to polish the second metal layer and the second interlayer dielectric layer until the top electrode or the capacitor dielectric layer is exposed.
3. The method for forming a semiconductor structure according to claim 1, wherein, The substrate includes a semiconductor substrate and a first interlayer dielectric layer on the surface of the semiconductor substrate, and the plurality of first metal layers are located in the first interlayer dielectric layer.
4. The method for forming a semiconductor structure as claimed in claim 1, wherein, The capacitor unit includes a columnar bottom electrode, a capacitor dielectric layer covering the top surface and sidewalls of the bottom electrode, and a top electrode covering the top surface and sidewalls of the capacitor dielectric layer.
5. The method for forming a semiconductor structure according to claim 1, wherein, The height of the second metal layer electrically connecting a part of the sidewalls of the top electrode is 10% to 80% of the total height of the top electrode.
6. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate includes a first region and a second region, and a plurality of first metal layers are formed in the substrate and are respectively located in the first region and the second region; An etch stop layer, located on the surface of the substrate and the first metal layer; A plurality of bottom electrodes, located on the surface of the etch stop layer and penetrating through the etch stop layer to respectively electrically connect the plurality of first metal layers in the first region; A capacitor dielectric layer and a top electrode sequentially located on the top surface and sidewalls of the plurality of bottom electrodes, and each bottom electrode and the capacitor dielectric layer and the top electrode on its top and sidewalls form a capacitor unit; A second interlayer dielectric layer, located on the etch stop layer to cover the capacitor units and the etch stop layer; A second metal layer, located in the second interlayer dielectric layer, the second metal layer in the first region simultaneously electrically connecting at least a part of the sidewalls of the top electrodes of the capacitor units, and the second metal layer in the second region electrically connecting the first metal layer in the second region.
7. The semiconductor structure according to claim 6, wherein The top surfaces of the second metal layer and the second interlayer dielectric layer are flush with the top surface of the top electrode or the capacitor dielectric layer.
8. The semiconductor structure according to claim 6, wherein, The substrate includes a semiconductor substrate and a first interlayer dielectric layer on the surface of the semiconductor substrate, and the plurality of first metal layers are located in the first interlayer dielectric layer.
9. The semiconductor structure according to claim 6, wherein, The capacitor unit includes a columnar bottom electrode, a dielectric layer covering the top surface and the side wall of the bottom electrode, and a top electrode covering the top surface and the side wall of the capacitor dielectric layer.
10. The semiconductor structure according to claim 6, wherein, The height of the partial side wall of the second metal layer electrically connected to the top electrode is 10% to 80% of the total height of the top electrode.