Capacitive coupling island chip architecture with high-voltage isolation function and packaging method

Abstract

The invention relates to a capacitive coupling chip architecture with a high-voltage isolation function and a packaging method, the capacitive coupling chip architecture comprises a capacitor module composed of a plurality of capacitive coupling channels, each capacitive coupling channel comprises two coupling capacitors connected in series, and each capacitor comprises five levels of a chip substrate, an N well, a high-voltage dielectric layer, an upper polar plate and a lower polar plate. The upper polar plate and the lower polar plate are both metal plates, the N well is arranged on the chip substrate, the upper polar plate and the lower polar plate are both arranged on the N well, a high-voltage dielectric layer is filled between the upper polar plate and the lower polar plate, and when the three-substrate chip packaging structure is adopted, the capacitor module, the signal transmitting module and the signal receiving module are respectively arranged on three different packaging substrates. When the chip packaging structure with the two substrates is adopted, the signal transmitting module and the signal receiving module are arranged on the two different packaging substrates respectively, and the capacitor module and the signal transmitting module or the signal receiving module are arranged on the same packaging substrate. A capacitor module formed by a plurality of capacitor coupling channels is also called as a capacitor coupling island.

Description

Technical Field

[0001] The present invention belongs to the field of high-voltage-resistant and anti-interference electronic isolation chips, and particularly relates to a capacitive coupling island chip architecture with a high-voltage isolation function and a packaging method thereof. Background Art

[0002] In an electronic system, if it is necessary to transmit signals between subsystems (circuits) in different voltage domains, an isolation channel is required for transmission. The isolation channel can block the loop between different voltage domains, and at the same time, it can also provide high-voltage isolation, transient protection, surge protection, interface isolation, or reduction of ground loop noise for electronic components or integrated circuits, thereby improving the stability and reliability of the operation of electronic components or integrated circuits. Usually, the isolation transmission between different voltage domains is completed by photosensitive devices. However, since photosensitive devices cannot be integrated or packaged within a chip, in recent years, people have begun to use capacitors or inductors to achieve the electronic isolation transmission of signals or energy between circuits in different voltage domains.

[0003] Among them, isolation capacitors are usually used for signal transmission between a high-voltage domain and a low-voltage domain, and achieve electrical isolation between the input circuit and the output circuit. It can provide high-voltage transient protection, surge protection, isolation interface, or ground loop noise for electronic components or integrated circuits, improving the stability and reliability of the operation of electronic components or integrated circuits.

[0004] In the prior art, the isolation capacitor and the internal circuit are usually fabricated on the same chip using integrated circuit technology, with high-voltage and low-voltage power supply domains, so there will be high-voltage and low-voltage interference and breakdown risks. And there is a parasitic capacitance between the lower plate of the capacitor and the semiconductor substrate. Since the entire chip shares the substrate, it will cause mutual interference between the internal circuit and the isolation capacitor, resulting in large losses of the transmitted signal on the isolation capacitor and serious signal attenuation. And it is required that the chip process must be a high-voltage process and can withstand thousands of volts of high voltage and tens of volts of pulse voltage per nanosecond. To achieve the required capacitance value, the area of the chip also needs to be large enough, which increases the cost of the chip. Since the high-voltage circuit and the low-voltage circuit are built on the same chip substrate, it is easy to generate interference through the substrate, thereby reducing the isolation degree or increasing the design difficulty.

[0005] That is, for existing isolation capacitor devices, after capacitance isolation, there is usually a certain degree of signal attenuation, which reduces the anti-interference ability of the system, affects the accuracy and reliability of signal transmission, and the indexes such as the voltage resistance and common-mode transient response of the overall chip will also perform poorly due to the limitations of the isolation capacitor device. Although only the isolation capacitor requires a high-voltage process, the entire chip still needs to be fabricated using a high-voltage process, thereby increasing the volume and cost of the chip. Summary of the Invention

[0006] Aiming at the defects existing in the prior art, the purpose of the present invention is to provide a capacitive coupling island chip architecture with a high-voltage isolation function and a packaging method, which can improve the overall efficiency of capacitive coupling, make it easy to integrate, reduce the chip area, improve the chip integration degree, and only the isolation capacitor chip on the capacitive isolation island requires a high-voltage process, while the chips constituting the signal transmitting module and the signal receiving module can be fabricated using a low-voltage chip process, thereby reducing the chip area, lowering the chip manufacturing cost, and being able to withstand high voltage and having strong anti-interference ability.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] In the first aspect, a capacitive coupling island chip architecture with a high-voltage isolation function includes a capacitive module composed of a number of capacitive coupling channels. Each capacitive coupling channel includes two serially connected coupling capacitors. Each coupling capacitor includes five levels: a chip substrate, an N-well, a high-voltage dielectric layer, an upper electrode plate, and a lower electrode plate. Both the upper electrode plate and the lower electrode plate are metal plates. The N-well is disposed on the chip substrate, and both the upper electrode plate and the lower electrode plate are disposed on the N-well. The upper electrode plate is disposed above the lower electrode plate, and a high-voltage dielectric layer is filled between the upper electrode plate and the lower electrode plate. When adopting a three-substrate chip packaging structure, the capacitive module, the signal transmitting module, and the signal receiving module are respectively placed on three different packaging substrates. When adopting a two-substrate chip packaging structure, the signal transmitting module and the signal receiving module are respectively placed on two different packaging substrates, and the capacitive module and the signal transmitting module or the signal receiving module are placed on the same packaging substrate. The capacitive module composed of several capacitive coupling channels is also called a capacitive coupling island.

[0009] Further, the coupling capacitor is disposed on the N-well of the chip substrate.

[0010] Further, the N-well is fabricated on the chip substrate by N-doping.

[0011] Further, the two coupling capacitors in each capacitive coupling channel share the chip substrate, the N-well, and the lower electrode plate, and the upper electrode plates of the two coupling capacitors are in the same metal layer or different metal layers.

[0012] Further, the two upper electrode plates are respectively connected to the circuits of the signal transmitting module and the signal receiving module through metal wire bonding.

[0013] Further, the dielectric of the high-voltage dielectric layer filled between the upper electrode plate and the lower electrode plate includes crystalline oxide.

[0014] Further, the distance between the upper electrode plate and the lower electrode plate is adjusted according to the voltage values on both sides of the upper electrode plate and the lower electrode plate to achieve the high-voltage isolation effect.

[0015] Second aspect: A method for packaging a capacitive coupling island chip with a high-voltage isolation function, which adopts a capacitive coupling island chip architecture with a high-voltage isolation function as described in the first aspect of the present invention and any one of its optional embodiments. The capacitive module, the signal transmitting module, and the signal receiving module are all packaged on three different packaging substrates, or the capacitive module and the signal transmitting module or the signal receiving module are packaged on the same packaging substrate, and the signal transmitting module and the signal receiving module are packaged on two different packaging substrates.

[0016] The beneficial technical effects of the present invention are as follows: By selecting a suitable dielectric layer material between the capacitive plates, the isolation voltage that the isolation capacitor can withstand reaches 8 kV or higher, so that the capacitive coupling island chip has good high-voltage isolation performance.

[0017] By integrating the capacitor separately on a chip, separating it from the signal transmitting module and / or the signal receiving module on other chips to form a capacitive coupling island; and doping N wells on the semiconductor substrate to separate the capacitors from each other, etc., the capacitive coupling island has good anti-interference performance.

[0018] The capacitive coupling island is separately integrated and only uses five levels of the integrated circuit process. It does not need to be integrated with the high-voltage circuit (i.e., the signal transmitting module) and the low-voltage circuit (i.e., the signal receiving module) at the same time, so that the capacitive coupling island has good integration. At the same time, the signal transmitting module and the signal receiving module can be fabricated using ordinary processes instead of high-voltage processes, thereby reducing the overall cost, shortening the production time, improving the product yield and design flexibility. Description of the Drawings

[0019] Figure 1 It is a top view of a capacitive coupling island chip architecture with a high-voltage isolation function shown in Embodiment 1 of the present invention;

[0020] Figure 2 It is a cross-sectional view of a capacitive coupling island chip architecture with a high-voltage isolation function shown in Embodiment 1 of the present invention at the upper electrode plate;

[0021] Figure 3 It is a schematic diagram of the architecture of a capacitive coupling island chip architecture with a high-voltage isolation function shown in Embodiment 1 of the present invention using a three-substrate package;

[0022] Figure 4 It is a schematic diagram of the architecture of a capacitive coupling island chip architecture with a high-voltage isolation function shown in Embodiment 1 of the present invention using a two-substrate package;

[0023] Figure 5Schematic diagram of the application of a capacitive coupled island chip architecture with high-voltage isolation function in a polarity discrimination type coupling circuit shown in the embodiments of the present invention;

[0024] Figure 6 Schematic diagram of the application of a capacitive coupled island chip architecture with high-voltage isolation function in an OOK (ON-OFF KEYING) type coupling circuit shown in the embodiments of the present invention;

[0025] Figure 7 Schematic diagram of the application of a capacitive coupled island chip architecture with high-voltage isolation function in an isolated power supply circuit shown in the embodiments of the present invention;

[0026] Wherein: 1-chip substrate, 2-N well, 3-upper plate, 4-lower plate, 5-high-voltage dielectric layer. Detailed implementation manners

[0027] The present invention will be further described below in conjunction with the accompanying drawings and detailed implementation manners.

[0028] Embodiment 1

[0029] As Figure 1 shown, the embodiments of the present invention provide a capacitive coupled island chip architecture with high-voltage isolation function, including a capacitive module composed of a plurality of capacitive coupling channels. The capacitive module composed of a plurality of capacitive coupling channels is also called a capacitive coupled island. Each capacitive coupling channel includes two series-connected coupling capacitors. A single coupling capacitor includes the chip substrate 1, N well 2, upper plate 3 and lower plate 4 at four levels as Figure 1 shown and the high-voltage dielectric layer 5 as Figure 2 shown. Both the upper plate 3 and the lower plate 4 are metal plates. The N well 2 is fabricated on the chip substrate 1 by N doping, and the lower plate 4, crystal dielectric layer 5 and upper plate 3 are configured on the N well 2 to form a capacitor.

[0030] Each capacitive coupling channel contains two series-connected coupling capacitors. The two coupling capacitors share the chip substrate 1, N well 2 and lower plate 4. The upper plates 3 of the two coupling capacitors are on the same horizontal plane and separated by a certain distance s1. The metals of the upper plates 3 of the two capacitors can be connected to the main circuits of the signal transmitting module and the signal receiving module respectively through metal wire bonding. There is a certain spacing s1 between the upper plates 3 of the two capacitors in the same capacitive coupling channel. The size of the appropriate spacing s1 should be adjusted to prevent the two upper plates from being directly broken down by high voltage. The two series-connected coupling capacitors provide a signal channel. In the embodiments of the present invention, the capacitive isolation island can provide multiple isolated signal channels.

[0031] As Figure 2As shown, similarly, the distance between the upper plates 3 of the capacitors in adjacent capacitive coupling channels is s2, and the size of s2 should also be appropriately adjusted to reduce the mutual interference of different electrical signals between adjacent capacitive coupling channels. The upper plates of the two coupling capacitors can be in the same metal layer or different metal layers. Even if the two upper plates 3 are not in the same metal layer, the high-voltage dielectric layer between the two upper plates 3 can also play a role in increasing isolation. In the embodiment of the present invention, the distance between the two metal layers of the upper plate 3 and the lower plate 4 is s3, and the distance s3 can be adjusted according to the voltages on both sides of the upper plate 3 and the lower plate 4 and the performance of the high-voltage dielectric layer 5 used.

[0032] The dielectric of the high-voltage dielectric layer filled between the upper plate 3 and the lower plate 4 includes crystal oxide. By selecting a suitable dielectric layer material and the plate distance s3 between the capacitive upper plate 3 and the lower plate 4, the isolation voltage that the capacitive coupling island can withstand can reach 8 kV or higher. Therefore, the capacitive coupling island can have good high-voltage isolation performance.

[0033] In the embodiment of the present invention, the two chips that need voltage isolation are called a signal transmission module and a signal reception module. The capacitive module is separately integrated on another chip, and is separated from both the signal transmission module and the signal reception module, and are respectively arranged on three different chips, and are separated on different packaging substrates to form a capacitive coupling island, as Figure 3 shown, where chip 1 is the signal transmission module, chip 2 is the signal reception module, the capacitive coupling island does not share the packaging substrate with the signal transmission module and the signal reception module, and is separated from each other on different chips, and is only connected by wire bonding, which well avoids the mutual interference of high and low potentials between the signal transmission module and the signal reception module. An N well is obtained by doping on the semiconductor substrate, and a PN junction is formed between the N well and the P substrate. Since this PN junction is in a high-resistance state in the unbiased state, the interference between the capacitive channels is further weakened. Through these improvements, the capacitive coupling island can have good anti-interference performance. At the same time, this also ensures that the chips where the signal transmission module is located and the chips where the signal reception module is located can be fabricated using low-voltage chip processes, thereby reducing the manufacturing cost.

[0034] In the embodiment of the present invention, the capacitive coupling island is integrated into a single chip, and only five levels of the integrated circuit process are used, without the need to be integrated with the high-voltage circuit (signal transmission module) and the low-voltage circuit (signal reception module) at the same time, so that the capacitive part has good integration and relatively low cost.

[0035] As an optional implementation manner, in the case of not using three-substrate packaging, it is possible to select as Figure 4In the two-packaging substrate capacitive coupling island scheme shown, the capacitive coupling island is packaged together with either the signal transmitting module or the signal receiving module. Even if the capacitive coupling island and the signal transmitting module share the packaging substrate, the signal receiving module is separately packaged, so that the signal receiving module uses a single packaging substrate alone. Or the capacitive coupling island and the signal receiving module share the packaging substrate, and the signal transmitting module is separately packaged, so that the signal transmitting module uses a single packaging substrate alone, reducing the number of packaging substrates from three to two, thereby reducing the area of the overall chip and better reducing costs. However, in this application scenario, the thickness of the dielectric layer from the upper plate to the lower plate should be appropriately increased.

[0036] In practical applications, the capacitive coupling island disclosed in the embodiments of the present invention can be applied to, for example, Figure 5 the polarity discrimination type coupling circuit shown in, Figure 6 the OOK type coupling circuit shown in, or Figure 7 the isolated power supply circuit shown in, making full use of the characteristics of the capacitive coupling island such as high voltage resistance, high integration, strong anti-interference ability, and low cost.

[0037] Figure 5 is a typical structure of a polarity discrimination type coupling circuit. Its signal transmitting module includes a pulse edge discriminator, a rising edge driver, and a falling edge driver. The receiving end includes a pulse edge flip-flop, a logic integration circuit, etc. Electrical isolation is formed between the signal transmitting module and the signal receiving module by an isolation capacitor. The function of the polarity discrimination type coupling circuit is: to detect the rising edge and falling edge of the input signal, transmit them respectively through the corresponding drivers, and after passing through the isolation capacitor, the waveform is restored in the signal receiving module through the pulse flip-flop and the logic integration circuit to obtain an output signal that is consistent with the waveform of the input signal. When planning the architecture, the signal transmitting module can be designed as chip 1, the signal receiving module can be designed as chip 2, and the isolation capacitor can be designed as a capacitive coupling island chip, and the three are separated from each other using a three-packaging substrate or two-packaging substrate architecture, making full use of the characteristics of the capacitive coupling island such as high voltage resistance, high integration, strong anti-interference ability, and low cost.

[0038] Figure 6It is a typical OOK-type coupling circuit structure. Its signal transmission module includes an output driver, etc., and its signal reception module includes a pulse envelope detector, etc. An electrical isolation is formed between the signal transmission module and the signal reception module by an isolation capacitor. The function of the OOK-type coupling circuit is: to perform OOK modulation on the input signal and then transmit it. After passing through the isolation capacitor, the waveform is restored by the pulse envelope detector in the signal reception module to obtain an output signal that is the same as the waveform of the input signal. During architecture planning, the signal transmission module can be designed as Chip 1, the signal reception module can be designed as Chip 2, and the isolation capacitor can be designed as a capacitive coupling island chip. The three are separated from each other by a triple-packaging substrate architecture, making full use of the characteristics of the capacitive coupling island such as high voltage resistance, high integration, strong anti-interference ability, and low cost.

[0039] Figure 7 It is a typical isolated power supply circuit structure. Chip 1 includes a power supply driver circuit, a logic control circuit, etc., and Chip 2 includes a full-wave rectifier, a voltage stabilization detection circuit, etc. Both Chip 1 and Chip 2 serve as both the signal transmission module and the signal reception module, and an electrical isolation is formed between them by an isolation capacitor. The function of the isolated power supply circuit is: in Chip 1, the input DC power supply is used as energy for transmission, and is transmitted through the power supply driver circuit. After passing through the isolation capacitor, it is processed into direct current by the full-wave rectifier in Chip 2; Chip 2 also has a voltage stabilization detection circuit to detect the voltage situation, and transmits the detection result back to Chip 1 through the isolation capacitor to adjust the working condition of the power supply driver circuit. During architecture planning, the isolation capacitor can be designed as a capacitive coupling island chip. The three of Chip 1, the capacitive coupling island, and Chip 2 are separated from each other by a triple-packaging substrate or a dual-packaging substrate architecture, making full use of the characteristics of the capacitive coupling island such as high voltage resistance, high integration, strong anti-interference ability, and low cost.

[0040] Embodiment 2

[0041] As Figure 3-4 shown, the embodiment of the present invention provides a packaging method for a capacitive coupling island chip with a high-voltage isolation function. Using the architecture of a capacitive coupling island chip with a high-voltage isolation function described in Embodiment 1 of the present invention and any of its optional embodiments, the capacitive coupling island is separately packaged on a chip to form a capacitive coupling island chip. The capacitive coupling island chip and the chip where at least one of the signal transmission module and the signal reception module with different voltage domains are located are respectively packaged on different packaging substrates, and the chips where the signal transmission module and the signal reception module with different voltage domains are located are respectively packaged on different packaging substrates, constituting a triple-substrate or dual-substrate packaging architecture.

[0042] As an alternative embodiment, the capacitive coupling island chip and the chip where any one of the signal transmitting module or the signal receiving module is located are encapsulated on the same packaging substrate. The capacitive coupling island chip is bonded to the same packaging substrate with insulating glue. Correspondingly, the other module in the signal receiving module or the signal transmitting module is encapsulated on another packaging substrate. Sharing the packaging substrate for the capacitive coupling island chip and the chip where the signal transmitting module or the signal receiving module is located reduces the packaging area of the overall chip and can better reduce costs. However, the thickness of the dielectric layer of the isolation capacitor needs to be appropriately thickened for voltage withstand requirements.

[0043] As can be seen from the above embodiments, a capacitive coupling island chip architecture and packaging method with a high-voltage isolation function disclosed by the present invention includes a plurality of capacitive coupling channels. The plurality of capacitive coupling channels form a capacitive module, and each capacitive coupling channel includes two series-coupled coupling capacitors. A single coupling capacitor is composed of only five levels of integrated circuit processes: substrate, N-well, high-voltage dielectric layer, lower electrode plate, and upper electrode plate. The isolation capacitor and at least one of the signal receiving module and the signal transmitting module are placed on different packaging substrates and are separately integrated to form a capacitive coupling island; doping the N-well on the semiconductor substrate enhances the isolation between the capacitive coupling channels. The capacitive coupling island chip architecture and packaging method with a high-voltage isolation function disclosed by the present invention have the characteristics of high voltage resistance, high integration, strong anti-interference ability, and low cost, and are widely applicable to various isolation circuits. Designing the isolation capacitor coupler as a single chip enables the production of other chips in the system without high-voltage processes, and the capacitive coupling island, the signal transmitting module, and the signal receiving module can be separately and independently optimized.

[0044] The devices and methods described in the present invention are not limited to the embodiments described in the specific embodiments. Those skilled in the art can obtain other embodiments based on the technical solutions of the present invention, which also belong to the scope of the technical innovation of the present invention.

Claims

1. A capacitive coupling island chip architecture with a high-voltage isolation function, characterized in that: It includes a capacitor module composed of a number of capacitive coupling channels. Each capacitive coupling channel includes two series-connected coupling capacitors. Each coupling capacitor includes five layers: a chip substrate, an N-well, a high-voltage dielectric layer, an upper plate, and a lower plate. Both the upper plate and the lower plate are metal plates. The N-well is disposed on the chip substrate. Both the upper plate and the lower plate are disposed on the N-well. The upper plate is disposed on the upper side of the lower plate. A high-voltage dielectric layer is filled between the upper plate and the lower plate. When using a chip packaging structure with three substrates, the capacitor module, the signal transmitting module, and the signal receiving module are respectively placed on three different packaging substrates. When using a chip packaging structure with two substrates, the signal transmitting module and the signal receiving module are respectively placed on two different packaging substrates. The capacitor module and the signal transmitting module or the signal receiving module are placed on the same packaging substrate. The capacitor module composed of several capacitive coupling channels is also called a capacitive coupling island.

2. The capacitive coupled island chip architecture with a high-voltage isolation function according to claim 1, wherein: The coupling capacitor is disposed on the N-well of the chip substrate.

3. The capacitive coupling island chip architecture with a high-voltage isolation function according to claim 2, characterized in that: The N-well is fabricated on the chip substrate by N-doping.

4. A capacitive coupling island chip architecture with a high-voltage isolation function according to claim 3, characterized in that: The two coupling capacitors in each capacitive coupling channel share the chip substrate, the N-well, and the lower plate. The upper plates of the two coupling capacitors are in the same metal layer or different metal layers.

5. The capacitive coupling island chip architecture with a high-voltage isolation function as described in claim 4, characterized in that: The two upper plates are respectively connected to the circuits of the signal transmitting module and the signal receiving module through wire bonding.

6. The capacitive coupling island chip architecture with a high-voltage isolation function according to claim 5, characterized in that: The dielectric of the high-voltage dielectric layer filled between the upper plate and the lower plate includes crystalline oxide.

7. The capacitive coupling island chip architecture with high-voltage isolation function according to claim 6, characterized in that: The distance between the upper plate and the lower plate is adjusted according to the voltage values on both sides of the upper plate and the lower plate to achieve the function of high-voltage isolation.

8. A chip packaging method for a capacitive coupling island with a high-voltage isolation function, using a chip architecture of a capacitive coupling island with a high-voltage isolation function as described in any one of claims 1-7. The capacitor module, the signal transmitting module, and the signal receiving module are all packaged on three different packaging substrates, or the capacitor module and the signal transmitting module or the signal receiving module are packaged on the same packaging substrate, and the signal transmitting module and the signal receiving module are packaged on two different packaging substrates.

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