COT control circuit for switching power supply

Abstract

The invention discloses a COT control circuit for a switching power supply, and belongs to the technical field of switching power supplies, and the COT control circuit for the switching power supply comprises a voltage sampling module which carries out the sampling of an input voltage and an output voltage through a proportional resistor, and provides an input current in proportion to the input voltage and an output current in proportion to the output voltage, two differential voltage signals are formed according to the input current and the output current; the differential signal transmission module is used for providing a differential voltage in which a proportional relation between an input voltage and an output voltage is stored according to the differential voltage signal; and the ripple voltage generation module is used for converting the differential voltage into a proportional current which is proportional to the output voltage and inversely proportional to the input voltage, and charging the fixed capacitor by using the proportional current to generate a ripple voltage. A ripple voltage which is proportional to an output voltage and inversely proportional to an input voltage is superposed on a reference voltage, so that the problem of difficulty in ripple injection design of a feedback node is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and particularly relates to a COT control circuit for a switching power supply. Background Art

[0002] COT (Constant On-Time) is a modulation control mode for switching power supplies. Its core feature is that the on-time Ton of each switch is fixed, while the off-time Toff is dynamically adjusted according to the feedback signal to achieve the stability of the output voltage. Compared with the traditional voltage / current control mode, the COT control mode is simpler. As Figure 1 shown, the output voltage Vout is sampled through the feedback resistors R10 and R20, and then the feedback voltage VFB and the reference voltage Vref are input to a fixed comparator for comparison. When VFB is lower than Vref, the fixed on-time pulse timer immediately starts a conduction period Ton of a fixed duration, making the switch Q10 conduct and Q20 cut off, charging the inductor L1 and boosting the output voltage. When the conduction time ends and enters the off state, Q10 cuts off and Q20 conducts. At this time, the inductor L1 discharges. The length of the off-time Toff is determined by the output load until VFB is lower than Vref again, triggering a new Ton period.

[0003] The COT control mode does not require a compensation network in the traditional voltage / current mode DC / DC control. The design of the converter is simpler, directly acting on the comparator with fast transient response. This also means that the output capacitor of the COT control mode can be smaller, which is sufficient to meet the given transient load response, saving both size and cost. In the light load condition of the COT control mode, the output voltage drops relatively slowly, and it takes a longer time for the feedback voltage to drop below Vref, and the frequency will decrease, maintaining a relatively high efficiency.

[0004] The traditional COT control mode also has the following defects: 1. The switching frequency is not fixed, which may increase the difficulty of EMI (Electromagnetic Interference) filtering. 2. The ripple of the feedback voltage VFB cannot be too small. When the ripple amplitude is insufficient, the controller may not be able to detect the voltage drop. When designing the power supply, it is generally more inclined to use ceramic capacitors with low equivalent series resistance (ESR) as the output capacitor to reduce the output ripple and stabilize the output voltage. However, if the output ripple amplitude is too small, it may cause false triggering or missed triggering, and even cause system instability and output voltage oscillation in extreme cases.

[0005] It should be noted that the information disclosed in the background art of this invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or an implication in any form that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a COT control circuit for a switching power supply to solve the problems of difficult setting of ripple voltage and non-fixed switching frequency.

[0007] To solve the above technical problems, the present invention provides a COT control circuit for a switching power supply, including: a voltage sampling module configured to sample the input voltage and the output voltage through a proportional resistor, provide an input current proportional to the input voltage and an output current proportional to the output voltage, and form two differential voltage signals based on the input current and the output current; a fixed conduction time generation module configured to form a charging current proportional to the input current for charging a charging capacitor to generate a fixed conduction time signal; a differential signal transmission module configured to provide a differential voltage storing the proportional relationship between the input voltage and the output voltage according to the differential voltage signals; a ripple voltage generation module configured to convert the differential voltage into a proportional current proportional to the output voltage and inversely proportional to the input voltage, and charge a fixed capacitor with the proportional current to generate a ripple voltage; a ripple current superposition module configured to convert the ripple voltage into a ripple current and superpose it on a reference current source to obtain a reference voltage superimposed with the ripple voltage.

[0008] Preferably, the voltage sampling module includes a first sampling unit and a second sampling unit. The first sampling unit is configured to sample the input voltage through a proportional resistor, generate an input current proportional to the input voltage, and transmit a first differential voltage signal to the differential signal transmission module through a switching tube. The second sampling unit is configured to sample the output voltage through a proportional resistor, generate an output current proportional to the output voltage, and transmit a second differential voltage signal to the differential signal transmission module through a switching tube. The first sampling unit and the second sampling unit have the same sampling ratio, and the switching tubes in the first sampling unit and the second sampling unit have the same size.

[0009] Preferably, the first sampling unit includes a first operational amplifier, a first resistor, a second resistor, a fifth resistor, a first NMOS transistor, a first current mirror, and a first switching transistor. The first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor and is connected to the non-inverting input terminal of the first operational amplifier, the second end of the second resistor is grounded, the output terminal of the first operational amplifier is connected to the control terminal of the first NMOS transistor, the output terminal of the first NMOS transistor is connected to the inverting input terminal of the first operational amplifier, the output terminal of the first NMOS transistor is also grounded through the fifth resistor, the input terminal of the first NMOS transistor is connected to the input terminal of the first current mirror, the output terminal of the first current mirror is connected to the input terminal of the first switching transistor, the control terminal and the input terminal of the first switching transistor are interconnected and output the first differential voltage signal, and the output terminal of the first switching transistor is grounded.

[0010] Preferably, the second sampling unit includes a second operational amplifier, a third resistor, a fourth resistor, a sixth resistor, a second NMOS transistor, a second current mirror, and a second switching transistor. The first end of the third resistor is connected to the output voltage, the second end of the third resistor is connected to the first end of the fourth resistor and is connected to the non-inverting input terminal of the second operational amplifier, the second end of the fourth resistor is grounded, the output terminal of the second operational amplifier is connected to the control terminal of the second NMOS transistor, the output terminal of the second NMOS transistor is connected to the inverting input terminal of the second operational amplifier, the output terminal of the second NMOS transistor is also grounded through the sixth resistor, the input terminal of the second NMOS transistor is connected to the input terminal of the second current mirror, the output terminal of the second current mirror is connected to the input terminal of the second switching transistor, the control terminal and the input terminal of the second switching transistor are interconnected and output the second differential voltage signal, and the output terminal of the second switching transistor is grounded.

[0011] Preferably, the differential signal transmission module includes a fully differential amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier through the seventh resistor, the second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier through the eighth resistor, a ninth resistor is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier, a tenth resistor is connected between the second output terminal and the inverting input terminal of the fully differential amplifier, and the resistance values of the seventh resistor, the eighth resistor, the ninth resistor, and the tenth resistor are equal.

[0012] Preferably, the ripple voltage generation module includes a bias current source, a third switch transistor, a fourth switch transistor, an eleventh resistor, a fixed capacitor, a fourth NMOS transistor, and a third current mirror. The third switch transistor and the fourth switch transistor have the same size. The input end of the bias current source is connected to the chip supply voltage, and the output end is connected to the input end of the third switch transistor. The input end and the control end of the third switch transistor are commonly connected and are also connected to the first end of the eleventh resistor and the first output end of the fully differential amplifier. The control end of the fourth switch transistor is connected to the second end of the eleventh resistor and the second output end of the fully differential amplifier. The input end of the fourth switch transistor is connected to the input end of the third current mirror. The output end of the third current mirror is connected to the first end of the fixed capacitor and the input end of the fourth NMOS transistor for providing a ripple voltage. The control end of the fourth NMOS transistor is used to access the falling-edge detection pulse signal provided by the chip SW port. The output ends of the third switch transistor, the fourth switch transistor, the second end of the fixed capacitor, and the output end of the fourth NMOS transistor are all grounded.

[0013] Preferably, the ripple current superposition module includes a third operational amplifier, a fifth NMOS transistor, a fourth current mirror, a reference current source, a twelfth resistor, and a thirteenth resistor. The non-inverting input end of the third operational amplifier is used to access the ripple voltage. The control end of the fifth NMOS transistor is connected to the output end of the third operational amplifier, and the output end is connected to the inverting input end of the third operational amplifier. The output end of the third operational amplifier is also grounded through the twelfth resistor. The input end of the fifth NMOS transistor is connected to the input end of the fourth current mirror. The output end of the fourth current mirror is connected to the output end of the reference current source and the first end of the thirteenth resistor. The input end of the reference current source is connected to the chip supply voltage, and the second end of the thirteenth resistor is grounded.

[0014] Preferably, the first current mirror includes a first PMOS transistor and a second PMOS transistor. The input ends of the first PMOS transistor and the second PMOS transistor are both connected to the chip supply voltage. The output end of the first PMOS transistor is connected to the input end of the first NMOS transistor. The output end and the control end of the first PMOS transistor are interconnected, and the control end of the first PMOS transistor is connected to the control end of the second PMOS transistor. The output end of the second PMOS transistor is connected to the input end of the first switch transistor.

[0015] Preferably, the fixed conduction time generation module includes a fifth PMOS transistor, a charging capacitor, a third NMOS transistor, and a comparator. The control terminal of the fifth PMOS transistor is connected to the control terminal of the first PMOS transistor. The input terminal of the fifth PMOS transistor is connected to the chip supply voltage. The output terminal of the fifth PMOS transistor is commonly connected to the first terminal of the charging capacitor, the input terminal of the third NMOS transistor, and the non-inverting input terminal of the comparator. The inverting input terminal of the comparator is used to access a charging reference voltage. The output terminal of the comparator is used to provide a fixed conduction time signal. The control terminal of the third NMOS transistor is used to receive the inverted signal of the switching frequency. The second terminal of the charging capacitor and the output terminal of the third NMOS transistor are both grounded.

[0016] Preferably, the fifth PMOS transistor and the first PMOS transistor have the same length and width but different m values, and are used to generate a charging current proportional to the input current.

[0017] In the COT control circuit for a switching power supply provided by the present invention, by sampling the input voltage and the output voltage, a proportional current that is proportional to the output voltage and inversely proportional to the input voltage is generated, which is converted into a ripple voltage that is proportional to the output voltage and inversely proportional to the input voltage. The ripple voltage is superimposed on the reference voltage Vref to achieve the effect of ripple injection, thereby solving the problem of the difficulty in designing ripple injection for the feedback node. Another current is formed based on the generated input current proportional to the input voltage, which is used to generate a fixed conduction time inversely proportional to the input voltage, so as to obtain a fixed switching frequency FSW that does not change with the change of the input voltage in the continuous conduction mode (CCM). Description of the Drawings

[0018] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 is a schematic diagram of a BUCK COT architecture in the prior art; Figure 2 is a circuit diagram of an embodiment of the present invention; Figure 3 is a waveform diagram of a fixed output voltage of 5V in an embodiment of the present invention, with the input voltage increasing from 10V to 40V; Figure 4 is a waveform diagram of a fixed input voltage of 10V in an embodiment of the present invention, with the output voltage increasing from 4V to 6V.

[0019] Appendix Figure 2 Among them: 100. Voltage sampling module; 101. First current mirror; 102. Second current mirror; 200. Fixed conduction time generation module; 300. Differential signal transmission module; 400. Ripple voltage generation module; 401. Third current mirror; 500. Ripple current superposition module; 501. Fourth current mirror. Detailed implementation mode

[0020] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales.

[0021] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" is usually the end close to the operator, the term "distal end" is usually the end close to the patient, "one end" and "the other end" as well as "proximal end" and "distal end" usually refer to corresponding two parts, which not only include the endpoints. The terms "mount", "connect", "couple" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. In addition, as used in the present invention, when an element is disposed on another element, it usually only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element in any orientation, unless otherwise clearly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] The research finds that there are three methods of ripple injection in the existing COT control mode: Method 1, using the ripple voltage naturally generated by the output capacitor ESR; Method 2, connecting a capacitor (CFF) in parallel across the upper voltage-dividing resistor of the feedback resistor, and coupling the ripple signal to the feedback node (FB) through the capacitor; Method 3, generating a voltage ripple in phase with the inductor current across the inductor through an RC network, and then coupling it to the feedback node (FB) through a capacitor.

[0023] These three methods all have problems to varying degrees in implementation. For Method 1, since the ESR of ceramic capacitors is small and insufficient for ripple compensation, the ESR of electrolytic capacitors is sufficient, but due to their large volume, the output ripple is large and not easily acceptable. For Method 2, similar to Method 1, it partially offsets the ripple attenuation problem of low-ESR capacitors, but it still depends on the output voltage ripple of the system itself and is insufficient to stably trigger the controller. For Method 3, the injected ripple amplitude is adjustable, but under different conditions, the compensation generally needs to be reset, which is rather cumbersome. Both Method 2 and Method 3 require adding additional devices. Generally speaking, the smaller the output voltage, the smaller the naturally generated ripple, and the greater the required ripple injection.

[0024] Further research finds that some existing COT control modes also introduce input voltage feedforward. In the continuous conduction mode (CCM), changes in the input voltage will not cause changes in the switching frequency (FSW). The formula for the switching frequency (FSW) is as follows:

[0025] The duty cycle D of the buck BUCK circuit:

[0026] Combining the above formulas, we can get:

[0027] If we want to fix the switching frequency, then Vin and Ton need to be inversely proportional.

[0028] According to the existing technology, if we want to make FSW fixed, then Vin and Ton need to be inversely proportional. We can use the time for a charging capacitor Con to be charged to a certain voltage value Vt by a current Ion that is inversely proportional to the input voltage, that is . Ion can be obtained by sampling the input voltage VIN’ and dividing it by a resistor R , and we can deduce .

[0029] A ripple voltage that is inversely proportional to the output voltage and does not change with the input voltage is superimposed on the reference voltage Vref. Alternatively, a current Ic can be used to charge a fixed capacitor Cc to form a ripple voltage, which is then converted into a ripple current and superimposed on the reference current. The superimposed ripple voltage should start rising at the falling edge of SW and reset and rise again at the falling edge of the next SW. The charging time is Toff + Ton’, where Ton’ is the conduction time of the next cycle.

[0030]

[0031] Based on the BUCK CCM mode, it can be seen from the above formula that the larger Vin is, the larger Toff is. If the amplitude of the ripple voltage is to remain unchanged, the charging current Ic should be inversely proportional to Vin; the larger Vo is, the smaller Toff is, and the charging current Ic should be proportional to Vo, that is 。

[0032] Based on this, the core idea of the present invention is to sample the input voltage and the output voltage, generate a proportional current that is proportional to the output voltage and inversely proportional to the input voltage, convert it into a ripple voltage that is proportional to the output voltage and inversely proportional to the input voltage, and superimpose the ripple voltage on the reference voltage Vref to achieve the effect of ripple injection, so as to solve the problem of the difficulty in designing ripple injection for the feedback node. On the basis of the generated proportional current, another current is formed to generate a fixed conduction time that is inversely proportional to the input voltage, so as to obtain a fixed switching frequency FSW that does not change with the input voltage in the continuous conduction (CCM) case.

[0033] Specifically, please refer to Figure 2 ,which is a schematic diagram of an embodiment of the present invention. As Figure 2 shown, a COT control circuit for a switching power supply includes: A voltage sampling module 100, configured to sample the input voltage Vin and the output voltage Vo through a proportional resistor, provide an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo, and form two differential voltage signals based on the input current Iin and the output current Io; A fixed conduction time generation module 200, configured to form a charging current Ion proportional to the input current Iin, used to charge a charging capacitor Con, and generate a fixed conduction time signal COT_on; A differential signal transmission module 300, configured to provide a differential voltage ΔV storing the proportional relationship between the input voltage Vin and the output voltage Vo according to the differential voltage signal; The ripple voltage generation module 400 is configured to convert the differential voltage ΔV into a proportional current Ic that is proportional to the output voltage Vo and inversely proportional to the input voltage Vin, and charge a fixed capacitor Cc with the proportional current Ic to generate a ripple voltage Vc; The ripple current superposition module 500 is configured to convert the ripple voltage Vc into a ripple current ΔI and superpose it on the reference current source Iref to obtain a reference voltage Vref with the ripple voltage Vc superposed thereon.

[0034] Exemplarily, in the voltage sampling module 100, the input voltage Vin and the output voltage Vo are sampled through a proportional resistor to generate an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo. The currents are processed to form two differential voltage signals containing the information of the input voltage Vin and the output voltage Vo respectively. The differential voltage ΔV is generated in the differential signal transmission module 300. The value of the differential voltage ΔV is related to the ratio between the input voltage Vin and the output voltage Vo. The ripple voltage generation module 400 then processes the differential voltage ΔV to form a proportional current Ic that is proportional to the output voltage Vo and inversely proportional to the input voltage Vin, and generates the ripple voltage Vc. In the ripple current superposition module 500, the ripple voltage Vc is first converted into a ripple current ΔI and superposed on the reference current source Iref to obtain a reference voltage Vref with the ripple voltage Vc superposed thereon, achieving the effect of ripple injection.

[0035] Further, a fixed conduction time generation module 200 is also provided. According to the provided input current Iin, a charging current Ion proportional to the input current Iin is formed. The charging current Ion is also proportional to the input voltage Vin and is used to generate a fixed conduction time signal inversely proportional to the input voltage Vin, so as to obtain a fixed switching frequency FSW that does not change with the change of the input voltage under the continuous conduction mode (CCM).

[0036] Specifically, the voltage sampling module 100 includes a first sampling unit (not labeled) and a second sampling unit (not labeled). The first sampling unit is configured to sample the input voltage Vin through a proportional resistor to generate an input current Iin proportional to the input voltage Vin, and transmit a first differential voltage signal to the differential signal transmission module through a switching transistor. The second sampling unit is configured to sample the output voltage Vo through a proportional resistor to generate an output current Io proportional to the output voltage Vo, and transmit a second differential voltage signal to the differential signal transmission module 300 through a switching transistor. The first sampling unit and the second sampling unit have the same sampling ratio, and the switching transistors in the first sampling unit and the second sampling unit have the same size.

[0037] After sampling to form an input current Iin proportional to the input voltage Vin and an output current Io proportional to the output voltage Vo, a switching transistor is used to provide a differential voltage signal input to the subsequent stage. To ensure the proportional relationship, the first sampling unit and the second sampling unit have the same sampling ratio, and the switching transistors in the first sampling unit and the second sampling unit have the same size. The proportional resistors of the first sampling unit are a first resistor R1 and a second resistor R2, and the proportional resistors in the second sampling unit are a third resistor R3 and a fourth resistor R4. More preferably, the resistance values of the first resistor R1 and the third resistor R3 are the same, and the resistance values of the second resistor R2 and the fourth resistor R4 are the same.

[0038] More preferably, the first sampling unit includes a first operational amplifier OP1, a first resistor R1, a second resistor R2, a fifth resistor R5, a first NMOS transistor NM1, a first current mirror 101, and a first switching transistor Q1. The first end of the first resistor R1 is connected to the input voltage Vin, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and is connected to the non-inverting input terminal of the first operational amplifier OP1, the second end of the second resistor R2 is grounded, the output terminal of the first operational amplifier OP1 is connected to the control terminal of the first NMOS transistor NM1, the output terminal of the first NMOS transistor NM1 is connected to the inverting input terminal of the first operational amplifier OP1, the output terminal of the first NMOS transistor NM1 is also grounded through the fifth resistor R5, the input terminal of the first NMOS transistor NM1 is connected to the input terminal of the first current mirror 101, the output terminal of the first current mirror 101 is connected to the input terminal of the first switching transistor Q1, the control terminal and the input terminal of the first switching transistor Q1 are interconnected, and the first differential voltage signal is output, and the output terminal of the first switching transistor Q1 is grounded.

[0039] The input terminal of the first NMOS transistor NM1 is the drain terminal, the output terminal is the source terminal, and the control terminal is the gate terminal. The gate terminal of the first NMOS transistor NM1 is connected to the output terminal of the first operational amplifier OP1, the source terminal of the first NMOS transistor NM1 is connected to the inverting input terminal of the first operational amplifier OP1, the source terminal of the first NMOS transistor NM1 is also grounded through the fifth resistor R5, and the drain terminal of the first NMOS transistor NM1 is connected to the input terminal of the first current mirror 101. The NMOS transistor in the present application can be replaced by a PMOS transistor. It should be noted that the arrangement of the replaced PMOS transistor needs to make its current direction the same as that of the original NMOS transistor. Similarly, the first switching transistor Q1 can also be a PNP triode or an NPN triode. Exemplarily, the first switching transistor Q1 is an NPN triode. The control terminal of the NPN triode is the base, the input terminal is the collector, and the output terminal is the emitter. The base and the collector of the first switching transistor Q1 are commonly connected, and the first differential voltage signal is output at the base.

[0040] The first current mirror 101 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The input terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the chip supply voltage Vcc. The output terminal of the first PMOS transistor PM1 is connected to the input terminal of the first NMOS transistor NM1. The output terminal and the control terminal of the first PMOS transistor PM1 are interconnected, and the control terminal of the first PMOS transistor PM1 is connected to the control terminal of the second PMOS transistor PM2. The output terminal of the second PMOS transistor PM2 is connected to the input terminal of the first switching transistor Q1. The input terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are the source terminals, the output terminals are the drain terminals, and the control terminals are the gate terminals. The source terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the chip supply voltage Vcc. The drain terminal of the first PMOS transistor PM1 is connected to the drain terminal of the first NMOS transistor NM1. The drain terminal and the gate terminal of the first PMOS transistor PM1 are interconnected, and the gate terminal of the first PMOS transistor PM1 is connected to the gate terminal of the second PMOS transistor PM2. The drain terminal of the second PMOS transistor PM2 is connected to the collector of the first switching transistor Q1. In the present application, the PMOS transistor can also be replaced by an NMOS transistor. It should be noted that the arrangement of the replaced NMOS transistor needs to make its current direction the same as that of the original PMOS transistor.

[0041] Specifically, the second sampling unit includes a second operational amplifier OP2, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a second NMOS transistor NM2, a second current mirror 102, and a second switching transistor Q2. The first end of the third resistor R3 is connected to the output voltage Vo. The second end of the third resistor R3 and the first end of the fourth resistor R4 are connected and connected to the non-inverting input terminal of the second operational amplifier OP2. The second end of the fourth resistor R4 is grounded. The output terminal of the second operational amplifier OP2 is connected to the control terminal of the second NMOS transistor NM2. The output terminal of the second NMOS transistor NM2 is connected to the inverting input terminal of the second operational amplifier OP2. The output terminal of the second NMOS transistor NM2 is also grounded through the sixth resistor R6. The input terminal of the second NMOS transistor NM2 is connected to the input terminal of the second current mirror 102. The output terminal of the second current mirror 102 is connected to the input terminal of the second switching transistor Q2. The control terminal and the input terminal of the second switching transistor Q2 are interconnected and output the second differential voltage signal. The output terminal of the second switching transistor Q2 is grounded.

[0042] It can be understood that the second switching transistor Q2 is an NPN transistor, and the base and collector of the second switching transistor Q2 are commonly connected, and the second differential voltage signal is output at the base. The second current mirror 102 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The input ends of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the chip power supply voltage Vcc. The output end of the third PMOS transistor PM3 is connected to the input end of the second NMOS transistor NM2. The control end and the output end of the third PMOS transistor PM3 are interconnected, and the control end of the third PMOS transistor PM3 is connected to the control end of the fourth PMOS transistor PM4. The output end of the fourth PMOS transistor PM4 is connected to the input end of the second switching transistor Q2. The input end and the control end of the second switching transistor Q2 are interconnected. The output end of the second switching transistor Q2 is grounded. The control end of the second switching transistor Q2 is used to provide a second differential voltage signal to the differential signal transmission module.

[0043] Among them, the resistance values of the first resistor R1 and the third resistor R3 are equal, the resistance values of the second resistor R2 and the fourth resistor R4 are equal, the resistance values of the fifth resistor R5 and the sixth resistor R6 are equal, the sampling ratios of the input voltage Vin and the output voltage Vo are the same. The first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 are PMOS transistors with the same size and are used to build a current mirror; the first NMOS transistor NM1 and the second NMOS transistor NM2 are NMOS transistors with the same size to enhance the current output ability; the first switching transistor Q1 and the second switching transistor Q2 are NPN transistors with the same size and are used to generate the Vbe voltage.

[0044] Vcc is the internal power supply voltage of the chip, which is generally set to 3.3V. The first resistor R1 and the second resistor R2 are sampling resistors, and the obtained sampling voltage is proportional to the input voltage Vin and is connected to the non-inverting input end of the first operational amplifier OP1. The output end of the first operational amplifier OP1 is connected to the gate of the first NMOS transistor NM1, and the inverting input end of the first operational amplifier OP1 is connected to the source of the first NMOS transistor NM1 to achieve voltage following and enhance the output current ability. The sampling voltage generates a current Iin proportional to the input voltage Vin through the fifth resistor R5. It is copied to the first switching transistor Q1 through the current mirror composed of the first PMOS transistor PM1 and the second PMOS transistor PM2. The be of the first switching transistor Q1 is short-circuited to ensure that it operates in the saturation state, and we can get , where I S is the reverse saturation current, and V T is approximately equal to 26mV at room temperature. Similarly, we can get .

[0045] Specifically, the differential signal transmission module 300 includes a fully differential amplifier FD_OP, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier FD_OP through the seventh resistor R7, and the second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier FD_OP through the eighth resistor R8. A ninth resistor R9 is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier FD_OP, and a tenth resistor R10 is connected between the second output terminal and the inverting input terminal of the fully differential amplifier FD_OP. Moreover, the resistance values of the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 are equal.

[0046] The fully differential amplifier FD_OP is used to suppress common-mode interference and output a stable differential voltage ΔV. R7 = R8 = R9 = R10, and the differential signal amplification factor is 1. The function of this module is to obtain a stable Vinbe - Vobe differential voltage, as shown in the following formula.

[0047]

[0048] Specifically, the ripple voltage generation module 400 includes a bias current source Ibias, a third switching transistor Q3, a fourth switching transistor Q4, an eleventh resistor R11, a fixed capacitor Cc, a fourth NMOS transistor NM4, and a third current mirror 401. The third switching transistor Q3 and the fourth switching transistor Q4 have the same size. The input terminal of the bias current source Ibias is connected to the chip power supply voltage Vcc, and the output terminal is connected to the input terminal of the third switching transistor Q3. The input terminal and the control terminal of the third switching transistor Q3 are commonly connected and are also connected to the first terminal of the eleventh resistor R11 and the first output terminal of the fully differential amplifier FD_OP. The control terminal of the fourth switching transistor Q4 is connected to the second terminal of the eleventh resistor R11 and the second output terminal of the fully differential amplifier FD_OP. The input terminal of the fourth switching transistor Q4 is connected to the input terminal of the third current mirror 401. The output terminal of the third current mirror 401 is connected to the first terminal of the fixed capacitor Cc and the input terminal of the fourth NMOS transistor NM4 to provide a ripple voltage Vc. The control terminal of the fourth NMOS transistor NM4 is used to connect to the falling-edge detection pulse signal Rc provided by the chip SW port. The output terminals of the third switching transistor Q3, the fourth switching transistor Q4, the second terminal of the fixed capacitor Cc, and the output terminal of the fourth NMOS transistor NM4 are all grounded.

[0049] In an implementation manner, the input terminal of the bias current source Ibias is connected to the switching power supply chip power supply voltage Vcc. The bias current source Ibias can be a current generated by an internal module of the chip or an externally provided current source.

[0050] The third current mirror 401 includes a sixth PMOS transistor PM6 and a seventh PMOS transistor PM7. The input terminals of the sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 are both connected to the chip supply voltage Vcc. The output terminal of the sixth PMOS transistor PM6 is connected to the input terminal of the fourth switch transistor Q4. The output terminal and the control terminal of the sixth PMOS transistor PM6 are interconnected, and the control terminal of the sixth PMOS transistor PM6 is connected to the control terminal of the seventh PMOS transistor PM7. The output terminal of the seventh PMOS transistor PM7 is connected to the first terminal of the fixed capacitor Cc.

[0051] The third switch transistor Q3 and the fourth switch transistor Q4 are both NPN bipolar transistors. The sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 are PMOS transistors with the same size, which are used to copy current. The third switch transistor Q3 and the fourth switch transistor Q4 are NPN bipolar transistors with the same size. The voltage across the eleventh resistor R11 is the differential voltage △V output by the fully differential amplifier FD_OP, which is also the voltage difference between Vbbe and Vcbe. The bias current source Ibais is a fixed current generated internally, as shown in the following formula.

[0052]

[0053]

[0054]

[0055] The proportional relationship between the input current Iin and the output current Io is transferred to the proportional relationship between the bias current source Ibais and the proportional current Ic through the differential voltage △V. The input current Iin and the output current Io are obtained by sampling the input voltage Vin and the output voltage Vo respectively. Therefore, the proportional current Ic is inversely proportional to the input voltage Vin and directly proportional to the output voltage Vo. The obtained proportional current Ic is used to charge the fixed capacitor Cc, and the ripple current Vc can be obtained. The Rc signal is a pulse signal detected at the falling edge of SW, which is used to control the switching of the fourth NMOS transistor NM4 and provide a discharge path for the fixed capacitor Cc.

[0056] Specifically, the ripple current superposition module 500 includes a third operational amplifier OP3, a fifth NMOS transistor NM5, a fourth current mirror 501, a reference current source Iref, a twelfth resistor R12, and a thirteenth resistor R13. The non-inverting input terminal of the third operational amplifier OP3 is used to access the ripple voltage Vc. The control terminal of the fifth NMOS transistor NM5 is connected to the output terminal of the third operational amplifier OP3, and the output terminal is connected to the inverting input terminal of the third operational amplifier OP3. The output terminal of the third operational amplifier OP3 is also grounded through the twelfth resistor R12. The input terminal of the fifth NMOS transistor NM5 is connected to the input terminal of the fourth current mirror 501. The output terminal of the fourth current mirror 501 is connected to the output terminal of the reference current source Iref and the first terminal of the thirteenth resistor R13. The input terminal of the reference current source Iref is connected to the chip supply voltage Vcc, and the second terminal of the thirteenth resistor R13 is grounded.

[0057] In an embodiment, the input terminal of the reference current source Iref is connected to the switching power supply chip supply voltage Vcc. The reference current source Iref can be a current generated by an internal module of the chip or an externally provided current source.

[0058] The fourth current mirror 501 includes an eighth PMOS transistor PM8 and a ninth PMOS transistor PM9. The input terminals of the eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 are both connected to the chip supply voltage Vcc. The output terminal of the eighth PMOS transistor PM8 is connected to the input terminal of the fifth NMOS transistor NM5. The output terminal and the control terminal of the eighth PMOS transistor PM8 are interconnected, and the control terminal of the eighth PMOS transistor PM8 is connected to the control terminal of the ninth PMOS transistor PM9. The output terminal of the ninth PMOS transistor PM9 is connected to the first terminal of the thirteenth resistor R13.

[0059] The ripple voltage Vc is connected to the non-inverting input terminal of the third operational amplifier OP3. The output terminal of the third operational amplifier OP3 is connected to the gate of the fifth NMOS transistor NM5, and the inverting input terminal of the third operational amplifier OP3 is connected to the source of the fifth NMOS transistor NM5 to achieve voltage following and enhance the output current capability. The ripple voltage Vc generates a ripple current △I through the twelfth resistor R12. The eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 are PMOS transistors with the same size and are used to copy the ripple current △I. The ripple current △I is superimposed on the reference current source Iref, and the reference voltage Vref superimposed with the ripple signal can be obtained through the thirteenth resistor R13.

[0060] Specifically, the fixed conduction time generation module 200 includes a fifth PMOS transistor PM5, a charging capacitor Con, a third NMOS transistor NM3, and a comparator COMP. The control terminal of the fifth PMOS transistor PM5 is connected to the control terminal of the first PMOS transistor PM1. The input terminal of the fifth PMOS transistor PM5 is connected to the chip supply voltage Vcc. The output terminal of the fifth PMOS transistor PM5 is commonly connected to the first terminal of the charging capacitor Con, the input terminal of the third NMOS transistor NM3, and the non-inverting input terminal of the comparator COMP. The inverting input terminal of the comparator COMP is used to connect to the charging reference voltage Vt. The output terminal of the comparator COMP is used to provide a fixed conduction time signal COT_on. The control terminal of the third NMOS transistor NM3 is connected to the inverted signal Ro of the switching frequency. The inverted signal Ro of the switching frequency is obtained, for example, by processing the signal output from the SW port of the chip. The second terminal of the charging capacitor Con and the output terminal of the third NMOS transistor NM3 are both grounded. The fifth PMOS transistor PM5 and the first PMOS transistor PM1 have the same length and width but different m values, and are used to generate a charging current Ion proportional to the input current Iin. It can be understood that different m values mean that the number of parallel MOS transistors in the fifth PMOS transistor PM5 and the first PMOS transistor PM1 on the layout is different.

[0061] The fifth PMOS transistor PM5 and the first PMOS transistor PM1 have the same length and width but different m values, and generate a charging current Ion proportional to the input current Iin. The charging current Ion charges the charging capacitor Con. COMP is a comparator. The charging voltage Von is compared with the charging reference voltage Vt to obtain the COT_on pulse signal when the fixed conduction time is reached, which is used to switch the drive to the form of the upper transistor being turned off and the lower transistor being turned on. The duration of the high level of the square wave is the fixed conduction time. . The Ro signal is the inverted signal of the switching frequency and is used to control the switching of the third NMOS transistor NM3 to provide a discharge path for the charging capacitor Con. COT_on is a narrow pulse signal used for logic control in the switching power supply.

[0062] Such as Figure 3 、 Figure 4 is the waveform diagram of this circuit, Figure 3Waveform diagram of the output voltage Vo fixed at 5V and the input voltage Vin varying from 10V to 40V. From the waveform of SW (output port), it can be seen that when the input voltage Vin increases, the conduction time Ton decreases, but the frequency remains unchanged. The charging current Ion is proportional to the input voltage Vin. The increase in the charging current Ion enables the charging voltage to reach the charging reference voltage Vt faster, resulting in a decrease in the conduction time Ton. The proportional current Ic is inversely proportional to the input voltage Vin. Since the frequency remains unchanged and the conduction time decreases, the turn-off time Toff will increase, and the charging time of the fixed capacitor Cc will increase. The charging current Ic decreases and the charging time increases, so the obtained ripple voltage Vc remains unchanged. The charging time of the fixed capacitor Cc is , the charging voltage , the charging time of the fixed capacitor Cc is proportional to the input voltage Vin, and the charging current Ic is inversely proportional to the input voltage Vin, so the ripple voltage remains unchanged.

[0063] Figure 4 Waveform diagram of the input voltage Vin fixed at 10V and the output voltage Vo varying from 4V to 6V. From the SW waveform, it can be seen that when the input voltage Vin remains unchanged, the conduction time Ton remains unchanged. However, due to the change in the output voltage Vo, the duty cycle will change, and the time of one cycle is no longer fixed. The proportional current Ic is proportional to the output voltage Vo. The conduction time Ton remains unchanged, and the turn-off time Toff is inversely proportional to the output voltage Vo, so the slope of the change in the charging voltage is fixed. The charging time of the fixed capacitor Cc is , the charging voltage , at this time, the conduction time Ton is a fixed value, the proportional current Ic is inversely proportional to the output voltage Vo, so the ripple voltage Vc is inversely proportional to Vo.

[0064] In the COT control circuit for a switching power supply provided by the present invention, by superimposing a ripple voltage that is inversely proportional to the output voltage and directly proportional to the input voltage on the reference voltage Vref, the problem of difficult design for ripple injection at the feedback node is solved. Based on the provided input current proportional to the input voltage, a fixed conduction time generating current is designed to generate a conduction time Ton inversely proportional to Vin to fix the switching frequency in the CCM case and reduce EMI.

[0065] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the technical solutions of the present invention.

Claims

1. A COT control circuit for a switching power supply, characterized in that, Comprising: A voltage sampling module, configured to sample the input voltage and the output voltage through a proportional resistor, provide an input current proportional to the input voltage and an output current proportional to the output voltage, and form two differential voltage signals based on the input current and the output current; A fixed conduction time generation module, configured to form a charging current proportional to the input current for charging a charging capacitor to generate a fixed conduction time signal; A differential signal transmission module, configured to provide a differential voltage storing the proportional relationship between the input voltage and the output voltage according to the differential voltage signals; A ripple voltage generation module, configured to convert the differential voltage into a proportional current proportional to the output voltage and inversely proportional to the input voltage, and charge a fixed capacitor with the proportional current to generate a ripple voltage; A ripple current superposition module, configured to convert the ripple voltage into a ripple current and superpose it on a reference current source to obtain a reference voltage superimposed with the ripple voltage.

2. The COT control circuit for a switching power supply according to claim 1, wherein The voltage sampling module includes a first sampling unit and a second sampling unit. The first sampling unit is configured to sample the input voltage through a proportional resistor, generate an input current proportional to the input voltage, and transmit a first differential voltage signal to the differential signal transmission module through a switching transistor. The second sampling unit is configured to sample the output voltage through a proportional resistor, generate an output current proportional to the output voltage, and transmit a second differential voltage signal to the differential signal transmission module through a switching transistor. The first sampling unit and the second sampling unit have the same sampling ratio, and the switching transistors in the first sampling unit and the second sampling unit have the same size.

3. The COT control circuit for a switching power supply according to claim 2, wherein, The first sampling unit includes a first operational amplifier, a first resistor, a second resistor, a fifth resistor, a first NMOS transistor, a first current mirror, and a first switching transistor. The first end of the first resistor is connected to the input voltage, the second end of the first resistor is connected to the first end of the second resistor and connected to the non-inverting input terminal of the first operational amplifier, the second end of the second resistor is grounded, the output terminal of the first operational amplifier is connected to the control terminal of the first NMOS transistor, the output terminal of the first NMOS transistor is connected to the inverting input terminal of the first operational amplifier, the output terminal of the first NMOS transistor is also grounded through the fifth resistor, the input terminal of the first NMOS transistor is connected to the input terminal of the first current mirror, the output terminal of the first current mirror is connected to the input terminal of the first switching transistor, the control terminal and the input terminal of the first switching transistor are interconnected and output the first differential voltage signal, and the output terminal of the first switching transistor is grounded.

4. The COT control circuit for a switching power supply according to claim 2, wherein The second sampling unit includes a second operational amplifier, a third resistor, a fourth resistor, a sixth resistor, a second NMOS transistor, a second current mirror, and a second switching transistor. The first end of the third resistor is connected to the output voltage, the second end of the third resistor is connected to the first end of the fourth resistor and is connected to the non-inverting input terminal of the second operational amplifier. The second end of the fourth resistor is grounded. The output terminal of the second operational amplifier is connected to the control terminal of the second NMOS transistor. The output terminal of the second NMOS transistor is connected to the inverting input terminal of the second operational amplifier. The output terminal of the second NMOS transistor is also grounded through the sixth resistor. The input terminal of the second NMOS transistor is connected to the input terminal of the second current mirror. The output terminal of the second current mirror is connected to the input terminal of the second switching transistor. The control terminal and the input terminal of the second switching transistor are interconnected, and the second differential voltage signal is output. The output terminal of the second switching transistor is grounded.

5. The COT control circuit for a switching power supply according to claim 2, characterized in that, The differential signal transmission module includes a fully differential amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The first differential voltage signal is connected to the non-inverting input terminal of the fully differential amplifier through the seventh resistor. The second differential voltage signal is connected to the inverting input terminal of the fully differential amplifier through the eighth resistor. A ninth resistor is connected between the first output terminal and the non-inverting input terminal of the fully differential amplifier. A tenth resistor is connected between the second output terminal and the inverting input terminal of the fully differential amplifier. The resistance values of the seventh resistor, the eighth resistor, the ninth resistor, and the tenth resistor are equal.

6. The COT control circuit for a switching power supply according to claim 5, wherein, The ripple voltage generation module includes a bias current source, a third switching transistor, a fourth switching transistor, an eleventh resistor, a fixed capacitor, a fourth NMOS transistor, and a third current mirror. The third switching transistor and the fourth switching transistor have the same size. The input terminal of the bias current source is connected to the chip supply voltage, and the output terminal is connected to the input terminal of the third switching transistor. The input terminal and the control terminal of the third switching transistor are commonly connected, and are also connected to the first end of the eleventh resistor and the first output terminal of the fully differential amplifier. The control terminal of the fourth switching transistor is connected to the second end of the eleventh resistor and the second output terminal of the fully differential amplifier. The input terminal of the fourth switching transistor is connected to the input terminal of the third current mirror. The output terminal of the third current mirror is connected to the first end of the fixed capacitor and the input terminal of the fourth NMOS transistor for providing a ripple voltage. The control terminal of the fourth NMOS transistor is used to access the falling-edge detection pulse signal provided by the chip SW port. The output terminals of the third switching transistor, the fourth switching transistor, the second end of the fixed capacitor, and the output terminal of the fourth NMOS transistor are all grounded.

7. The COT control circuit for a switching power supply according to claim 2, wherein, The ripple current superposition module includes a third operational amplifier, a fifth NMOS transistor, a fourth current mirror, a reference current source, a twelfth resistor, and a thirteenth resistor. The non-inverting input terminal of the third operational amplifier is used to connect the ripple voltage. The control terminal of the fifth NMOS transistor is connected to the output terminal of the third operational amplifier, and the output terminal is connected to the inverting input terminal of the third operational amplifier. The output terminal of the third operational amplifier is also grounded through the twelfth resistor. The input terminal of the fifth NMOS transistor is connected to the input terminal of the fourth current mirror. The output terminal of the fourth current mirror is connected to the output terminal of the reference current source and the first end of the thirteenth resistor. The input terminal of the reference current source is connected to the chip supply voltage, and the second end of the thirteenth resistor is grounded.

8. The COT control circuit for a switching power supply according to claim 3, wherein The first current mirror includes a first PMOS transistor and a second PMOS transistor. The input terminals of the first PMOS transistor and the second PMOS transistor are both connected to the chip supply voltage. The output terminal of the first PMOS transistor is connected to the input terminal of the first NMOS transistor. The output terminal and the control terminal of the first PMOS transistor are interconnected, and the control terminal of the first PMOS transistor is connected to the control terminal of the second PMOS transistor. The output terminal of the second PMOS transistor is connected to the input terminal of the first switch transistor.

9. The COT control circuit for a switching power supply according to claim 8, wherein, The fixed conduction time generation module includes a fifth PMOS transistor, a charging capacitor, a third NMOS transistor, and a comparator. The control terminal of the fifth PMOS transistor is connected to the control terminal of the first PMOS transistor. The input terminal of the fifth PMOS transistor is connected to the chip supply voltage. The output terminal of the fifth PMOS transistor is commonly connected to the first end of the charging capacitor, the input terminal of the third NMOS transistor, and the non-inverting input terminal of the comparator. The inverting input terminal of the comparator is used to connect the charging reference voltage. The output terminal of the comparator is used to provide a fixed conduction time signal. The control terminal of the third NMOS transistor is used to connect the inverted signal of the switching frequency. The second end of the charging capacitor and the output terminal of the third NMOS transistor are both grounded.

10. The COT control circuit for a switching power supply according to claim 9, characterized in that, The fifth PMOS transistor and the first PMOS transistor have the same length and width but different m values, and are used to generate a charging current proportional to the input current.

Images