Input tube anti-breakdown structure in wide power supply range

Abstract

The invention discloses an input tube counterattack punch-through structure in a wide power supply range, relates to the technical field of integrated circuits, and protects an input tube from being broken down when input voltage is relatively high. According to the structure, bias changing along with input is provided for the voltage-withstanding tube through the redundancy differential pair, it is guaranteed that the voltage difference between a collector electrode and an emitter electrode of the input tube is always located at a small constant value and does not change along with the change of input voltage, and the input tube is prevented from being broken down when the input voltage is high.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and specifically to an anti-breakdown structure for the input transistors of an operational amplifier with a wide power supply range under the BCD process. Background Art

[0002] For an operational amplifier with a wide power supply range, when the power supply voltage is high, a dedicated high-voltage withstand transistor is required to bear most of the power supply voltage. However, in some cases, only the high-voltage withstand transistor cannot ensure that some transistors in the circuit are not broken down. Therefore, the present invention proposes an anti-breakdown structure for the input transistors under a wide power supply range. Summary of the Invention

[0003] The technical solution adopted by the present invention utilizes a pair of redundant differential pairs, connects their inputs to the inputs of the actual differential pairs, and ensures that the input transistors are prevented from being broken down when the input voltage is high. The invention includes ordinary bipolar input differential pair transistors Q1, Q2, ordinary PMOS redundant differential pair transistors M1, M2, ordinary PMOS transistor M3, high-voltage withstand PLDMOS transistors M4, M5, M6, M7, M8, M9, M10, current sources I1, I2, I3, I4, polysilicon resistors R1, R2, R3.

[0004] The gates of the voltage-resistant PLDMOS transistors M8, M9, and M10 are all connected to Vbias. The base of the ordinary bipolar transistor Q1 is connected to the non-inverting input terminal of the operational amplifier. The base of the ordinary bipolar transistor Q2 is connected to the inverting input terminal of the operational amplifier. The current source I2 is connected between the positive power supply and the source terminal of the voltage-resistant PLDMOS transistor M9. The current source I3 is connected between the positive power supply and the source terminal of the voltage-resistant PLDMOS transistor M10. The emitter of the ordinary bipolar transistor Q1 is connected to the drain terminal of the voltage-resistant PLDMOS transistor M9. The emitter of the ordinary bipolar transistor Q2 is connected to the drain terminal of the voltage-resistant PLDMOS transistor M10. The source terminal of the voltage-resistant PLDMOS transistor M6 is connected to the collector of the ordinary bipolar transistor Q1. The source terminal of the voltage-resistant PLDMOS transistor M7 is connected to the collector of the ordinary bipolar transistor Q2. The polysilicon resistor R2 is connected between the drain terminal of the voltage-resistant PLDMOS transistor M6 and the negative power supply. The polysilicon resistor R3 is connected between the drain terminal of the voltage-resistant PLDMOS transistor M7 and the negative power supply. The gates of the voltage-resistant PLDMOS transistors M5, M6, and M7 are connected to the gate of the voltage-resistant PLDMOS transistor M4. The current source I1 is connected between the positive power supply and the source terminal of the voltage-resistant PLDMOS transistor M8. The drain of the voltage-resistant PLDMOS transistor M8 is connected together with the sources of the ordinary PMOS transistors M1, M2, and M3. The gate of the ordinary PMOS transistor M1 is connected to the non-inverting input terminal of the operational amplifier. The gate of the ordinary PMOS transistor M2 is connected to the inverting input terminal of the operational amplifier. The gate and the drain of the ordinary PMOS transistor M3 are connected. The source of the voltage-resistant PLDMOS transistor M4 is connected to the drain of the ordinary PMOS transistor M3. The gate and the drain of the voltage-resistant PLDMOS transistor M4 are connected. The current source I4 is connected between the drain of the voltage-resistant PLDMOS transistor M4 and the negative power supply. The drains of the ordinary PMOS transistors M1 and M2 are connected to the source of the voltage-resistant PLDMOS transistor M5. The polysilicon resistor R1 is connected between the drain of the voltage-resistant PLDMOS transistor M5 and the negative power supply.

[0005] Figure 1 This is the anti-breakdown circuit diagram of the input transistor proposed by the present invention.

[0006] Figure 2 For the input transistors Q1 / Q2V CE The simulation diagram showing the variation with the input common-mode voltage. Specific implementation

[0007] To make the above features of the present invention clearer, the following will give a detailed description of the specific implementation of the present invention in conjunction with the drawings.

[0008] Figure 1 It shows the anti-breakdown circuit structure of the input transistor under a wide power supply proposed by the present invention. Among them, IN1 is the non-inverting input terminal of the operational amplifier, and IN2 is the inverting input terminal of the operational amplifier. VBIAS is the bias voltage terminal.

[0009] When the power supply voltage is relatively high, most of the power supply voltage in the branches where Q1 and Q2 are located is borne by M9, M10, M6, and M7 to prevent the input transistors Q1 and Q2 from being broken down. The branch currents of the input transistors Q1 and Q2 are fixed at I2 and I3 respectively. The collector current formula of the bipolar transistor is:

[0010]

[0011] In the formula: I C is the collector current of the bipolar transistor, I S is the saturation current of the bipolar transistor, V T is the thermal voltage. V BE is the voltage difference between the base and the collector.

[0012] It can be seen from formula (1) that when I C is constant, V BE is constant. Figure 1 The collector current of Q1 in is constant at I1. When the voltages of the two input terminals are 0, M9 and M6 jointly bear most of the power supply voltage; when the voltages of the two input terminals are relatively low, the emitter potentials of Q1 and Q2 tubes also decrease as the input voltage decreases. At this time, the voltages across M6 and M7 will decrease, and most of the power supply voltage drops across M9 and M10; when the voltages of the two input terminals are relatively high, the emitter potentials of Q1 and Q2 tubes also increase as the input voltage increases. At this time, M9 and M10 can only bear a small part of the power supply voltage. To ensure that Q1 and Q2 are not broken down, the excess power supply voltage must be borne by M6 and M7.

[0013] When the voltages of the two input terminals are relatively high, M6 and M7 must bear most of the power supply voltage. If M6 and M7 are breakdown-resistant NLDMOS transistors, the impedance seen from the collectors of Q1 / Q2 upwards is much greater than the impedance seen downwards. At this time, the collector potentials of Q1 / Q2 will be obtained by dividing the voltage between the two impedances described above, that is, the collector potentials of Q1 / Q2 are close to the negative power supply rail. In this case, when the voltages of the two input terminals are relatively high, the voltage of the emitter of Q1 / Q2 increases accordingly. At this time, the voltage difference between the collector voltage and the emitter voltage of Q1 / Q2 becomes very large, exceeding the voltage that Q1 / Q2 can withstand, resulting in Q1 / Q2 being broken down.

[0014] Therefore, M6 and M7 can only be PLDMOS. After determining that M6 and M7 can only be Figure 1 the shown PLDMOS, it is also necessary to consider how to bias the gates of M6 and M7. If the gates of M6 and M7 are fixed-biased, to ensure that the input transistors Q1 / Q2 can still be in the amplification region when the input voltage is relatively low, the bias potential of the gates of M6 and M7 must be close to the negative power supply. The drain current formula in the saturation region of the PMOS transistor is

[0015]

[0016] Where: I D is the drain current of the PMOS, μ p is the hole mobility, Cox is the gate oxide capacitance per unit area, V GS is the potential difference between the gate and source of the PMOS transistor, V TH is the threshold voltage of the PMOS.

[0017] It can be seen from Equation (2) that when I D is constant, V GS is constant.

[0018] The drain currents of M6 and M7 are constantly I2 and I3. Therefore, when the sum of the gate potentials of M6 and M7 approaches the negative power supply, their source potentials are also very close to the negative power supply rail, that is, the collector potential of Q1 / Q2 approaches the negative power supply rail. If the potentials of the two input terminals are relatively high, the voltage at the emitter of Q1 / Q2 increases accordingly. At this time, the difference between the collector voltage and the emitter voltage of Q1 / Q2 becomes very large, exceeding the voltage that Q1 / Q2 can withstand, resulting in Q1 / Q2 being broken down. Therefore, the gate potentials of M6 and M7 cannot be fixed potentials.

[0019] As described above, to ensure that the input transistors Q1 / Q2 are not broken down, M6 and M7 must be PLDMOS and the gate potentials of the two must change with the input. Figure 1 The structure composed of M1, M2, M3, M4, M5, M8, I1, I4, and R1 in

[0020] V G6,7 = V in,cm - V GS1,2 + V GS3 + V GS4 (3)

[0021] Where V G6,7 is the gate potential of M6 and M7, V in，cm is the input common-mode voltage, V GS is the gate-source voltage of the transistor.

[0022]

[0023] Where I 1,2 is the drain current of M1 and M2 at the input common-mode voltage.

[0024] I1, I2, I 1,2 are constant currents, then the gate-source voltages V of M1, M2, M3, M4, and M5GS If it is a fixed value, from equation (3), it can be known that the gate potentials of M6 and M7 change with the change of the common-mode input voltage.

[0025] V C1,2 = V in,cm - V GS1,2 + V GS3 + V GS4 - V GS6,7 (5)

[0026] In the formula, V C1,2 is the collector potential of Q1 and Q2.

[0027] V E1,2 = V in,cm - V BE1,2 (6)

[0028] In the formula, V E1,2 is the emitter potential of Q1 and Q2.

[0029] V CE1,2 = V BE1,2 - V GS1,2 - V GS6,7 + V GS3 + V GS4 (7)

[0030] In the formula, V CE1,2 is the voltage difference between the collector and emitter of Q1 / Q2.

[0031] Figure 2 shows the simulation diagram of Q1 / Q2 V CE changing with the input common-mode voltage. It can be seen from the figure that the V CE of Q1 / Q2 remains constant, avoiding the breakdown of the input transistor when the input voltage is too high.

[0032] The current sources I2 and I3 are constant values and equal, then the gate-source voltages of M6 and M7 are constant values. From equation (7), it can be known that the V CE of Q1 / Q2 is constant and this value is relatively small. At this time, when the input common-mode voltage changes arbitrarily within the input range of Q1 / Q2, Q1 / Q2 will not have the risk of breakdown.

[0033] In summary, the present invention provides a structure for preventing the input transistor from being broken down. The redundant differential pair is used to provide a bias that changes with the input for the original withstand voltage transistor, so that the V CE of the input transistor remains constant and its value is small within its common-mode input range, preventing the input transistor from being broken down.

Claims

1. An input tube anti-breakdown structure under a wide power supply range, characterized in that The input transistor anti-breakdown structure under a wide power supply range includes a first PNP transistor, a second PNP transistor, a first ordinary PMOS transistor, a second ordinary PMOS transistor, a third ordinary PMOS transistor, a fourth voltage-resistant PLDMOS transistor, a fifth voltage-resistant PLDMOS transistor, a sixth voltage-resistant PLDMOS transistor M6, a seventh voltage-resistant PLDMOS transistor, an eighth voltage-resistant PLDMOS transistor, a ninth voltage-resistant PLDMOS transistor, a tenth voltage-resistant PLDMOS transistor, a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first input terminal, a second input terminal, a positive power supply, and a negative power supply, where: The base of the first PNP transistor and the gate of the first ordinary PMOS transistor are both connected to the first input terminal; the base of the second PNP transistor and the gate of the second ordinary PMOS transistor are both connected to the second input terminal; the first current source is connected between the positive power supply and the source terminal of the eighth high-voltage-resistant PLDMOS transistor; the second current source is connected between the positive power supply and the source terminal of the ninth high-voltage-resistant PLDMOS transistor; the third current source is connected between the positive power supply and the source terminal of the tenth high-voltage-resistant PLDMOS transistor; the emitter of the first PNP transistor is connected to the drain terminal of the ninth high-voltage-resistant PLDMOS transistor; the emitter of the second PNP transistor is connected to the drain terminal of the tenth high-voltage-resistant PLDMOS transistor; the source terminal of the sixth high-voltage-resistant PLDMOS transistor is connected to the collector of the first PNP transistor; the source terminal of the seventh high-voltage-resistant PLDMOS transistor is connected to the collector of the second PNP transistor; the first resistor is connected between the drain terminal of the fifth high-voltage-resistant PLDMOS transistor and the negative power supply; the second resistor is connected between the drain terminal of the sixth high-voltage-resistant PLDMOS transistor and the negative power supply; the third resistor is connected between the drain terminal of the seventh high-voltage-resistant PLDMOS transistor and the negative power supply; the gates of the fourth to seventh high-voltage-resistant PLDMOS transistors are all connected to the drain of the fourth high-voltage-resistant PLDMOS transistor; the sources of the first to third ordinary PMOS transistors are all connected to the drain of the eighth high-voltage-resistant PLDMOS transistor; the gate and drain of the third ordinary PMOS transistor are both connected to the source of the fourth high-voltage-resistant PLDMOS transistor M4; the fourth current source is connected between the drain of the fourth high-voltage-resistant PLDMOS transistor and the negative power supply; the drains of the first and second ordinary PMOS transistors are both connected to the source of the fifth high-voltage-resistant PLDMOS transistor; the gates of the eighth to tenth high-voltage-resistant PLDMOS transistors are all connected to the bias voltage V BIAS ; the first PNP transistor and the second PNP transistor are input transistors; the first ordinary PMOS transistor and the second ordinary PMOS transistor are redundant differential pairs.

2. The input tube anti-breakdown structure under a wide power supply range according to claim 1, wherein The first PNP transistor and the second PNP transistor have the same size; the second current source and the third current source have the same current value; the eighth voltage-resistant PLDMOS transistor, the ninth voltage-resistant PLDMOS transistor, and the tenth voltage-resistant PLDMOS transistor have the same size; the sixth voltage-resistant PLDMOS transistor and the seventh voltage-resistant PLDMOS transistor have the same size; the first resistor, the second resistor, and the third resistor have the same size; the first ordinary PMOS transistor, the second ordinary PMOS transistor, and the third ordinary PMOS transistor have the same size; the current value of the first current source is twice the current value of the fourth current source; the current value of the second current source is four times the current value of the first current source; the fourth voltage-resistant PLDMOS transistor and the fifth voltage-resistant PLDMOS transistor have the same size; the size of the sixth voltage-resistant PLDMOS transistor is four times the size of the fifth voltage-resistant PLDMOS transistor.

3. The input tube anti-breakdown structure under a wide power supply range according to claim 1, characterized in that, The first input terminal signal and the second input terminal signal are the same and are the common-mode input voltage; the branch where the fourth voltage-resistant PLDMOS transistor and the fifth voltage-resistant PLDMOS transistor are located provides a gate voltage bias that varies with the input for the sixth voltage-resistant PLDMOS transistor and the seventh voltage-resistant PLDMOS transistor, which makes the collector potential of the first PNP transistor vary with the first input terminal signal and the collector potential of the second PNP transistor vary with the second input terminal signal. Finally, the emitter-collector voltage of the two input transistors remains constant under the change of the input common-mode voltage, avoiding the input transistors from being broken down when the input common-mode voltage is relatively high.

4. The input tube anti-breakdown structure under a wide power supply range according to claim 1, characterized in that The positive power supply range is +2.3V to +18V; the negative power supply range is -18V to -2.3V.

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