Constant starting time generating circuit

Abstract

The invention provides a constant starting time generation circuit which comprises a first RS trigger I1, a comparison signal control circuit, a first comparison signal generation circuit, a second comparison signal generation circuit, a reset signal control circuit, a test auxiliary circuit and a selector I2, and the second end of the test auxiliary circuit is connected to the setting end of the first RS trigger I1 through the selector I2. An output signal of the first RS trigger I1 is calibrated through the test auxiliary circuit and the reset signal control circuit; an output signal of a previous-stage circuit is connected to the setting end of the first RS trigger I1 through the selector I2, and the input delay of the reset end of the first RS trigger I1 is eliminated through dynamic adjustment of the reset signal control circuit. According to the invention, the foreground calibration mode is utilized to calibrate the resistance and capacitance errors, and the output delay of the comparator is dynamically adjusted and calibrated after entering the normal working mode, so that the accurate control of the constant starting time is realized, and the working frequency of the switching power supply is accurately controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and particularly relates to a constant on-time generation circuit. Background Art

[0002] Constant On-Time (COT) switching power supplies have been widely used in recent years due to their advantages such as simple structure, fast response speed, and high low-load efficiency. Figure 1 is the basic principle block diagram of a constant on-time controlled buck switching power supply (BUCK). As Figure 1 shown, when the output voltage VOUT is lower than the reference voltage VREF, the output voltage VTRIG of the comparator X0 will increase. After receiving the VTRIG signal, the constant on-time generation circuit I0 will generate a pulse signal with a fixed time width TON to the subsequent control logic. The control logic will turn on the PMOS switch tube MP0 for this fixed time to increase VOUT, realizing the closed-loop control of VOUT.

[0003] Compared with traditional Pulse Width Modulation (PWM) switching power supplies, a disadvantage of constant on-time controlled switching power supplies is that there is no clock input with a fixed frequency. Its operating frequency or period is determined by its input and output voltages and the constant on-time. Taking the buck switching power supply as an example, according to the principle that the change in the inductor L current is 0 within the same period in the steady state, the current increase value when the PMOS switch tube MP0 is on is equal to the current decrease value when the NMOS switch tube MN0 is on, that is, (VIN - VOUT) / L * TON = VOUT / L * (T - TON), where VIN is the input voltage, VOUT is the output voltage, L is the inductance value, TON is the constant on-time, and T is the switching period. After simplification, the period T = VIN / VOUT * TON. Because the frequency is not fixed, it will cause switching noises of various frequencies inside the system. Therefore, an improved constant on-time generation circuit will dynamically adjust the constant on-time according to the input voltage and the output voltage, making the on-time proportional to VOUT / VIN and keeping the period constant.

[0004] Figure 2It is an improved constant on-time generation circuit commonly used at present. The operational amplifier A1, PMOS transistor MP1, and resistor R1 form a feedback loop, and under the control of the input voltage VIN, a current value VIN / R1 is generated on the load resistor R1. The PMOS transistors MP2 and MP1 form a current mirror, mirroring the current on the resistor R1 to the capacitor C1, and charging C1 when the switch S2 is off. Its working process is as follows: In the initial state, S2 is closed, pulling down the voltage of the upper plate of C1. The comparator X1 outputs 0, and the reset signal of the RS flip-flop I1 is invalid. After the constant on-time generation circuit receives the trigger signal VTRIG sent by the previous-stage circuit, the RS flip-flop I1 is set, and the output VTON becomes 1. At the same time, its control switch S2 is turned off, and MP2 starts to charge C1. The charging current is equal to VIN / R1. When the voltage of the upper plate of C1 is higher than the output voltage VOUT, the comparator X1 flips and outputs 1, resetting the RS flip-flop. The output VTON becomes 0, and at the same time, S2 is closed, and the circuit returns to the initial state. The duration of the high voltage 1 of VTON, that is, the constant on-time, is equal to the time when C1 is charged to VOUT. In the ideal state, VTON = C1 * VOUT / (VIN / R1) = VOUT / VIN * C1 * R1, which is proportional to VOUT / VIN, and can make the theoretical switching period constant. However, there is a certain delay in the comparator flip in the actual circuit, and it cannot flip on time when the voltage of the upper plate of C1 is charged to the VOUT voltage. In addition, the values of the capacitor C1 and the resistor R1 will vary with the process. There will still be a considerable randomness in the period of the switching power supply.

[0005] Based on this, a new solution is needed to more accurately control the constant on-time and thus accurately control the switching frequency of the switching power supply. Summary of the Invention

[0006] The object of the present invention is to provide a constant on-time generation circuit that can accurately control the constant on-time according to the changes in the input and output voltages of the switching power supply, and thus accurately control the switching frequency of the switching power supply.

[0007] According to one aspect of the present invention, a constant on-time generation circuit is provided, including a first RS flip-flop I1, a comparison signal control circuit, a first comparison signal generation circuit, a second comparison signal generation circuit, a reset signal control circuit, a test auxiliary circuit, and a selector I2. Among them, the comparison signal control circuit is connected to the first end of the first comparison signal generation circuit and the first end of the second comparison signal generation circuit. The second end of the first comparison signal generation circuit is connected to the first end of the reset signal control circuit. The second end of the reset signal control circuit is connected to the reset end of the first RS flip-flop I1. The second end of the second comparison signal generation circuit is connected to the first end of the test auxiliary circuit. The second end of the test auxiliary circuit is connected to the first input end of the selector I2. The second input end of the selector I2 is connected to the output signal of the previous-stage circuit. The output end of the selector I2 is connected to the set end of the first RS flip-flop I1. In the calibration mode, the second end of the test auxiliary circuit is connected to the set end of the first RS flip-flop I1 through the selector I2, and the output signal of the first RS flip-flop I1 is calibrated through the test auxiliary circuit and the reset signal control circuit. In the normal operation mode, the output signal of the previous-stage circuit is connected to the set end of the first RS flip-flop I1 through the selector I2, and the input delay at the reset end of the first RS flip-flop I1 is eliminated through the dynamic adjustment of the reset signal control circuit.

[0008] In the constant on-time generation circuit provided by the present invention, the comparison signal control circuit includes a first amplifier A1, a first PMOS transistor MP1, a resistor R1, and a second PMOS transistor MP2. The negative input end of the first amplifier A1 is connected to the input voltage. The positive input end of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1. The output end of the first amplifier A1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply. The second end of the resistor R1 is grounded. The drain of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generation circuit and the first end of the second comparison signal generation circuit.

[0009] In the constant on-time generation circuit provided by the present invention, the first comparison signal generation circuit includes a first switch S1, a first capacitor C1, and a second switch S2. The first end of the first switch S1 is connected to the drain of the second PMOS transistor MP2. The second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2, and the first end of the reset signal control circuit. The lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

[0010] In the constant on-time generating circuit provided by the present invention, the reset signal control circuit includes a sampling compensation circuit and a first comparator X1. The positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1. The negative input terminal of the first comparator X1 is connected to the sampling compensation circuit. The output terminal of the first comparator X1 is connected to the reset terminal of the first RS flip-flop I1.

[0011] In the constant on-time generating circuit provided by the present invention, the sampling compensation circuit includes a third switch S3, a second amplifier A2, and a third capacitor C3. The first terminal of the third switch S3 is connected to the upper plate of the first capacitor C1. The positive input terminal of the second amplifier A2 is connected to the output voltage. The negative input terminal of the second amplifier A2 is connected to the second terminal of the third switch S3 and the first terminal of the third capacitor C3. The output terminal of the second amplifier A2 is connected to the negative input terminal of the first comparator X1 and the second terminal of the third capacitor C3.

[0012] In the constant on-time generating circuit provided by the present invention, the second comparison signal generating circuit includes a fourth switch S4 and a second capacitor C2. The first terminal of the fourth switch S4 is connected to the drain terminal of the second PMOS transistor MP2. The second terminal of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first terminal of the test auxiliary circuit. The lower plate of the second capacitor C2 is grounded.

[0013] In the constant on-time generating circuit provided by the present invention, the test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input terminal of the third amplifier A3 is connected to the output voltage. The negative input terminal of the third amplifier A3 is connected to the first terminal of the sixth switch S6 and the first terminal of the fourth capacitor C4. The output terminal of the third amplifier A3 is connected to the second terminal of the fourth capacitor C4 and the negative input terminal of the second comparator X2. The positive input terminal of the second comparator X2 is connected to the first terminal of the fifth switch S5, the second terminal of the sixth switch S6, and the upper plate of the second capacitor C2. The output terminal of the second comparator X2 is connected to the first input terminal of the selector I2. The second terminal of the fifth switch S5 is grounded.

[0014] Implementing the constant on-time generation circuit of the present invention has the following beneficial effects: The constant on-time generation circuit provided by the present invention includes a sampling and compensation circuit composed of a third switch S3, a second amplifier A2, and a third capacitor C3 to dynamically adjust the voltage at the negative input terminal of the first comparator, so that the upper plate of the first capacitor is accurately flipped when charged to the VOUT voltage; at the same time, a test and auxiliary circuit composed of a third amplifier, a fifth switch, a sixth switch, a fourth capacitor, and a second comparator is used to perform foreground calibration on the constant on-time generation circuit to eliminate the change in capacitance and resistance values caused by process fluctuations; finally, accurately control the output constant on-time, and further accurately control the switching frequency of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained according to the provided drawings: Figure 1 It is a schematic diagram of a constant on-time controlled buck switching power supply (BUCK); Figure 2 It is a circuit diagram of an existing improved constant on-time generation circuit; Figure 3 As shown Figure 2 It is a timing diagram of the improved constant on-time generation circuit shown; Figure 4 It is a schematic diagram of the constant on-time generation circuit provided by an embodiment of the present invention; Figure 5 It is a circuit diagram of the constant on-time generation circuit provided by an embodiment of the present invention; Figure 6 For Figure 5 It is an equivalent circuit of the constant on-time generation circuit shown in the foreground calibration mode; Figure 7 For Figure 5 It is a timing diagram of the constant on-time generation circuit shown in the foreground calibration mode; Figure 8 For Figure 5 It is an equivalent circuit of the constant on-time generation circuit shown in the normal working mode; Figure 9 For Figure 5 It is a timing diagram of the constant on-time generation circuit shown in the normal working mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0018] The general idea of the present invention is as follows: in the foreground calibration mode, the constant on-time generation circuit outputs a square wave with a period of the target constant on-time, which is convenient for measurement and calibration of the resistance and capacitance values; in the normal working mode, the delay of the comparator is dynamically calibrated to achieve accurate control of the constant on-time.

[0019] To better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the drawings of the specification and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. Without conflict, the technical features in the embodiments of the present invention and the embodiments can be combined with each other.

[0020] Figure 1 FIG. 13 is a schematic diagram of a conventional constant on-time control (COT) buck switching power supply (BUCK). The control logic controls the switching of the power PMOS transistor MP0 and the power NMOS transistor MN0 to output a square wave, and then filters the output voltage VOUT through a filter composed of an inductor and a capacitor. When VOUT is lower than the reference voltage VREF, the output voltage VTRIG of the comparator X0 becomes logic 1. After receiving the VTRIG signal, the constant on-time generation circuit I0 generates a pulse signal VTON with a fixed time length. The control logic circuit makes the power PMOS transistor conduct for a fixed length of time according to this signal, so that VOUT is pulled up once or several times until VOUT is higher than VREF, realizing the closed-loop control of the output amplitude of VOUT.

[0021] Figure 2It is an improved constant on-time generation circuit for the prior art, which is used to generate a pulse with a constant on-time in a constant on-time controlled switching power supply. Among them, the operational amplifier A1, the PMOS transistor MP1 and the resistor R1 form a feedback loop, and under the control of VIN, a current value VIN / R1 is generated on the load resistor R1. The PMOS transistor MP2 and the PMOS transistor MP1 form a current mirror, which mirrors the current on the load resistor R1 to the capacitor C1, and charges the capacitor C1 when the switch S2 is disconnected. The working process is as follows: In the initial state, the switch S2 is closed to pull down the voltage of the upper plate of the capacitor C1, the comparator X1 outputs 0, and the reset signal of the RS flip-flop I1 is invalid; after the constant on-time generation circuit receives the trigger signal VTRIG sent by the previous-stage circuit, the RS flip-flop I1 is set, the output VTON becomes 1, and at the same time its control switch S2 is disconnected, and the PMOS transistor MP2 starts to charge the capacitor C1, and the charging current is equal to VIN / R1; when the voltage of the upper plate of the capacitor C1 is higher than the output voltage VOUT, the comparator X1 flips and outputs 1; the RS flip-flop is reset, the output VTON becomes 0, and at the same time the switch S2 is closed, and the circuit returns to the initial state. The duration of the high voltage 1 of VTON, that is, the constant on-time, is equal to the time when the capacitor C1 is charged to VOUT. In the ideal state, VTON = C1 * VOUT / (VIN / R1) = VOUT / VIN * C1 * R1, which is proportional to VOUT / VIN, and can make the theoretical switching period constant. However, due to various non-ideal factors such as comparator flip-flop delay and resistor-capacitor value error, accurate control cannot be achieved.

[0022] Figure 4 The schematic diagram of the constant on-time generation circuit provided by an embodiment of the present invention is as follows Figure 4As shown, the constant on-time generation circuit provided by the present invention includes a first RS flip-flop I1, a comparison signal control circuit 100, a first comparison signal generation circuit 200, a second comparison signal generation circuit 300, a reset signal control circuit 400, a test auxiliary circuit 500, and a selector I2. Among them, the comparison signal control circuit 100 is connected to the first end of the first comparison signal generation circuit 200 and the first end of the second comparison signal generation circuit 300. The second end of the first comparison signal generation circuit 200 is connected to the first end of the reset signal control circuit 400. The second end of the reset signal control circuit 400 is connected to the reset terminal of the first RS flip-flop I1. The second end of the second comparison signal generation circuit 300 is connected to the first end of the test auxiliary circuit 500. The second end of the test auxiliary circuit 500 is connected to the first input terminal of the selector I2. The second input terminal of the selector I2 is connected to the output signal of the previous-stage circuit. The output terminal of the selector I2 is connected to the set terminal of the first RS flip-flop I1. In the calibration mode, the second end of the test auxiliary circuit 500 is connected to the set terminal of the first RS flip-flop I1 through the selector I2, and the output signal of the first RS flip-flop I1 is calibrated through the test auxiliary circuit 500 and the reset signal control circuit 400. In the normal operation mode, the output signal of the previous-stage circuit is connected to the set terminal of the first RS flip-flop I1 through the selector I2, and the input delay at the reset terminal of the first RS flip-flop I1 is eliminated through the dynamic adjustment of the reset signal control circuit 400.

[0023] Figure 5 It is the circuit diagram of the constant on-time generation circuit provided by an embodiment of the present invention. Specifically, in an embodiment of the present invention, the comparison signal control circuit 100 includes a first amplifier A1, a first PMOS transistor MP1, a resistor R1, and a second PMOS transistor MP2. The negative input terminal of the first amplifier A1 is connected to the input voltage. The positive input terminal of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1. The output terminal of the first amplifier A1 is connected to the gate terminal of the first PMOS transistor MP1 and the gate terminal of the second PMOS transistor MP2. The source terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply. The second end of the resistor R1 is grounded. The drain terminal of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generation circuit and the first end of the second comparison signal generation circuit.

[0024] Specifically, in an embodiment of the present invention, the first comparison signal generation circuit 200 includes a first switch S1, a first capacitor C1, and a second switch S2. The first end of the first switch S1 is connected to the drain of the second PMOS transistor MP2. The second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2, and the first end of the reset signal control circuit. The lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

[0025] Specifically, in an embodiment of the present invention, the reset signal control circuit 400 includes a sampling and compensation circuit 410 and a first comparator X1. The positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1. The negative input terminal of the first comparator X1 is connected to the sampling and compensation circuit 410. The output terminal of the first comparator X1 is connected to the reset terminal of the first RS flip-flop I1.

[0026] Specifically, in an embodiment of the present invention, the sampling and compensation circuit 410 includes a third switch S3, a second amplifier A2, and a third capacitor C3. The first end of the third switch S3 is connected to the upper plate of the first capacitor C1. The positive input terminal of the second amplifier A2 is connected to the output voltage. The negative input terminal of the second amplifier A2 is connected to the second end of the third switch S3 and the first end of the third capacitor C3. The output terminal of the second amplifier A2 is connected to the negative input terminal of the first comparator X1 and the second end of the third capacitor C3.

[0027] Specifically, in an embodiment of the present invention, the second comparison signal generation circuit includes a fourth switch S4 and a second capacitor C2. The first end of the fourth switch S4 is connected to the drain of the second PMOS transistor MP2. The second end of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first end of the test auxiliary circuit. The lower plate of the second capacitor C2 is grounded.

[0028] Specifically, in an embodiment of the present invention, the test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input terminal of the third amplifier A3 is connected to the output voltage. The negative input terminal of the third amplifier A3 is connected to the first end of the sixth switch S6 and the first end of the fourth capacitor C4. The output terminal of the third amplifier A3 is connected to the second end of the fourth capacitor C4 and the negative input terminal of the second comparator X2. The positive input terminal of the second comparator X2 is connected to the first end of the fifth switch S5, the second end of the sixth switch S6, and the upper plate of the second capacitor C2. The output terminal of the second comparator X2 is connected to the first input terminal of the selector I2. The second end of the fifth switch S5 is grounded.

[0029] A constant on-time generation circuit of the present invention first calibrates the errors of resistors and capacitors using a foreground calibration mode, and after entering the normal operating mode, accurately controls the constant on-time by dynamically adjusting the output delay of a calibration comparator, thereby accurately controlling the operating frequency of a switching power supply.

[0030] The following combines Figure 6 and Figure 7 to elaborate on the working process of the foreground calibration mode of the present invention: Refer to Figure 6, in the foreground calibration mode, the first selector I2 selects the output of the second comparator X2 as the set signal of the first RS flip-flop I1. In the initial state, the first switch S1 is closed, the fourth switch S4 is open, and at the same time the second switch S2 and the third switch S3 are open. The second PMOS transistor MP2 charges the first capacitor C1, and the current is VIN / R1. When the voltage of the upper plate of the first capacitor C1 exceeds the negative terminal voltage VR1 of the first comparator X1, the output voltage VRST of the first comparator X1 becomes 1, and the output voltage VTON of the first RS flip-flop I1 becomes 0. When the output voltage VTON of the first RS flip-flop I1 becomes 0, the first switch S1 is opened, the fourth switch S4 is closed, the fifth switch S5 and the sixth switch S6 are open, and the second PMOS transistor MP2 starts to charge the second capacitor C2. During the charging process of the second capacitor C2, the third switch S3 is closed, the voltage of the upper plate of the first capacitor C1 is sampled, and the difference between it and the output voltage VOUT is integrated onto the third capacitor C3 through the second amplifier A2, causing the output voltage VR1 of the second amplifier A2 to change in the opposite direction, that is, when the output voltage VOUT is higher than the voltage of the upper plate of the first capacitor C1, the output voltage VR1 of the second amplifier A2 increases, and when the output voltage VOUT is lower than the voltage of the upper plate of the first capacitor C1, the output voltage VR1 of the second amplifier A2 decreases. Then the third switch S3 is opened, and the second switch S2 is closed to clear the charge on the first capacitor C1. At this time, the second capacitor C2 is still in the charging process. Similarly, when the voltage of the upper plate of the second capacitor C2 exceeds the negative terminal voltage VR2 of the second comparator X2, the output voltage VSET of the second comparator X2 becomes 1, and the output voltage VTON of the first RS flip-flop I1 becomes 1. When the output voltage VTON of the first RS flip-flop I1 becomes 1, the fourth switch S4 is opened, the first switch S1 is closed, the second switch S2 is opened, and the second PMOS transistor MP2 charges the first capacitor C1 again. During the charging process of the first capacitor C1, the sixth switch S6 is closed, the voltage of the upper plate of the second capacitor C2 is sampled, and the difference between it and the output voltage VOUT is integrated onto the fourth capacitor C4 through the third amplifier A3, causing the output voltage VR2 of the third amplifier A3 to change in the opposite direction, that is, when the output voltage VOUT is higher than the voltage of the upper plate of the second capacitor C2, the output voltage VR2 of the third amplifier A3 increases, and when the output voltage VOUT is lower than the voltage of the upper plate of the second capacitor C2, the output voltage VR2 of the third amplifier A3 decreases. The output voltage VTON of the first RS flip-flop I1 completes a cycle of change, and the waveform is a periodic square wave signal. After multiple cycles of circulation, the output voltage VR1 of the second amplifier A2 and the output voltage VR2 of the third amplifier A3 will be modulated to an amplitude slightly lower than VOUT, so that the final charging voltages of the first capacitor C1 and the second capacitor C2 are equal to the output voltage VOUT.The square wave period T of the output voltage VTON of the first RS flip-flop I1 is equal to VOUT / VIN*R1(C1 + C2). In the foreground test mode, the process deviations of the capacitance and resistance are understood by testing this frequency, and the frequency is calibrated by adjusting the value of R1. The calibrated value of R1 will be used in the normal operating mode.

[0031] The working process of the normal operating mode of the present invention will be described below in conjunction with Figure 8 and Figure 9 : In the normal operating mode as Figure 8 shown, the first selector I2 selects the output signal VTRIG of the previous-stage circuit as the set signal of the first RS flip-flop I1. The fifth switch S5, the sixth switch S6, the third amplifier A3, the second comparator X2, and the fourth capacitor C4 are all disconnected and excluded from the circuit. The first switch S1 and the fourth switch S4 are always closed. When the trigger signal VTRIG received from the previous-stage circuit is 1, the first RS flip-flop I1 outputs 1. At the same time, the second switch S2 is disconnected, and the second PMOS transistor MP2 charges the first capacitor C1 and the second capacitor C2, and the current is VIN / R1. When the upper plate voltage of the first capacitor C1 and the second capacitor C2 exceeds the negative terminal voltage VR1 of the first comparator X1, the output terminal VRST of the first comparator X1 becomes 1, and the output voltage VTON of the first RS flip-flop I1 becomes 0. The circuit outputs a constant-time turn-on pulse. During the waiting for the next VTRIG signal, the third switch S3 is closed to sample the upper plate voltage of the first capacitor C1 and the second capacitor C2, and the difference between it and the output voltage VOUT is integrated onto the third capacitor C3 through the second amplifier A2, causing the output voltage VR1 of the second amplifier A2 to change in the opposite direction, that is, when the output voltage VOUT is higher than the upper plate voltage of the first capacitor C1 and the second capacitor C2, the output voltage VR1 of the second amplifier A2 increases, and when the output voltage VOUT is lower than the upper plate voltage of the first capacitor C1 and the second capacitor C2, the output voltage VR1 of the second amplifier A2 decreases. Then the third switch S3 is disconnected, and the second switch S2 is closed to clear the charges on the first capacitor C1 and the second capacitor C2. After several cycles of adjustment, the output voltage VR1 of the second amplifier A2 will stabilize at a value slightly lower than VOUT, so that the final charging voltage of the first capacitor C1 and the second capacitor C2 is equal to VOUT. In this way, the width TON of a constant-time turn-on pulse is equal to VOUT / VIN*R1*(C1 + C2), that is, equal to the period value calibrated by the circuit in the foreground calibration mode. The switching power supply uses the constant turn-on time control with this time width, and its period is always equal to R1*(C1 + C2), unaffected by the input and output voltages and process deviations, achieving precise control.

[0032] In summary, the present invention provides a constant on-time generation circuit, which can accurately control the constant on-time according to the changes in the input and output voltages of the switching power supply, and thus accurately control the switching frequency of the switching power supply.

[0033] In each of the descriptions provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0034] Similarly, it should be understood that, in order to streamline this disclosure and assist in understanding one or more of the various inventive aspects, in the foregoing description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all the features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0035] Furthermore, those skilled in the art will appreciate that, although some embodiments herein include some features included in other embodiments but not others, the combination of features of different embodiments is meant to be within the scope of the present invention and forms different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

[0036] It should be noted that the above embodiments illustrate rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A constant on-time generation circuit, characterized in that, It includes a first RS flip-flop I1, a comparison signal control circuit (100), a first comparison signal generation circuit (200), a second comparison signal generation circuit (300), a reset signal control circuit (400), a test auxiliary circuit (500) and a selector I2. Among them, the comparison signal control circuit (100) is connected to the first end of the first comparison signal generation circuit (200) and the first end of the second comparison signal generation circuit (300). The second end of the first comparison signal generation circuit (200) is connected to the first end of the reset signal control circuit (400). The second end of the reset signal control circuit (400) is connected to the reset end of the first RS flip-flop I1. The second end of the second comparison signal generation circuit (300) is connected to the first end of the test auxiliary circuit (500). The second end of the test auxiliary circuit (500) is connected to the first input end of the selector I2. The second input end of the selector I2 is connected to the output signal of the previous-stage circuit. The output end of the selector I2 is connected to the set end of the first RS flip-flop I1. In the calibration mode, the second end of the test auxiliary circuit (500) is connected to the set end of the first RS flip-flop I1 through the selector I2, and the output signal of the first RS flip-flop I1 is calibrated through the test auxiliary circuit (500) and the reset signal control circuit (400). In the normal working mode, the output signal of the previous-stage circuit is connected to the set end of the first RS flip-flop I1 through the selector I2, and the input delay at the reset end of the first RS flip-flop I1 is eliminated through the dynamic adjustment of the reset signal control circuit (400).

2. The constant turn-on time generation circuit according to claim 1, wherein The comparison signal control circuit (100) includes a first amplifier A1, a first PMOS transistor MP1, a resistor R1 and a second PMOS transistor MP2. The negative input end of the first amplifier A1 is connected to the input voltage. The positive input end of the first amplifier A1 is connected to the drain of the first PMOS transistor MP1 and the first end of the resistor R1. The output end of the first amplifier A1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply. The second end of the resistor R1 is grounded. The drain of the second PMOS transistor MP2 is connected to the first end of the first comparison signal generation circuit and the first end of the second comparison signal generation circuit.

3. The constant turn-on time generating circuit according to claim 2, wherein The first comparison signal generation circuit (200) includes a first switch S1, a first capacitor C1 and a second switch S2. The first end of the first switch S1 is connected to the drain of the second PMOS transistor MP2. The second end of the first switch S1 is connected to the upper plate of the first capacitor C1, the first end of the second switch S2 and the first end of the reset signal control circuit. The lower plate of the first capacitor C1 and the second end of the second switch S2 are grounded.

4. The constant turn-on time generation circuit according to claim 3, characterized in that The reset signal control circuit (400) includes a sampling compensation circuit (410) and a first comparator X1. The positive input terminal of the first comparator X1 is connected to the upper plate of the first capacitor C1. The negative input terminal of the first comparator X1 is connected to the sampling compensation circuit (410). The output terminal of the first comparator X1 is connected to the reset terminal of the first RS flip-flop I1.

5. The constant turn-on time generation circuit according to claim 4, wherein The sampling compensation circuit (410) includes a third switch S3, a second amplifier A2, and a third capacitor C3. The first terminal of the third switch S3 is connected to the upper plate of the first capacitor C1. The positive input terminal of the second amplifier A2 is connected to the output voltage. The negative input terminal of the second amplifier A2 is connected to the second terminal of the third switch S3 and the first terminal of the third capacitor C3. The output terminal of the second amplifier A2 is connected to the negative input terminal of the first comparator X1 and the second terminal of the third capacitor C3.

6. The constant turn-on time generation circuit according to claim 2, wherein The second comparison signal generation circuit includes a fourth switch S4 and a second capacitor C2. The first terminal of the fourth switch S4 is connected to the drain terminal of the second PMOS transistor MP2. The second terminal of the fourth switch S4 is connected to the upper plate of the second capacitor C2 and the first terminal of the test auxiliary circuit. The lower plate of the second capacitor C2 is grounded.

7. The constant turn-on time generation circuit according to claim 6, characterized in that, The test auxiliary circuit includes a third amplifier A3, a fifth switch S5, a sixth switch S6, a fourth capacitor C4, and a second comparator X2. The positive input terminal of the third amplifier A3 is connected to the output voltage. The negative input terminal of the third amplifier A3 is connected to the first terminal of the sixth switch S6 and the first terminal of the fourth capacitor C4. The output terminal of the third amplifier A3 is connected to the second terminal of the fourth capacitor C4 and the negative input terminal of the second comparator X2. The positive input terminal of the second comparator X2 is connected to the first terminal of the fifth switch S5, the second terminal of the sixth switch S6, and the upper plate of the second capacitor C2. The output terminal of the second comparator X2 is connected to the first input terminal of the selector I2. The second terminal of the fifth switch S5 is grounded.

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