A temperature compensated level shifting driver

Abstract

The present invention relates to the field of level conversion drivers for phased array circuits and systems, specifically a temperature-compensated level conversion driver, comprising: a logic level positive-to-negative conversion unit and a drive shaping unit connected thereto; the logic level positive-to-negative conversion unit comprising a feedback-enhanced transistor voltage drop unit formed by connecting P Schottky diodes in series with transistors, an enhancement-type transistor voltage drop unit formed by short-circuiting the drain and gate of M transistors, and positive temperature coefficient resistors RB1 and RB2. By introducing the feedback-enhanced transistor voltage drop unit formed by connecting P Schottky diodes in series with transistors, the enhancement-type transistor voltage drop unit formed by short-circuiting the drain and gate of M transistors, and the positive temperature coefficient resistors RB1 and RB2, temperature compensation is achieved while converting a positive logic level to a negative logic level. The present invention improves the temperature sensitivity of the flip level and is applicable to complex working environments with anti-interference requirements.

Description

Technical Field

[0001] The present invention relates to the field of level conversion drivers applied to phased array circuits and systems, and in particular to a temperature-compensated level conversion driver. Background Art

[0002] Existing phased array radar systems place high demands on the RF performance of transceiver components, including noise, power, and linearity. While integrated circuits manufactured using GaAs and GaN processes may have limitations in terms of integration compared to semiconductor processes like CMOS and SiGe, they offer significant advantages in RF performance. Therefore, to meet these high-performance requirements, integrated circuits using compound semiconductor processes like GaAs and GaN are widely used in phased array radar systems. With increasing system integration, the RF, analog, digital, and control circuits within the transceiver components are now integrated onto a single motherboard. Due to the high integration density of antenna systems and the complex operating environment of the array, drastic current or voltage fluctuations can introduce noise sources from both the power and ground lines. Impedance mismatches in transmission lines can also introduce reflected noise. Signal coupling within multilayer boards and electromagnetic induction between conductors can lead to crosstalk. These factors further stringently restrict the circuit's interference mitigation performance.

[0003] Integrated circuits using GaAs and GaN processes, such as digitally controlled attenuators, digitally controlled phase shifters, switches for transmitting and receiving amplification circuits, and multifunctional amplitude and phase control circuits, are commonly used within transceiver components. In phased array systems, these modules perform functions such as amplitude weighting, beam direction change, and switching between receive and transmit pulses, playing an irreplaceable role. These circuits require external digital circuit control. The most common control signals in radar systems include TTL mode (+5V / 0V) and LVTTL mode (+3.3V / 0V). However, switching crystals in compound semiconductor processes such as GaAs and GaN often require negative logic control, necessitating level-shifting drivers.

[0004] Currently, level-shifting drivers that use resistors and Schottky diodes for voltage division are stable at room temperature, but are susceptible to temperature fluctuations in high and low-temperature environments. For example, the HMC649A digitally controlled phase shifter requires a low-level input range of 0 to 0.2V and a high-level input range of Vdd ± 0.2V (Vdd is the power supply voltage). Related products like the NC13165C-618PD require a low-level input range of 0 to 0.4V and a high-level input range of 3.0 to 5.0V. These required low-level and high-level input ranges are significantly smaller, posing a risk in environments with high interference requirements.

[0005] Referring to the level conversion drivers disclosed in the invention patents CN110247651B, CN111682866B, CN104682967B, CN114567151B and CN119171903A, none of them mention the effect of temperature drift on the flip level. The Schottky diode used internally is connected in series in the level conversion branch, and the temperature drift characteristics of the Schottky diode itself will affect the flip level value of the input port of the level conversion circuit, making it easy to be disturbed under high and low temperature conditions and become unstable. Summary of the Invention

[0006] The present invention aims to address the aforementioned problem of temperature drift of the input-terminal flipping level of the level shifter driver itself under high and low temperature conditions, and to propose a temperature-compensated level shifter driver. The temperature-compensated level shifter driver is suitable for use in field-effect transistor processes such as GaAs and low-voltage GaN that do not have insulated gate complementary logic. The driver employs a series circuit structure comprising multiple devices, including a positive temperature coefficient resistor, an enhancement-mode transistor with Schottky diode feedback, and an enhancement-mode transistor with gate-drain shorting. The driver can achieve temperature compensation over a wide temperature range, thereby minimizing the temperature impact on the flipping level of the input port of the level shifter circuit, and providing enhanced immunity to noise and crosstalk interference.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] A temperature-compensated level conversion driver is used to convert an input positive logic level +5V / 0V or +3.3V / 0V into a negative logic level signal 0V / -5V, comprising: a logic level positive-to-negative conversion unit and a drive shaping unit connected thereto;

[0009] The logic level positive-to-negative conversion unit includes: two enhancement-mode transistor voltage drop units: a first enhancement-mode transistor voltage drop unit and a second enhancement-mode transistor voltage drop unit; four resistors: a resistor RB1, a resistor RB2, a resistor RB3, and a resistor RD1; two transistors: an enhancement-mode transistor E13 and a depletion-mode transistor D01; wherein:

[0010] One end of resistor RB1 is connected to the input signal VCI as a signal input terminal, and the other end is connected to the input of the first enhancement-mode transistor voltage drop unit. The first enhancement-mode transistor voltage drop unit is a feedback enhancement-mode transistor voltage drop unit composed of P Schottky diodes and P transistors connected in series, and its output end is connected to the input end of the first enhancement-mode transistor voltage drop unit. The second enhancement-mode transistor voltage drop unit is an enhancement-mode transistor voltage drop unit composed of M enhancement-mode transistors with their gates and drains short-circuited in series, and its output end is respectively connected to one end of resistor RB2 and one end of resistor RB3. The other end of resistor RB2 is connected to a negative power supply VSS, and the other end of resistor RB3 is connected to the gate of transistor E13. The source of transistor E13 is connected to the negative power supply VSS, and the drain is connected to one end of resistor RD1 and the gate of transistor D01, and serves as the output end of the logic level positive-to-negative conversion unit to output signal VCO. The drain of transistor D01 is grounded. The other end of resistor RD1 is connected to the source of transistor D01.

[0011] The drive shaping unit includes: a first inverting drive circuit, a second inverting drive circuit, a third inverting drive circuit and a fourth inverting drive circuit; the input end of the first inverting drive circuit is the input end of the drive shaping unit, which is connected to the output end of the logic level positive-to-negative conversion unit, and the output end is respectively connected to the input end of the second inverting drive circuit and the input end of the third inverting drive circuit; the output end of the second inverting drive circuit outputs a signal VON, and the output end of the third inverting drive circuit is connected to the input end of the fourth inverting drive circuit and then outputs a signal VOP; the signals VON and VOP output are complementary logic signals of 0V / -5V.

[0012] Furthermore, the first enhancement mode transistor voltage drop unit is a feedback enhancement mode transistor voltage drop unit composed of five Schottky diodes and five enhancement mode transistors connected in series, the five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4 and Schottky diode SD5; the five enhancement mode transistors are: transistor E01, transistor E02, transistor E03, transistor E04 and transistor E05; wherein: the positive end of the Schottky diode SD1 is connected to the resistor RB1 and the drain of the transistor E01, and the negative end is connected to the transistor The gate of the transistor E01; the positive end of the Schottky diode SD2 is connected to the source of the transistor E01 and the drain of the transistor E02, and the negative end is connected to the gate of the transistor E02; the positive end of the Schottky diode SD3 is connected to the source of the transistor E02 and the drain of the transistor E03, and the negative end is connected to the gate of the transistor E03; the positive end of the Schottky diode SD4 is connected to the source of the transistor E03 and the drain of the transistor E04, and the negative end is connected to the gate of the transistor E04; the positive end of the Schottky diode SD5 is connected to the source of the transistor E04 and the drain of the transistor E05, and the negative end is connected to the gate of the transistor E05;

[0013] The second enhancement-mode transistor voltage drop unit is composed of seven enhancement-mode transistors with their gates and drains short-circuited. The seven enhancement-mode transistors are: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11 and transistor E12; wherein: the drain of transistor E06 is connected to the gate and then to the source of transistor E05, the drain of transistor E07 is connected to the gate and then to the source of transistor E06, and the drain of transistor E08 is connected to the gate and then to the source of transistor E07; the drain of transistor E09 is connected to the gate and then to the source of transistor E08, the drain of transistor E10 is connected to the gate and then to the source of transistor E09, and the drain of transistor E11 is connected to the gate and then to the source of transistor E10; the drain of transistor E12 is connected to the gate and then to the source of transistor E11, and its source is the common point of the output of the second enhancement-mode transistor voltage drop unit connected to the second resistor RB2 and the third resistor RB3.

[0014] Furthermore, the drive shaping unit specifically includes: eight transistors: enhancement transistor E14, enhancement transistor E15, enhancement transistor E16, enhancement transistor E17, depletion transistor D02, depletion transistor D03, depletion transistor D04 and depletion transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4 and resistor RD5; wherein: the gate of transistor E14 is connected to the signal VCO as the input of the drive shaping unit; the source of transistor E14, transistor E15, transistor E16 and transistor E17 are all connected to VSS; transistor D02, transistor D03, transistor D04 and transistor The drains of transistors D05 are both grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14, forming a first inverting drive circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15, forming a second inverting drive circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16, forming a third inverting drive circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17, forming a fourth inverting drive circuit; the gates of the enhancement-mode transistors in each inverting drive circuit serve as input terminals, and the drains serve as output terminals.

[0015] Furthermore, the five Schottky diodes have the same size.

[0016] Furthermore, the transistor E01 , the transistor E02 , the transistor E03 , the transistor E04 , the transistor E05 , the transistor E06 , the transistor E07 , the transistor E08 , the transistor E09 , the transistor E10 , the transistor E11 , the transistor E12 and the transistor E13 have the same size.

[0017] Furthermore, the resistor RB1 , the resistor RB2 , the resistor RB3 , the resistor RD1 , the resistor RD2 , the resistor RD3 , the resistor RD4 , and the resistor RD5 are all positive temperature coefficient resistors with a sheet resistance greater than 400 ohms.

[0018] The temperature-compensated level-conversion driver of the present invention is based on the feedback-enhanced transistor voltage-drop unit composed of P Schottky diodes and transistors connected in series, the enhanced transistor voltage-drop unit composed of M transistor drains and gates short-circuited, and the combined action of multiple positive temperature coefficient resistors RB1 and RB2. While achieving conversion from a positive logic level to a negative logic level, it also realizes a temperature compensation function, thereby improving the temperature sensitivity of the flip level.

[0019] Compared with the traditional level conversion driver composed of a direct series structure of a resistor and a Schottky diode, the present invention can achieve the offset of the positive temperature coefficient and the negative temperature coefficient, and realize temperature compensation of the flip level within the temperature range of -55°C to +125°C. It can be applied to complex working environments with anti-interference requirements, such as in controlling the conduction and shutdown of negative voltage logic control switching transistors using GaAs process and GaN process. It can be applied to switches, digitally controlled attenuators, digitally controlled phase shifters, amplitude and phase control multi-function circuits and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of a temperature-compensated level-converting driver circuit according to the present invention;

[0021] Figure 2 A simplified functional block diagram of a temperature-compensated level-shifting driver according to the present invention is shown;

[0022] Figure 3 This is the schematic diagram of the level conversion driver circuit of the existing scheme;

[0023] Figure 4 The temperature characteristic curve of the Schottky diode of the present invention;

[0024] Figure 5 A temperature characteristic curve diagram of the gate-drain shorting unit of the enhancement mode transistor of the present invention;

[0025] Figure 6 The comparison of the temperature effect curves of the flip level of the present invention and the traditional solution based on 0.25um GaAs process;

[0026] Figure 7 The figure shows the temperature influence curve comparison between the flip level of the present invention and the flip level of the traditional solution based on 0.15um GaAs process. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0028] See Figure 1-Figure 2 This embodiment provides a temperature-compensated level conversion driver, comprising a logic level positive-to-negative conversion unit and a drive shaping unit. The specific functions and connection relationships of each unit are described as follows:

[0029] The logic level positive-to-negative conversion unit includes two enhancement-mode transistor voltage drop units: a first enhancement-mode transistor voltage drop unit and a second enhancement-mode transistor voltage drop unit; four resistors: resistor RB1, resistor RB2, resistor RB3, and resistor RD1; and two transistors: enhancement-mode transistor E13 and depletion-mode transistor D01. The first enhancement-mode transistor voltage drop unit is a feedback enhancement-mode transistor voltage drop unit composed of five Schottky diodes connected in series with five enhancement-mode transistors. The five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4, and Schottky diode SD5; and the five enhancement-mode transistors are: transistor E01, transistor E02, transistor E03, transistor E04, and transistor E05. The second enhancement-mode transistor voltage drop unit is composed of seven enhancement-mode transistors with their gates and drains shorted together: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11, and transistor E12. Their connections are as follows:

[0030] Resistor RB1 is a current-limiting protection resistor for the input port. One end is connected to the signal input terminal and input signal VCI, and the other end is connected to the positive terminal of Schottky diode SD1 and the drain of transistor E01. The negative terminal of Schottky diode SD1 is connected to the gate of transistor E01. The positive terminal of Schottky diode SD2 is connected to the source of transistor E01 and the drain of transistor E02, and the negative terminal is connected to the gate of transistor E02. The positive terminal of Schottky diode SD3 is connected to the source of transistor E02 and the drain of transistor E03, and the negative terminal is connected to the gate of transistor E03. The positive terminal of Schottky diode SD4 is connected to the source of transistor E03 and the drain of transistor E04, and the negative terminal is connected to the gate of transistor E04. The positive terminal of Schottky diode SD5 is connected to the source of transistor E04 and the drain of transistor E05, and the negative terminal is connected to the gate of transistor E05. The drain and gate of transistor E06 are connected to the source of transistor E05. The drain and gate of transistor E07 are connected to the source of transistor E06. The drain and gate of transistor E08 are connected to the source of transistor E07. The drain and gate of transistor E09 are connected to the source of transistor E08. The drain and gate of transistor E10 are connected to the source of transistor E09. The drain and gate of transistor E11 are connected to the source of transistor E10. The drain and gate of transistor E12 are connected to the source of transistor E11. The source of transistor E12 is connected to the output of the second enhancement-mode transistor voltage drop unit and is connected to one end of the second resistor RB2 and one end of the third resistor RB3. Resistor RB2 is a positive temperature-controlled voltage divider resistor, and its other end is connected to the negative power supply VSS. The other end of resistor RB3 is connected to the gate of transistor E13, providing gate current limiting when transistor E13 is on, thereby reducing VSS power consumption. The source of transistor E13 is connected to the negative power supply VSS, while its drain is connected to one end of resistor RD1 and the gate of transistor D01. This serves as the output of the logic level positive-to-negative conversion unit, outputting the signal VCO. The drain of transistor D01 is grounded; the other end of resistor RD1 is connected to the source of transistor D01. In this embodiment, resistor RD1 limits quiescent current, thereby reducing static power consumption. Transistor D01 and resistor RD1 together serve as the logic load for transistor E13, providing a preliminary inverted signal. Consequently, their combined action forms a single-ended signal VCO, which is transmitted to the driver shaping unit.

[0031] The driving shaping unit includes: a first inverting driving circuit, a second inverting driving circuit, a third inverting driving circuit, and a fourth inverting driving circuit; the input end of the first inverting driving circuit is the input end of the driving shaping unit, which is connected to the output end of the logic level positive-to-negative unit, and the output end is respectively connected to the input ends of the second inverting driving circuit and the third inverting driving circuit; the output end of the second inverting driving circuit outputs a signal VON, and the output end of the third inverting driving circuit is connected to the input end of the fourth inverting driving circuit and then outputs a signal VOP; the signals VON and VOP output complementary logic signals of 0V / -5V. The specific structure and connection relationship are as follows:

[0032] The driving shaping unit has eight transistors: enhancement transistor E14, enhancement transistor E15, enhancement transistor E16, enhancement transistor E17, depletion transistor D02, depletion transistor D03, depletion transistor D04, and depletion transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4, and resistor RD5; where: the gate of transistor E14 is used as the input of the driving shaping unit to connect the signal VCO; the sources of transistors E14, E15, E16, and E17 are all connected to VSS; the drains of transistors D02, D03, D04, and D05 are all grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14 to form the first inverting driving circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15 to form the second inverting driving circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16 to form the third inverting driving circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17 to form the fourth inverting driving circuit; the gates of the enhancement transistors in each inverting driving circuit are all used as input ends, and the drains are all used as output ends. In this embodiment, the negative power supply VSS is a power supply of -5V.

[0033] When an input control signal VH (such as a signal higher than the inversion level Vs, such as +5V, +3.3V, etc.) is input, VOP outputs a 0V high level and VON outputs a -5V low level; when an input control signal VL (such as 0V, etc., a signal lower than the inversion level Vs) is input, VOP outputs a -5V low level and VON outputs a 0V high level. Transistor E13 is an enhancement transistor, and its on and off states are determined by the threshold voltage Vth and the gate-source voltage Vgs. Among them, the threshold voltage Vth is positive and fluctuates with temperature. When the gate-source voltage Vgs > Vth, transistor E13 is turned on, at this time VOP outputs 0V and VON outputs -5V; conversely, when Vgs < Vth, transistor E13 is turned off, at this time VOP outputs -5V and VON outputs 0V.

[0034] For a more intuitive description Figure 1 In the embodiment of the temperature compensated level shifter, Figure 2 A simplified block diagram of a temperature compensated level shifter driver is given. Figure 1 The five series-connected enhancement-mode transistor voltage drop units based on Schottky diode feedback are replaced with a "P series" structure. The seven series-connected enhancement-mode transistor gate-drain shorting voltage drop units are replaced with an "M series" structure. The inverting unit circuit within the driver shaping unit is directly replaced with four "inverting drive circuits." Due to differences in semiconductor processes, the on-state voltage and current curves of the first and second enhancement-mode transistor voltage drop units vary. During implementation, the values of P and M can be flexibly adjusted based on process parameters to achieve temperature compensation.

[0035] Figure 3 This is a typical schematic diagram of a conventional level-shifting driver circuit. Its structure is disclosed in Chinese patents CN110247651B, CN111682866B, CN104682967B, and CN119171903A. Unlike the temperature-compensated level-shifting driver of this embodiment, this structure uses N Schottky diodes and a resistor for voltage division. During the level-shifting process, the flip level of this structure fluctuates significantly due to temperature.

[0036] Figure 4 The temperature characteristic curve of Schottky diode is given. The three curves in the figure represent the relationship between current and voltage under different conditions of high temperature HT, normal temperature MT and low temperature LT. Figure 4 It can be seen that the higher the temperature, the lower the on-state voltage.

[0037] Figure 5 The temperature characteristic curve of the gate-drain short circuit unit of the enhancement mode transistor is given. The three curves in the figure represent the relationship between current and voltage under different conditions of high temperature HT, room temperature MT and low temperature LT. Figure 5 It can be seen that the higher the temperature, the lower the on-state voltage, but the curvature of the current changing with voltage is the same as Figure 4 Schottky diode temperature characteristics have obvious differences.

[0038] Combine Figure 4 and Figure 5 The enhancement-mode transistor voltage drop unit based on Schottky diode feedback will form a temperature feedback characteristic. This structure, combined with the enhancement-mode transistor gate-drain short-circuit voltage drop unit and the positive temperature coefficient resistor, forms a complex temperature compensation effect.

[0039] In order to verify the practicality of the present invention, a 0.25um GaAs process model was used for verification. Figure 6 The flip level of the present invention is Figure 3 The comparison of the curve of the traditional solution flip level affected by temperature is shown in the figure. Figure 6 The existing solution in Figure 3 The traditional resistor and Schottky diode voltage divider structure shown. Figure 6 It can be seen that compared to the existing solution, after introducing the first enhancement-mode transistor voltage drop unit, the second enhancement-mode transistor voltage drop unit, and the positive temperature coefficient voltage divider resistors RB1 and RB2, this embodiment has an input low-level range VL of 0 to 1.5V and a high-level range VH of 2.3 to 5.0V. Under the same conditions, the input low-level range VL of the existing solution is 0 to 0.5V, and the high-level range VH is 3.0 to 5.0V. In comparison, the flip level Vs of the temperature-compensated level shifter driver of this embodiment is less affected by temperature fluctuations, has greater compatibility with TTL mode (+5V / 0V) and LVTTL mode (+3.3V / 0V), and has the advantage of greater stability in applications with strong interference signals.

[0040] In order to further verify the process adaptability of the present invention, the principle simulation verification was carried out again using a 0.15um GaAs process model. Figure 7 The flip level of the present invention is Figure 3 The comparison of the curve of the traditional solution flip level affected by temperature is shown in the figure. Figure 7 The existing solution in Figure 3 The traditional resistor and Schottky diode voltage divider structure shown. Figure 7 It can be seen that compared to the existing solution, after introducing the first enhancement-mode transistor voltage drop unit, the second enhancement-mode transistor voltage drop unit, and the positive temperature coefficient voltage divider resistors RB1 and RB2, this embodiment has an input low-level range VL of 0 to 1.7V and a high-level range VH of 2.0 to 5.0V. Under the same conditions, the input low-level range VL of the existing solution is 0 to 1.1V, and the high-level range VH is 2.8 to 5.0V. When compared under the same conditions, the flip level Vs of the temperature-compensated level shifter driver of this embodiment still fluctuates less due to temperature, indicating that the circuit structure of the present invention can achieve temperature compensation under different process parameter values.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims.

Claims

1. A temperature-compensated level-shifting driver for converting an input positive logic level (+5V / 0V) or +3.3V / 0V) into a negative logic level signal (0V / -5V), comprising: The logic level positive-to-negative conversion unit and the drive shaping unit connected thereto are characterized by: The logic level positive-to-negative conversion unit includes: two enhancement-mode transistor voltage drop units: a first enhancement-mode transistor voltage drop unit and a second enhancement-mode transistor voltage drop unit; four resistors: a resistor RB1, a resistor RB2, a resistor RB3, and a resistor RD1; two transistors: an enhancement-mode transistor E13 and a depletion-mode transistor D01; wherein: One end of resistor RB1 is a signal input terminal connected to an input signal VCI, and the other end is connected to the input of a first enhancement-mode transistor voltage drop unit. The first enhancement-mode transistor voltage drop unit is a feedback enhancement-mode transistor voltage drop unit composed of P Schottky diodes and P transistors connected in series, and its output end is connected to the input end of a second enhancement-mode transistor voltage drop unit. The second enhancement-mode transistor voltage drop unit is an enhancement-mode transistor voltage drop unit composed of M enhancement-mode transistors with their gates and drains short-circuited in series, and its output end is respectively connected to one end of resistor RB2 and one end of resistor RB3. The other end of resistor RB2 is connected to a negative power supply VSS, and the other end of resistor RB3 is connected to the gate of transistor E13. The source of transistor E13 is connected to the negative power supply VSS, and the drain is connected to one end of resistor RD1 and the gate of transistor D01, and serves as the output end of a logic level positive-to-negative conversion unit to output a signal VCO. The drain of transistor D01 is grounded. The other end of resistor RD1 is connected to the source of transistor D01. The drive shaping unit includes: a first inverting drive circuit, a second inverting drive circuit, a third inverting drive circuit and a fourth inverting drive circuit; the input end of the first inverting drive circuit is the input end of the drive shaping unit, which is connected to the output end of the logic level positive-to-negative conversion unit, and the output end is respectively connected to the input end of the second inverting drive circuit and the input end of the third inverting drive circuit; the output end of the second inverting drive circuit outputs a signal VON, and the output end of the third inverting drive circuit is connected to the input end of the fourth inverting drive circuit and then outputs a signal VOP; the signals VON and VOP output are complementary logic signals of 0V / -5V.

2. The temperature-compensated level-shifting driver according to claim 1, wherein: The first enhancement-mode transistor voltage drop unit is a feedback enhancement-mode transistor voltage drop unit composed of five Schottky diodes and five enhancement-mode transistors connected in series, the five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4 and Schottky diode SD5; the five enhancement-mode transistors are: transistor E01, transistor E02, transistor E03, transistor E04 and transistor E05; wherein: The positive end of Schottky diode SD1 is connected to resistor RB1 and the drain of transistor E01, and the negative end is connected to the gate of transistor E01; the positive end of Schottky diode SD2 is connected to the source of transistor E01 and the drain of transistor E02, and the negative end is connected to the gate of transistor E02; the positive end of Schottky diode SD3 is connected to the source of transistor E02 and the drain of transistor E03, and the negative end is connected to the gate of transistor E03; the positive end of Schottky diode SD4 is connected to the source of transistor E03 and the drain of transistor E04, and the negative end is connected to the gate of transistor E04; the positive end of Schottky diode SD5 is connected to the source of transistor E04 and the drain of transistor E05, and the negative end is connected to the gate of transistor E05; The second enhancement mode transistor voltage drop unit is composed of seven enhancement mode transistors with gates and drains shorted, the seven enhancement mode transistors being: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11 and transistor E12; wherein: The drain and gate of transistor E06 are connected to the source of transistor E05, the drain and gate of transistor E07 are connected to the source of transistor E06, and the drain and gate of transistor E08 are connected to the source of transistor E07; the drain and gate of transistor E09 are connected to the source of transistor E08, the drain and gate of transistor E10 are connected to the source of transistor E09, and the drain and gate of transistor E11 are connected to the source of transistor E10; the drain and gate of transistor E12 are connected to the source of transistor E11, and the source is the common point of the output of the second enhancement-mode transistor voltage drop unit connected to the second resistor RB2 and the third resistor RB3.

3. The temperature-compensated level-shifting driver according to claim 2, wherein: The drive shaping unit specifically includes: eight transistors: enhancement mode transistor E14, enhancement mode transistor E15, enhancement mode transistor E16, enhancement mode transistor E17, depletion mode transistor D02, depletion mode transistor D03, depletion mode transistor D04 and depletion mode transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4 and resistor RD5; wherein: the gate of transistor E14 is connected to the signal VCO as the input of the drive shaping unit; the sources of transistors E14, transistors E15, transistors E16 and transistors E17 are all connected to VSS; transistors D02, transistors D03, transistors D04 and transistors D The drains of transistors 05 are both grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14, forming a first inverting drive circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15, forming a second inverting drive circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16, forming a third inverting drive circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17, forming a fourth inverting drive circuit; the gates of the enhancement transistors in each inverting drive circuit serve as input terminals, and the drains serve as output terminals.

4. The temperature-compensated level-shifting driver according to claim 3, wherein: The five Schottky diodes have the same size; the transistors E01, E02, E03, E04, E05, E06, E07, E08, E09, E10, E11, E12 and E13 have the same size.

5. The temperature-compensated level-shifting driver according to claim 3, wherein: The resistor RB1 , the resistor RB2 , the resistor RB3 , the resistor RD1 , the resistor RD2 , the resistor RD3 , the resistor RD4 , and the resistor RD5 are all positive temperature coefficient resistors with a sheet resistance greater than 400 ohms.

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