High-bandwidth linear differential buffer and electronic device
By setting the adjustment capacitor at the output end of the differential module of the buffer, the contradiction between buffer linearity and bandwidth is solved, and a buffer design with high bandwidth and low power consumption is realized.
Patent Information
- Application Number
- CN202510383071.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-18
Smart Images
Figure CN120342381A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic device design, and particularly to a high-bandwidth linear differential buffer and an electronic device. Background Art
[0002] A buffer is an electronic circuit or device mainly used to enhance the driving ability of a signal, isolate circuits, prevent signal distortion, and match impedances; it is widely used in digital circuits, analog circuits, and communication systems. For example, when the buffer is used as an input buffer, as a driver that isolates the input drive outside the chip and the core circuit inside the chip, it has a small output impedance and a large input impedance, and the amplification factor is approximately 1. The small input impedance gives the buffer a strong driving ability, and the large output impedance gives the buffer a reasonable bandwidth. The input buffer adopts a source follower, which has a small output impedance, a large input impedance, and an amplification factor of about 1; in the related art, in order to obtain better linearity, a traditional input buffer requires a large current, increasing the power consumption of the input buffer; or, an additional capacitor is added at the output end. Although the additional capacitor reduces the input impedance, at the same time, it also makes the bandwidth smaller.
[0003] Therefore, how to provide a buffer with improved linearity without affecting the input bandwidth and without increasing power consumption is a technical problem that needs to be solved urgently at present. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the present invention provides a technical solution for a new type of differential buffer to solve at least one of the above technical problems.
[0005] To achieve the above and other related objectives, the technical solutions provided in this application are as follows.
[0006] According to the first aspect of the embodiments of the present application, a high-bandwidth linear differential buffer is provided, including:
[0007] A first buffer module and a second buffer module, an input end of the first buffer module and an input end of the second buffer module are cooperatively configured to input a differential input voltage, and the differential input voltage is buffered by the first buffer module and the second buffer module to obtain a differential output voltage. Wherein, a first adjustment capacitor is respectively arranged between an output end of the first buffer module and an analog ground end and between an output end of the second buffer module and the analog ground end, a second adjustment capacitor is arranged between an output end of the first buffer module and a reference current input end of the second buffer module, and the second adjustment capacitor is arranged between an output end of the second buffer module and a reference current input end of the first buffer module. A capacitance value of the first adjustment capacitor is M times a capacitance value of the second adjustment capacitor to improve an input bandwidth and linearity of a differential buffer, M≥2, and M is an integer.
[0008] In an embodiment of the present invention, both the first buffer module and the second buffer module include a buffer unit and a tail current generation unit. The tail current generation unit provides a tail current. The buffer unit receives a bias voltage, the differential input voltage, and the tail current generation unit, and buffers the differential input voltage based on the bias voltage and the tail current to obtain the differential output voltage.
[0009] In an embodiment of the present invention, the buffer unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, and a first capacitor. A drain of the first NMOS transistor is connected to a power supply voltage. A first end of the first resistor is connected to a gate of the first NMOS transistor, and the first end of the first resistor is further connected to a first end of the first capacitor. A source of the first NMOS transistor is connected to a drain of the second NMOS transistor. A second end of the first capacitor is connected to a gate of the second NMOS transistor. Wherein, a second end of the first resistor is connected to the bias voltage, a gate of the second NMOS transistor is an input end of the buffer unit, and a source of the second NMOS transistor is an output end of the buffer unit.
[0010] In an embodiment of the present invention, the tail current generation unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and an operational amplifier. A source of the third NMOS transistor is connected to an input end of the operational amplifier. An output end of the operational amplifier is connected to a gate of the third NMOS transistor. The source of the third NMOS transistor is further connected to a drain of the fourth NMOS transistor. A source of the fourth NMOS transistor is grounded. A gate of the fourth NMOS transistor is connected to a gate of the fifth NMOS transistor. A source of the fifth NMOS transistor is grounded. A drain of the fifth NMOS transistor is connected to a gate of the fifth NMOS transistor. Wherein, a drain of the third NMOS transistor is connected to an output end of the buffer unit, and a drain of the fifth NMOS transistor is connected to the reference current.
[0011] In an embodiment of the present invention, the size of the fifth NMOS transistor is (M + 1) times the size of the fourth NMOS transistor.
[0012] In an embodiment of the present invention, the operational gain of the operational amplifier is negative.
[0013] According to the second aspect of the embodiments of the present application, there is provided an electronic device, which includes the high-bandwidth linear differential buffer described above.
[0014] The present application provides a high-bandwidth linear differential buffer and an electronic device. The differential buffer includes a first buffer module and a second buffer module. First adjustment capacitors are respectively arranged between the first buffer module and the analog ground terminal, and between the second buffer module and the analog ground terminal. Second adjustment capacitors are also arranged between the output terminal of the first buffer module and the reference current input terminal of the second buffer module, and between the output terminal of the second buffer module and the reference current input terminal of the second buffer module. The current in the differential buffer is adjusted by the first adjustment capacitors and the second adjustment capacitors to improve the input bandwidth and linearity of the differential buffer. By respectively arranging adjustment capacitors between the output terminals of the two differential modules of the differential buffer and the module ground terminal, and between the output terminals of the two differential modules and the reference current input terminal of the other differential module, the present application not only improves the linearity of the buffer, but also does not affect the input bandwidth of the buffer, and at the same time ensures low power consumption of the buffer.
[0015] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:
[0017] Figure 1 is the specific structural diagram of a traditional input buffer in the prior art;
[0018] Figure 2 is the specific structural diagram of an input buffer with a replication capacitor added at the input end in the prior art;
[0019] Figure 3 is the block diagram of the high-bandwidth linear differential buffer shown in an exemplary embodiment of the present invention;
[0020] Figure 4It is the specific structural diagram of the high-bandwidth linear differential buffer shown in an exemplary embodiment of the present invention;
[0021] Figure 5 It is the specific structural diagram of the high-bandwidth linear differential buffer including the current direction shown in an exemplary embodiment of the present invention. Detailed implementation manners
[0022] The following will describe the implementation manners of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, rather than for limiting the protection scope of the present invention.
[0023] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, number, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0024] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.
[0025] A buffer is an electronic circuit or device mainly used to enhance the driving ability of a signal, isolate circuits, prevent signal distortion, and match impedances. It has wide applications in digital circuits, analog circuits, and communication systems. For example: when the buffer is used as an input buffer, as a driver that isolates the input drive outside the chip and the core circuit inside the chip, it has a small output impedance and a large input impedance, and the amplification factor is approximately 1. The small input impedance enables the buffer to have a strong driving ability, and the large output impedance enables the buffer to have a reasonable bandwidth.
[0026] The input buffer adopts a source follower, which has a small output impedance, a large input impedance, and an amplification factor of about 1; in the related art, such as Figure 1As shown, the output terminal of the buffer outputs current \(i_{Cs}\) to the load capacitor \(C_s\). Since the bias current \(i_b\) generated by the tail current source remains unchanged, the current flowing through the source follower \(M_0\) becomes \(i_b - i_{Cs}\). \(i_{Cs}\) changes with the change rate and direction of the input signal \(V_{in}\). Therefore, to ensure the linearity of the source follower \(M_0\), it is necessary to satisfy: So that the influence of the change of \(i_{Cs}\) on the source follower \(M_0\) can be ignored, but this design increases the power consumption of the circuit.
[0027] As Figure 2 shown, to obtain better linearity, a replica capacitor \(C_c\) is set between the input terminal \(V_{in}\) of the buffer and the input terminal of the cascode point \(V_1\), where \(C_c = C_s\). Since the amplification factor of the buffer is approximately equal to 1, \(V_{in}\approx V_o\). In addition, the cascode point is a low-impedance node, so \(i_{Cs}\approx i_{Cc}\). This structure makes the current of the source follower \(M_0\) remain \(i_b\) unchanged. Therefore, the input buffer can provide high linearity when \(i_b\) is small. This structure adds a replica capacitor \(C_c\) at the input terminal of the buffer, making the input impedance smaller, but at the same time reducing the bandwidth of the input buffer.
[0028] To solve the above problems, as Figure 3 shown, the present application provides a high-bandwidth linear differential buffer, including:
[0029] A first buffer module and a second buffer module. The input terminals of the first buffer module and the second buffer module cooperate to input a differential input voltage \((V_{inp}-V_{inn})\). The differential input voltage \((V_{inp}-V_{inn})\) is buffered by the first buffer module and the second buffer module to obtain a differential output voltage \((V_{op}-V_{on})\). Among them, first adjustment capacitors \((C_{s1}, C_{s2})\) are respectively set between the output terminal of the first buffer module and the analog ground terminal and between the output terminal of the second buffer module and the analog ground terminal. A second adjustment capacitor \((C_{c_n})\) is set between the output terminal of the first buffer module and the reference current \(I_0\) input terminal of the second buffer module. A second adjustment capacitor \((C_{c_p})\) is set between the output terminal of the second buffer module and the reference current \(I_0\) input terminal of the first buffer module. The capacitance values \((C_{s1}, C_{s2})\) of the first adjustment capacitors are \(M\) times the capacitance values \((C_{c_n}, C_{c_p})\) of the second adjustment capacitors to improve the input bandwidth and linearity of the differential buffer, where \(M\geq2\) and \(M\) is an integer.
[0030] Specifically, both the first buffer module and the second buffer module include a buffer unit and a tail current generation unit. The tail current generation unit provides a tail current. The buffer unit is connected to a bias voltage Vb1, a differential input voltage (Vinp - Vinn), and the tail current generation unit, and buffers the differential input voltage (Vinp - Vinn) based on the bias voltage Vb1 and the tail current to obtain a differential output voltage (Vop - Von).
[0031] More specifically, as Figure 4 shown, the buffer unit in the first buffer module includes a first NMOS transistor M11, a second NMOS transistor M12, a first resistor R11, and a first capacitor C11. The drain of the first NMOS transistor M11 is connected to the power supply voltage VCC. The first end of the first resistor R11 is connected to the gate of the first NMOS transistor M11, and the first end of the first resistor R11 is also connected to the first end of the first capacitor C11. The source of the first NMOS transistor M11 is connected to the drain of the second NMOS transistor M12. The second end of the first capacitor C11 is connected to the gate of the second NMOS transistor M12. Among them, the second end of the first resistor R11 is connected to the bias voltage Vb1. The gate of the second NMOS transistor M12 is the input end of the buffer unit in the first buffer module. The input end of the buffer unit in the first buffer module is connected to one end Vinp of the differential input voltage. The source of the second NMOS transistor M12 is the output end of the buffer unit in the first buffer module. The output end of the buffer unit in the first buffer module outputs one end Vop of the differential output voltage to the outside.
[0032] More specifically, as Figure 4 shown, the tail current generation unit in the first buffer module includes a third NMOS transistor M13, a fourth NMOS transistor M14, a fifth NMOS transistor M15, and an operational amplifier AMP1. The source of the third NMOS transistor M13 is connected to the input end of the operational amplifier AMP1. The output end of the operational amplifier AMP1 is connected to the gate of the third NMOS transistor M13. The source of the third NMOS transistor M13 is also connected to the drain of the fourth NMOS transistor M14. The source of the fourth NMOS transistor M14 is grounded. The gate of the fourth NMOS transistor M14 is connected to the gate of the fifth NMOS transistor M15. The source of the fifth NMOS transistor M15 is grounded. The drain of the fifth NMOS transistor M15 is connected to the gate of the fifth NMOS transistor M15. Among them, the drain of the third NMOS transistor M13 is connected to the output end of the buffer unit in the first buffer module. The drain of the third NMOS transistor M13 is connected to the source of the second NMOS transistor M12. The drain of the fifth NMOS transistor M15 is connected to the reference current I0.
[0033] More specifically, as Figure 4As shown, the buffer unit in the second buffer module includes a first NMOS transistor M21, a second NMOS transistor M22, a first resistor R21, and a first capacitor C21. The drain of the first NMOS transistor M21 is connected to the power supply voltage VCC. The first end of the first resistor R21 is connected to the gate of the first NMOS transistor M21 and also to the first end of the first capacitor C21. The source of the first NMOS transistor M21 is connected to the drain of the second NMOS transistor M22. The second end of the first capacitor C21 is connected to the gate of the second NMOS transistor M22. Among them, the second end of the first resistor R21 is connected to the bias voltage Vb1. The gate of the second NMOS transistor M22 is the input end of the buffer unit in the second buffer module. The input end of the buffer unit in the second buffer module is connected to the other end Vinn of the differential input voltage. The source of the second NMOS transistor M22 is the output end of the buffer unit in the second buffer module. The output end of the buffer unit in the second buffer module outputs the other end Von of the differential output voltage.
[0034] More specifically, as Figure 4 shown, the tail current generation unit in the second buffer module includes a third NMOS transistor M23, a fourth NMOS transistor M24, a fifth NMOS transistor M25, and an operational amplifier AMP2. The source of the third NMOS transistor M23 is connected to the input end of the operational amplifier AMP2. The output end of the operational amplifier AMP2 is connected to the gate of the third NMOS transistor M23. The source of the third NMOS transistor M23 is also connected to the drain of the fourth NMOS transistor M24. The source of the fourth NMOS transistor M24 is grounded. The gate of the fourth NMOS transistor M24 is connected to the gate of the fifth NMOS transistor M25. The source of the fifth NMOS transistor M25 is grounded. The drain of the fifth NMOS transistor M25 is connected to the gate of the fifth NMOS transistor M25. Among them, the drain of the third NMOS transistor M23 is connected to the output end of the buffer unit in the second buffer module. The drain of the third NMOS transistor M23 is connected to the source of the second NMOS transistor M22. The drain of the fifth NMOS transistor M25 is connected to the reference current I0.
[0035] It should be noted that, as Figure 4 shown, the second adjustment capacitor Cc_n is disposed between the output end of the first buffer module and the input end of the reference current of the second buffer module, that is, the second adjustment capacitor Cc_n is disposed between the source of the second NMOS transistor M12 and the drain of the fifth NMOS transistor M25; the second adjustment capacitor Cc_p is disposed between the output end of the second buffer module and the input end of the reference current of the second buffer module, that is, the second adjustment capacitor Cc_p is disposed between the source of the second NMOS transistor M22 and the drain of the fifth NMOS transistor M15.
[0036] Specifically, the size of the fifth NMOS transistor is (M + 1) times the size of the fourth NMOS transistor. Specifically, the ratio of the sizes (M15, M25) of the fifth NMOS transistor to the sizes (M14, M24) of the fourth NMOS transistor is 1:(M + 1).
[0037] Specifically, the operational gain of the operational amplifier AMP2 is negative. Specifically, the third NMOS transistor is strengthened by the operational amplifiers (AMP1, AMP2) to achieve gain bootstrapping, and the gain multiple of the operational amplifier is -A.
[0038] Please refer to Figures 3 to 5 As shown, the working principle of the high-bandwidth linear differential buffer provided by this application is as follows:
[0039] As Figures 3 to 5 As shown, a first adjustment capacitor Cs1 is provided between the output terminal of the first differential module and the analog ground terminal, and a first adjustment capacitor Cs2 is provided between the output terminal of the second differential module and the analog ground terminal. The differential buffer is provided with a second adjustment capacitor Cc_n between the output terminal of the first buffer module and the input terminal of the reference current I0 of the second buffer module, and a second adjustment capacitor Cc_p is provided between the output terminal of the second buffer module and the input terminal of the reference current I0 of the first buffer module.
[0040] The first potential Vop output by the first buffer module is equal in magnitude and opposite in direction to the second potential Von output by the second buffer. The capacitance values of the second adjustment capacitors (Cc_n, Cc_p) are 1 / M of the first adjustment capacitors (Cs1, Cs2); the gate and drain of the fifth PMOS transistor M15 are connected. As Figure 5 As shown, the current shunted away by the first adjustment capacitor Cs1 at the source of the second NMOS transistor M12 is iCs. Since the potential Vb_N in the second buffer module is a low-resistance contact point, the current shunted by the second adjustment capacitor Cc_n at the output terminal of the first buffer module is iCc_n; it can be seen that the total current shunted by the first adjustment capacitor Cs1 and the second adjustment capacitor Cc_n at the output terminal of the first buffer module is iCs + iCc_p = (1 + 1 / M)*iCs, and the current flowing through the second NMOS transistor M12 is ib1 - (1 + 1 / M)*iCs. Because the current shunted by the second adjustment capacitor Cc_p at the potential Vb_p of the first buffer module is iCc_p, and the ratio of the size of the fifth NMOS transistor M15 to the size of the fourth NMOS transistor M14 is 1:(M + 1), the tail power supply flowing through the fourth NMOS transistor M14 is ib1 - (1 + 1 / M)*iCs, so that the current of the second NMOS transistor M12 remains unchanged.
[0041] As Figure 5As shown, the current flowing into the source of the second NMOS transistor M22 through the first adjustment capacitor Cs2 is iCs, and the current flowing into the output terminal of the second buffer module through the second adjustment capacitor Cc_p is iCc_p. Thus, it can be known that the total current input to the output terminal of the second buffer module through the first adjustment capacitor Cs2 and the second adjustment capacitor Cc_p is iCs + iCc_p = (1 + 1 / M) * iCs, and the current flowing through the second NMOS transistor M22 is ib2 + (1 + 1 / M) * iCs. Because the current increasing the potential Vb_p of the second buffer module through the second adjustment capacitor Cc_n is iCc_n, and the ratio of the size of the fifth NMOS transistor M25 to the size of the fourth NMOS transistor M24 is 1:(M + 1), the tail current flowing through the fourth NMOS transistor M24 is ib2 + (1 + 1 / M) * iCs, making the current of the second NMOS transistor M22 remain unchanged, where ib1 = ib2, and both are the tail currents generated by the reference current I0.
[0042] Since no additional capacitor is added to the input terminal of the differential buffer, the added adjustment capacitor does not affect the input bandwidth of the buffer, and the currents flowing through the second NMOS transistors (M12, M22) are balanced by the differential structure, without increasing the power consumption of the buffer, and also improving the linearity of the input buffer.
[0043] For example, when M = 8, the current flowing through the second NMOS transistor M12 is ib1 - (1 + 1 / 8) * iCs, and the current flowing through the second NMOS transistor M22 is ib1 + (1 + 1 / 8) * iCs.
[0044] It should be noted that the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor provided in this application can all be replaced by NPN-type triodes.
[0045] In another aspect of this application, this application also provides an electronic device, which includes the high-bandwidth linear differential buffer described above to enhance the working performance of the electronic device.
[0046] The present application provides a high-bandwidth linear differential buffer and an electronic device. The differential buffer includes a first buffer module and a second buffer module. A first adjustment capacitor is respectively provided between the first buffer module and the analog ground terminal, and between the second buffer module and the analog ground terminal. Second adjustment capacitors are also provided between the output terminal of the first buffer module and the reference current input terminal of the second buffer module, and between the output terminal of the second buffer module and the reference current input terminal of the second buffer module. The current in the differential buffer is adjusted by the first adjustment capacitor and the second adjustment capacitor to improve the input bandwidth and linearity of the differential buffer. By respectively providing adjustment capacitors between the output terminals of the two differential modules of the differential buffer and the module ground terminal, and between the output terminals of the two differential modules and the reference current input terminal of another differential module, the linearity of the input buffer is improved without affecting the input bandwidth and without increasing power consumption, thereby enhancing the market competitiveness and having great economic benefits.
[0047] The above embodiments are only used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can make modifications or changes to the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A high-bandwidth linear differential buffer, characterized in that, It includes a first buffer module and a second buffer module. The input ends of the first buffer module and the second buffer module cooperate to input a differential input voltage. The differential input voltage is buffered by the first buffer module and the second buffer module to obtain a differential output voltage. Among them, a first adjustment capacitor is respectively provided between the output end of the first buffer module and the analog ground terminal and between the output end of the second buffer module and the analog ground terminal, and a second adjustment capacitor is provided between the output end of the first buffer module and the reference current input end of the second buffer module, and the second adjustment capacitor is provided between the output end of the second buffer module and the reference current input end of the first buffer module. The capacitance value of the first adjustment capacitor is M times the capacitance value of the second adjustment capacitor to improve the input bandwidth and linearity of the differential buffer, where M≥2 and M is an integer.
2. The high-bandwidth linear differential buffer according to claim 1, wherein Both the first buffer module and the second buffer module include a buffer unit and a tail current generation unit. The tail current generation unit provides a tail current. The buffer unit receives a bias voltage, the differential input voltage, and the tail current generation unit, and buffers the differential input voltage based on the bias voltage and the tail current to obtain the differential output voltage.
3. The high-bandwidth linear differential buffer according to claim 2, characterized in that The buffer unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, and a first capacitor. The drain of the first NMOS transistor is connected to the power supply voltage. The first end of the first resistor is connected to the gate of the first NMOS transistor, and the first end of the first resistor is also connected to the first end of the first capacitor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The second end of the first capacitor is connected to the gate of the second NMOS transistor. Among them, the second end of the first resistor is connected to the bias voltage. The gate of the second NMOS transistor is the input end of the buffer unit, and the source of the second NMOS transistor is the output end of the buffer unit.
4. The high-bandwidth linear differential buffer according to claim 2, wherein The tail current generation unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and an operational amplifier. The source of the third NMOS transistor is connected to the input end of the operational amplifier. The output end of the operational amplifier is connected to the gate of the third NMOS transistor. The source of the third NMOS transistor is also connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded. The drain of the fifth NMOS transistor is connected to the gate of the fifth NMOS transistor. Among them, the drain of the third NMOS transistor is connected to the output end of the buffer unit, and the drain of the fifth NMOS transistor is connected to the reference current.
5. The high-bandwidth linear differential buffer according to claim 4, wherein The size of the fifth NMOS transistor is (M + 1) times the size of the fourth NMOS transistor.
6. The high-bandwidth linear differential buffer according to claim 4, wherein The operational gain of the operational amplifier is negative.
7. An electronic device, characterized in that, The electronic device includes the high-bandwidth linear differential buffer as described in any one of claims 1-6.