Under-voltage locking circuit structure with dual-mode redundancy hysteretic characteristic

Abstract

The invention discloses an under-voltage locking circuit structure with dual-mode redundancy hysteretic characteristics, which comprises a voltage reference module I1, ensures that a circuit can still provide stable reference voltage in a low-voltage environment, and effectively improves the anti-interference capability and the stability of the circuit. And meanwhile, the reference comparison module I2 adopts a reverse Schmidt unit and a plurality of phase inverters, so that a hysteresis comparison function is realized, and misoperation caused by voltage fluctuation is avoided. The level detection reset module I3 realizes accurate detection and rapid reset of the input voltage through combination of multiple groups of PMOS and NMOS transistors and ingenious configuration of capacitors and resistors, and further improves the response speed and stability of the circuit. According to the digital isolator, the performance of the digital isolator is improved, the risk of misoperation is reduced, a powerful guarantee is provided for stable operation of a system, and the digital isolator is suitable for various electronic devices requiring high precision and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and relates to an under-voltage lock-out circuit structure with dual-mode redundant hysteresis characteristics. Background Art

[0002] As a key circuit component, digital isolators are widely used in various electronic systems, especially in applications that require high isolation, low noise, and strong anti-interference capabilities, such as industrial control, automotive electronics, communication systems, and medical equipment. Its core function is to achieve isolated transmission of signals through non-conductive media (such as light, magnetic fields, or capacitors), effectively preventing adverse factors such as ground potential differences, noise, and surge voltages from interfering with the circuit system, thereby protecting sensitive circuits and enhancing the stability and reliability of the entire system.

[0003] The under-voltage lock-out (UVLO) mechanism is one of the common protection functions in digital isolators and other integrated circuits. Its role is to monitor the power supply voltage level. Once the power supply voltage drops below a preset threshold, the UVLO module will quickly take measures, such as shielding the output signal or putting the chip into a low-power / reset state, to prevent circuit instability or damage caused by insufficient power supply voltage. This mechanism is crucial for protecting the circuit from transient voltage drops or long-term low-voltage operation, and helps to improve the overall reliability and safety of the system.

[0004] However, traditional under-voltage lock-out circuits have some inherent challenges in design. First, the voltage change rate during power-on and power-off processes may be relatively fast, which may cause transient glitches or instability in modules such as voltage comparators and delay circuits inside the UVLO circuit, thereby mis-triggering the under-voltage lock-out signal and causing logic errors or unnecessary reset operations in the subsequent circuit. Second, the response speed of traditional UVLO circuits may not be fast enough to respond to rapidly changing power supply voltages, especially in application environments with frequent power fluctuations. This may lead to the circuit operating in an unstable state for too long. How to improve the stability of the circuit and ensure the accurate execution of the UVLO function is one of the challenges faced by designers. Summary of the Invention

[0005] The purpose of the present invention is to solve the technical problem in the prior art that traditional UVLO circuits have a slow response speed, resulting in the circuit operating in an unstable state for a long time, and to provide an under-voltage lock-out circuit structure with dual-mode redundant hysteresis characteristics.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: In a first aspect, the present invention discloses an undervoltage lock - out circuit structure with dual - mode redundant hysteresis characteristics, including: a first PMOS transistor P1, a first resistor R1, a second resistor R2, a third resistor R3, a voltage reference circuit I1, a reference comparison circuit I2, a level detection and reset module I3, and an AND gate AND1; The source of the first PMOS transistor P1 is connected to the power supply VCC. The gate of the first PMOS transistor P1 is connected to one end of the second resistor R2. The drain of the first PMOS transistor P1 is connected to one end of the third resistor R3. One end of the first resistor R1 is respectively connected to the other end of the third resistor R3 and the positive - terminal input of the reference comparison circuit I2. The other end of the second resistor R2 is respectively connected to the other end of the first resistor R1 and the ground. The output of the voltage reference circuit I1 is connected to the negative - terminal input of the reference comparison circuit I2. One of the power - supply terminals of the reference comparison circuit I2 is grounded, and the other is connected to the power supply VCC. The output of the reference comparison circuit I2 is connected to one input of the AND gate AND1, and the output of the threshold reset module I3 is connected to the other input of the AND gate AND1. The output of the AND gate is the output undervoltage lock - out signal V of the undervoltage lock - out circuit UVLO .

[0007] A further improvement lies in: The voltage reference circuit I1 includes a current - mirror self - start circuit, a classic PTAT current - source circuit, and an output circuit. The current - mirror self - start circuit sends a start command to the classic PTAT current - source circuit. The current provided by the classic PTAT current - source circuit generates a PTAT voltage reference Vref through the output circuit. The PTAT voltage reference Vref is input to the negative - terminal of the reference comparison circuit I2.

[0008] The current - mirror self - start circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth resistor R4; The source of the second PMOS transistor P2 is respectively externally connected to the power supply VCC, one end of the fourth resistor R4, the source of the third PMOS transistor P3, and the classic PTAT current - source circuit. The gate of the second PMOS transistor P2 is externally connected to the classic PTAT current - source circuit. The drain of the second PMOS transistor P2 is respectively connected to the drain of the first NMOS transistor N1, the drain of the second NMOS transistor N2, and the gate of the third PMOS transistor P3. The source of the first NMOS transistor N1 is respectively externally connected to the classic PTAT current - source circuit and the ground. The gate of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to the other end of the fourth resistor R4. The drain of the third PMOS transistor P3 is externally connected to the classic PTAT current - source circuit.

[0009] The classical PTAT current source circuit includes: a first NPN transistor npn1, a second NPN transistor npn2, a fifth resistor R5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first capacitor C1; The source of the fourth PMOS transistor P4 is respectively connected to the source of the second PMOS transistor P2, one end of the first capacitor C1, the source of the fifth PMOS transistor P5, and the output circuit; the gate of the fourth PMOS transistor P4 is respectively connected to the gate of the fifth PMOS transistor P5, the other end of the first capacitor C1, the gate of the second PMOS transistor P2, the collector of the second NPN transistor npn2, and the output circuit; the drain of the fourth PMOS transistor P4 is respectively connected to the drain of the third PMOS transistor P3, the collector of the first NPN transistor npn1, and the base of the first NPN transistor npn1; the emitter of the first NPN transistor npn1 is connected to the source of the first NMOS transistor N1, one end of the fifth resistor R5, and the output circuit; the base of the first NPN transistor npn1 is connected to the base of the second NPN transistor npn2; the emitter of the second NPN transistor npn2 is connected to the other end of the fifth resistor R5; the collector of the second NPN transistor npn2 is connected to the drain of the fifth PMOS transistor P5.

[0010] The output circuit includes: a sixth PMOS transistor P6, a sixth resistor R6, and a third NPN transistor npn3; The source of the sixth PMOS transistor P6 is connected to the source of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor P6 is connected to one end of the sixth resistor R6 and the output Vref of the voltage reference circuit I1; the collector of the third NPN transistor npn3 is connected to the other end of the sixth resistor R6 and the base of the third NPN transistor NPN; the emitter of the third NPN transistor npn3 is connected to one end of the fifth resistor R5.

[0011] The reference comparison circuit I2 includes: a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; The source of the seventh PMOS transistor P7 is respectively connected to the source of the eighth PMOS transistor P8, the source of the ninth PMOS transistor P9, the source of the eleventh PMOS transistor P11, and the power supply VCC; the gate of the seventh PMOS transistor P7 is respectively connected to the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the gate of the ninth PMOS transistor P9, the drain of the third NMOS transistor N3, and the drain of the tenth PMOS transistor P10; The gate of the third NMOS transistor N3 is the negative terminal input of the reference comparison module I2; the source of the third NMOS transistor N3 is respectively connected to the source of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5; the gate of the fourth NMOS transistor N4 is the positive terminal input of the reference comparison module I2; the drain of the fourth NMOS transistor N4 is respectively connected to the drain of the eighth PMOS transistor P8 and the gate of the eleventh PMOS transistor P11; the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10; the gate of the fifth NMOS transistor N5 is connected to the gate of the sixth NMOS transistor N6; the source of the fifth NMOS transistor N5 is respectively connected to the source of the sixth NMOS transistor N6 and the ground; the drain of the eleventh PMOS transistor P11 is respectively connected to the drain of the sixth NMOS transistor N6 and the input of the delay inverter INV1; the gate of the tenth PMOS transistor P10 is respectively connected to the output of the delay inverter INV1 and the input of the inverter INV2; the output of the inverter INV2 is the output COMP of the reference comparator module I2.

[0012] The level detection and reset module I3 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a second capacitor C2, a third capacitor C3, a seventh resistor R7, and an eighth resistor R8; The source of the twelfth PMOS transistor P12 is connected to the sources of the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, and the power supply VCC respectively; the drain of the twelfth PMOS transistor P12 is connected to the source of the thirteenth PMOS transistor P13; the gate of the twelfth PMOS transistor P12 is connected to the gates of the thirteenth PMOS transistor P13 and one end of the seventh resistor R7 respectively; the other end of the seventh resistor R7 is connected to the ground; the drain of the thirteenth PMOS transistor P13 is connected to the gates of the fourteenth PMOS transistor P14, one end of the second capacitor C2, the drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the twelfth NMOS transistor N12, and the gate of the thirteenth NMOS transistor N13 respectively; the other end of the second capacitor C2 is connected to the sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the twelfth NMOS transistor N12, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, one end of the third capacitor C3, and the ground respectively; the drain of the fifteenth PMOS transistor P15 is connected to the source of the fourteenth PMOS transistor P14; the gate of the fifteenth PMOS transistor P15 is connected to one end of the eighth resistor R8, the gate of the sixteenth PMOS transistor P16, and the gate of the seventeenth PMOS transistor P17 respectively; the other end of the eighth resistor R8 is connected to the ground; the drain of the sixteenth PMOS transistor P16 is connected to the source of the seventeenth PMOS transistor P17; the drain of the fourteenth PMOS transistor P14 is connected to the drains of the eighth NMOS transistor N8, the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 respectively; the source of the tenth NMOS transistor N10 is connected to the drain of the ninth NMOS transistor N9, and the drain of the seventeenth PMOS transistor P17 is connected to the drains of the eleventh NMOS transistor N11, the gate of the tenth NMOS transistor N10, the gate of the twentieth PMOS transistor P20, and the gate of the fourteenth NMOS transistor N14 respectively; the source of the eleventh NMOS transistor N11 is connected to the drain of the twelfth NMOS transistor N12; the drain of the eighteenth PMOS transistor P18 is connected to the drain of the thirteenth NMOS transistor N13 respectively; the gate of the eighteenth PMOS transistor P18 is connected to the gate of the nineteenth PMOS transistor P19; the drain of the nineteenth PMOS transistor P19 is connected to the source of the twentieth PMOS transistor P20; the drain of the twentieth PMOS transistor P20 is connected to the drains of the fourteenth NMOS transistor N14, the other end of the third capacitor C3, and the output OUT of the level detection and reset module I3 respectively.

[0013] The current provided by the classical PTAT current source circuit generates a PTAT voltage reference Vref through the output circuit, specifically as follows:

[0014] Among them, is the voltage between the base and emitter of the third NPN transistor npn3.

[0015] The positive input of the reference comparison circuit I2 is a reference signal reflecting the power-on level of VCC generated by the self-biased voltage division structure of the first resistor R1, the third resistor R3, and the first PMOS transistor P1. The negative input of the reference comparison circuit I2 is the reference voltage Vref; when 0.48VCC > Vref + the comparator outputs a high level, and the power-on locking ends; When the power supply VCC loses power, when the divided voltage ratio signal level of the VCC power-on level is less than the reference level, the comparator outputs a low-level reference locking signal; Obtain The process of is as follows: The width-to-length ratios of the eighth PMOS transistor P8 and the seventh PMOS transistor P7 are 2:1. At this time, the overdrive voltages of the third NMOS transistor N3 and the fourth NMOS transistor N4 are respectively:

[0016]

[0017]

[0018] Among them, represents the gate oxide capacitance per unit area; represents the gate width / gate length; represents the electron mobility; The current Iref flowing through the fifth NMOS transistor N5 is:

[0019]

[0020] Among them, represents the current flowing through P7; represents the current flowing through P8; When the power supply loses power, at this time, the output signal of the first-stage inverter is fed back to the gate of the tenth PMOS transistor P10 to control it to be in the conducting state, and the mirror current of the ninth PMOS transistor P9 is injected into the third NMOS transistor N3. Among them, the width-to-length ratios of the seventh PMOS transistor P7, the ninth PMOS transistor P9, and the eighth PMOS transistor P8 are P7:P9:P8 = 1:1:2. Therefore, there is the following formula:

[0021] Therefore, when 0.48VCC < Vref, the comparator outputs a low-level reference locking signal.

[0022] Compared with the prior art, the present invention has the following beneficial effects: Through the voltage reference module I1, the present invention ensures that the circuit can still provide a stable reference voltage in a low-voltage environment, effectively improving the anti-interference ability and stability of the circuit. At the same time, the reference comparison module I2 adopts a reverse Schmitt unit and multiple inverters to achieve a hysteresis comparison function, avoiding misoperation caused by voltage fluctuations; the level detection and reset module I3 realizes precise detection and fast reset of the input voltage through the combination of multiple groups of PMOS and NMOS transistors and the ingenious configuration of capacitors and resistors, further improving the response speed and stability of the circuit. The present invention not only improves the performance of the digital isolator but also reduces the risk of misoperation, providing a strong guarantee for the stable operation of the system and being applicable to various electronic devices with high-precision and low-power requirements. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Schematic diagram of the undervoltage lockout circuit structure with dual-mode redundant hysteresis characteristics of the present invention; Figure 2 Equivalent circuit diagram of the voltage reference circuit I1; Figure 3 Circuit structure diagram of the reference comparison circuit I2; Figure 4 Schematic diagram of the circuit structure of the level detection and reset module I3. Detailed Embodiments

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0026] Accordingly, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0027] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings: See Figure 1 , the present invention discloses an undervoltage lock - out circuit structure with dual - mode redundant hysteresis characteristics, including: a first PMOS transistor P1, a first resistor R1, a second resistor R2, a third resistor R3, a voltage reference circuit I1, a reference comparison circuit I2, a level detection and reset module I3, and an AND gate AND1; The source of the first PMOS transistor P1 is connected to the power supply VCC. The gate of the first PMOS transistor P1 is connected to one end of the second resistor R2. The drain of the first PMOS transistor P1 is connected to one end of the third resistor R3. One end of the first resistor R1 is respectively connected to the other end of the third resistor R3 and the positive - terminal input of the reference comparison circuit I2. The other end of the second resistor R2 is respectively connected to the other end of the first resistor R1 and the ground. The output of the voltage reference circuit I1 is connected to the negative - terminal input of the reference comparison circuit I2. One of the power - supply terminals of the reference comparison circuit I2 is grounded, and the other is connected to the power supply VCC. The output of the reference comparison circuit I2 is connected to one input of the AND gate AND1, and the output of the threshold reset module I3 is connected to the other input of the AND gate AND1. The output of the AND gate is the output undervoltage lock - out signal V UVLO .

[0029] See Figure 2 , the voltage reference circuit I1 includes a current - mirror self - start circuit, a classic PTAT current - source circuit, and an output circuit. The current - mirror self - start circuit sends a start command to the classic PTAT current - source circuit. The current provided by the classic PTAT current - source circuit generates a PTAT voltage reference Vref through the output circuit. The PTAT voltage reference Vref is input to the negative - terminal of the reference comparison circuit I2.

[0030] The current - mirror self - start circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth resistor R4; The source of the second PMOS transistor P2 is externally connected to the power supply VCC, one end of the fourth resistor R4, the source of the third PMOS transistor P3, and the classical PTAT current source circuit respectively; the gate of the second PMOS transistor P2 is externally connected to the classical PTAT current source circuit; the drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1, the drain of the second NMOS transistor N2, and the gate of the third PMOS transistor P3 respectively; the source of the first NMOS transistor N1 is externally connected to the classical PTAT current source circuit and grounded respectively; the gate of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2; the gate of the second NMOS transistor N2 is connected to the other end of the fourth resistor R4; the drain of the third PMOS transistor P3 is externally connected to the classical PTAT current source circuit.

[0031] The classical PTAT current source circuit includes: the first NPN transistor npn1, the second NPN transistor npn2, the fifth resistor R5, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the first capacitor C1; The source of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2, one end of the first capacitor C1, the source of the fifth PMOS transistor P5, and the output circuit respectively; the gate of the fourth PMOS transistor P4 is connected to the gate of the fifth PMOS transistor P5, the other end of the first capacitor C1, the gate of the second PMOS transistor P2, the collector of the second NPN transistor npn2, and the output circuit respectively; the drain of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3, the collector of the first NPN transistor npn1, and the base of the first NPN transistor npn1 respectively; the emitter of the first NPN transistor npn1 is connected to the source of the first NMOS transistor N1, one end of the fifth resistor R5, and the output circuit; the base of the first NPN transistor npn1 is connected to the base of the second NPN transistor npn2; the emitter of the second NPN transistor npn2 is connected to the other end of the fifth resistor R5; the collector of the second NPN transistor npn2 is connected to the drain of the fifth PMOS transistor P5.

[0032] The output circuit includes: the sixth PMOS transistor P6, the sixth resistor R6, and the third NPN transistor npn3; The source of the sixth PMOS transistor P6 is connected to the source of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor P6 is connected to one end of the sixth resistor R6 and the output Vref of the voltage reference circuit I1; the collector of the third NPN transistor npn3 is connected to the other end of the sixth resistor R6 and the base of the third NPN transistor NPN; the emitter of the third NPN transistor npn3 is connected to one end of the fifth resistor R5.

[0033] See Figure 3, the reference comparison circuit I2 includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; The source of the seventh PMOS transistor P7 is respectively connected to the sources of the eighth PMOS transistor P8, the ninth PMOS transistor P9, the eleventh PMOS transistor P11, and the power supply VCC; the gate of the seventh PMOS transistor P7 is respectively connected to the drain of the seventh PMOS transistor P7, the gates of the eighth PMOS transistor P8, the ninth PMOS transistor P9, the drain of the third NMOS transistor N3, and the drain of the tenth PMOS transistor P10; The gate of the third NMOS transistor N3 is the negative terminal input of the reference comparison module I2; the source of the third NMOS transistor N3 is respectively connected to the sources of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5; the gate of the fourth NMOS transistor N4 is the positive terminal input of the reference comparison module I2; the drain of the fourth NMOS transistor N4 is respectively connected to the drains of the eighth PMOS transistor P8 and the gate of the eleventh PMOS transistor P11; the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10; the gate of the fifth NMOS transistor N5 is connected to the gate of the sixth NMOS transistor N6; the source of the fifth NMOS transistor N5 is respectively connected to the source of the sixth NMOS transistor N6 and the ground; the drain of the eleventh PMOS transistor P11 is respectively connected to the drain of the sixth NMOS transistor N6 and the input of the delay inverter INV1; the gate of the tenth PMOS transistor P10 is respectively connected to the output of the delay inverter INV1 and the input of the inverter INV2; the output of the inverter INV2 is the output COMP of the reference comparator module I2.

[0034] See Figure 4 , the level detection and reset module I3 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a second capacitor C2, a third capacitor C3, a seventh resistor R7, and an eighth resistor R8; The source of the twelfth PMOS transistor P12 is connected to the sources of the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, and the power supply VCC respectively; the drain of the twelfth PMOS transistor P12 is connected to the source of the thirteenth PMOS transistor P13; the gate of the twelfth PMOS transistor P12 is connected to the gates of the thirteenth PMOS transistor P13 and one end of the seventh resistor R7 respectively; the other end of the seventh resistor R7 is connected to the ground; the drain of the thirteenth PMOS transistor P13 is connected to the gates of the fourteenth PMOS transistor P14, one end of the second capacitor C2, the drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the twelfth NMOS transistor N12, and the gate of the thirteenth NMOS transistor N13 respectively; the other end of the second capacitor C2 is connected to the sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the twelfth NMOS transistor N12, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, one end of the third capacitor C3, and the ground respectively; the drain of the fifteenth PMOS transistor P15 is connected to the source of the fourteenth PMOS transistor P14; the gate of the fifteenth PMOS transistor P15 is connected to one end of the eighth resistor R8, the gate of the sixteenth PMOS transistor P16, and the gate of the seventeenth PMOS transistor P17 respectively; the other end of the eighth resistor R8 is connected to the ground; the drain of the sixteenth PMOS transistor P16 is connected to the source of the seventeenth PMOS transistor P17; the drain of the fourteenth PMOS transistor P14 is connected to the drains of the eighth NMOS transistor N8, the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 respectively; the source of the tenth NMOS transistor N10 is connected to the drain of the ninth NMOS transistor N9, the drain of the seventeenth PMOS transistor P17 is connected to the drains of the eleventh NMOS transistor N11, the gate of the tenth NMOS transistor N10, the gate of the twentieth PMOS transistor P20, and the gate of the fourteenth NMOS transistor N14 respectively; the source of the eleventh NMOS transistor N11 is connected to the drain of the twelfth NMOS transistor N12; the drain of the eighteenth PMOS transistor P18 is connected to the drain of the thirteenth NMOS transistor N13 respectively; the gate of the eighteenth PMOS transistor P18 is connected to the gate of the nineteenth PMOS transistor P19; the drain of the nineteenth PMOS transistor P19 is connected to the source of the twentieth PMOS transistor P20; the drain of the twentieth PMOS transistor P20 is connected to the drains of the fourteenth NMOS transistor N14, the other end of the third capacitor C3, and the output OUT of the level detection and reset module I3 respectively.

[0035] Example: A undervoltage lock - out circuit structure with dual - mode redundancy hysteresis characteristics mainly consists of a voltage reference circuit I1, a reference comparison circuit I2, and a level detection and reset module I3, and the output V UVLO is the undervoltage lock - out signal. When the power supply voltage VCC in the circuit gradually rises from 0 level, the voltage reference module I1 starts up automatically as the power supply voltage increases and generates a 1.2V reference voltage Vref. The reference voltage is used as the negative - terminal input of the reference comparator module I2 and is compared with the voltage signal (positive - terminal input) generated by the self - biased voltage - dividing structure of resistor R1, R3, and P1 transistor, generating a reference lock - out signal COMP that can reflect the undervoltage of the power supply voltage. There is a feedback path in the comparator, forming a hysteresis effect, so that the positive and negative jump thresholds of the circuit output are different. During the power - on process of the voltage reference module I1, abnormal output jitter may occur, so the level detection and reset module I3 is introduced. This module can establish the operating point prior to the stable output of the reference voltage by the voltage reference module I1 and quickly output a primary lock - out signal OUT, which is logically operated with the output COMP of the reference comparator module I2 to output the undervoltage lock - out signal V UVLO .

[0036] The voltage reference module I1 has the characteristic of self - starting, and its output is the reference voltage Vref.

[0037] The first NMOS transistor N1, the second NMOS transistor N2, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth resistor R4 form a PTAT current - mirror self - starting circuit. When the power supply is powered on to about 2 N - transistor thresholds, the first NMOS transistor N1 and the second NMOS transistor N2 gradually turn on, and then the third PMOS transistor P3 turns on, injecting current into the bases of the first NPN transistor npn1 and the second NPN transistor npn2 to achieve the self - starting of the current source. When the power supply voltage continues to rise and the current source is stably started, the conduction of the second NMOS transistor N2 causes the first NMOS transistor N1 to form a gate - drain short - circuit relationship, and the gate potential of the third PMOS transistor P3 is pulled up to a potential close to the power supply by the second PMOS transistor P2, and the third PMOS transistor P3 turns off, and the self - starting part ends its operation.

[0038] The classic PTAT current source consists of the first NPN transistor npn1, the second NPN transistor npn2, the fifth resistor R5, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the first capacitor C1, generating a PTAT current Iref flowing through the fifth resistor R5. According to the mirror - circuit proportional relationship and the drain potential of the P6 transistor being the PTAT voltage reference Vref,

[0039] By adjusting the device parameters, a 1.2V reference voltage with good temperature characteristics is obtained.

[0040] The positive input of the reference comparison circuit I2 is a reference signal reflecting the VCC power-on level generated by the self-biased voltage division structure of the first resistor R1, the third resistor R3, and the first PMOS transistor P1. The negative input of the reference comparison circuit I2 is the reference voltage Vref; when 0.48VCC > Vref + the comparator outputs a high level and the power-on lock ends; When the power supply VCC is powered off, when the divided voltage ratio signal level of the VCC power-on level is less than the reference level, the comparator outputs a low-level reference lock signal; Obtaining The process is as follows: The aspect ratios of the eighth PMOS transistor P8 and the seventh PMOS transistor P7 are 2:1. At this time, the overdrive voltages of the third NMOS transistor N3 and the fourth NMOS transistor N4 are respectively:

[0041]

[0042]

[0043] Among them, represents the gate oxide capacitance per unit area; represents the gate width / gate length; represents the electron mobility; The current Iref flowing through the fifth NMOS transistor N5 is:

[0044]

[0045] Among them, represents the current flowing through P7; represents the current flowing through P8; When the power supply is powered off, the output signal of the first-stage inverter is fed back to the gate of the tenth PMOS transistor P10 to control it to be in the on state, and the mirror current of the ninth PMOS transistor P9 is injected into the third NMOS transistor N3. Among them, the aspect ratios of the seventh PMOS transistor P7, the ninth PMOS transistor P9, and the eighth PMOS transistor P8 are P7:P9:P8 = 1:1:2. Therefore, there is the following formula:

[0046] Therefore, when 0.48VCC < Vref, the comparator outputs a low-level reference lock signal.

[0047] The hysteresis interval of the reference lock threshold is 130mV. The reference lock start threshold and the lock end threshold are different, effectively avoiding frequent chip restart due to power supply voltage fluctuations, thereby improving the circuit reliability.

[0048] The level detection and reset module I3 can preferentially establish a working point before the reference is established during the power-on process, and quickly output a primary lock signal OUT, which can effectively shield the abnormal output jitter that may occur during the power-on process of the voltage reference module I1.

[0049] During the power-on process of the power supply VCC, when the voltage of the power supply VCC is greater than the thresholds of the sixteenth PMOS transistor P16 and the seventeenth PMOS transistor P17, they conduct, the gate potential of the fourteenth NMOS transistor N14 is pulled high, and the OUT output is at a low level, providing a primary undervoltage lock signal. As the power supply voltage VCC further increases, the seventh NMOS transistor N7 and the fourteenth PMOS transistor P14 conduct (at this time, the current flowing through the fourteenth PMOS transistor P14 is the sum of the currents of the eighth NMOS transistor N8 and the ninth NMOS transistor N9), the gate potential of the eleventh NMOS transistor N11 increases, and finally the eleventh NMOS transistor N11 is turned on, the gate potential of the fourteenth NMOS transistor N14 is pulled low accordingly, and the OUT output is at a high level, releasing the primary undervoltage lock.

[0050] When the power supply VCC starts to lose power, the tenth NMOS transistor N10 is in the off state (at this time, the current flowing through the fourteenth PMOS transistor P14 is only the current flowing through the N8 transistor). As the power supply voltage decreases, the gate potential of the eleventh NMOS transistor N11 gradually decreases, and finally the eleventh NMOS transistor N11 is turned off, the gate potential of the fourteenth NMOS transistor N14 increases accordingly, and the OUT output is at a low level, outputting an undervoltage lock signal. The difference in the current flowing through the P14 transistor during the power-on and power-off of the power supply VCC generates different power-on and power-off reset points, effectively avoiding frequent restart of the chip caused by power supply voltage fluctuations and improving the reliability of the circuit.

[0051] Global undervoltage lock signal V UVLO Is generated by the logical operation of the reference lock signal COMP and the level detection signal OUT as Figure 1 Shown. The undervoltage lock circuit with dual-mode redundant hysteresis characteristics, this structure includes two-stage reset modules. By virtue of the characteristic that the level detection and reset module I3 preferentially establishes a working point during the VCC power-on process and quickly outputs a primary lock signal, it can effectively shield the abnormal output jitter that may occur during the power-on process of the voltage reference module I1; on the other hand, the good temperature stability of the secondary voltage reference module I1 ensures the temperature drift performance of the global undervoltage lock signal. Through the logical complementarity of the two-stage reset modules, while fully considering the timing reliability and temperature stability during the power-on process, dual-mode redundancy of the global undervoltage lock output signal is realized, and the temperature stability and reliability in the full temperature range are ensured, thus guaranteeing the normal function of the circuit.

[0052] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An undervoltage lockout circuit structure with a dual - mode redundant hysteresis characteristic, characterized in that, Comprising: A first PMOS transistor P1, a first resistor R1, a second resistor R2, a third resistor R3, a voltage reference circuit I1, a reference comparison circuit I2, a level detection and reset module I3, and an AND gate AND1; The source of the first PMOS transistor P1 is connected to the power supply VCC. The gate of the first PMOS transistor P1 is connected to one end of the second resistor R2. The drain of the first PMOS transistor P1 is connected to one end of the third resistor R3. One end of the first resistor R1 is respectively connected to the other end of the third resistor R3 and the positive terminal input of the reference comparison circuit I2. The other end of the second resistor R2 is respectively connected to the other end of the first resistor R1 and the ground; The output of the voltage reference circuit I1 is connected to the negative input of the reference comparison circuit I2; one of the power supply terminals of the reference comparison circuit I2 is grounded, and the other is connected to the power supply VCC; the output of the reference comparison circuit I2 is connected to one input of the AND gate AND1, and the output of the threshold reset module I3 is connected to the other input of the AND gate AND1. The output of the AND gate is the under-voltage lockout signal V of the under-voltage lockout circuit UVLO .

2. The under-voltage lockout circuit structure with dual-mode redundant hysteresis characteristics according to claim 1, characterized in that The voltage reference circuit I1 includes a current mirror self-starting circuit, a classic PTAT current source circuit, and an output circuit. The current mirror self-starting circuit sends a start command to the classic PTAT current source circuit. The current provided by the classic PTAT current source circuit generates a PTAT voltage reference Vref through the output circuit. The PTAT voltage reference Vref is input to the negative terminal of the reference comparison circuit I2.

3. The under-voltage lockout circuit structure with dual-mode redundant hysteresis characteristics according to claim 2, characterized in that, The current mirror self-starting circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth resistor R4; The source of the second PMOS transistor P2 is externally connected to the power supply VCC, one end of the fourth resistor R4, the source of the third PMOS transistor P3, and the classic PTAT current source circuit. The gate of the second PMOS transistor P2 is externally connected to the classic PTAT current source circuit. The drain of the second PMOS transistor P2 is respectively connected to the drain of the first NMOS transistor N1, the drain of the second NMOS transistor N2, and the gate of the third PMOS transistor P3. The source of the first NMOS transistor N1 is externally connected to the classic PTAT current source circuit and grounded. The gate of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to the other end of the fourth resistor R4. The drain of the third PMOS transistor P3 is externally connected to the classic PTAT current source circuit.

4. A undervoltage lockout circuit structure with a dual-mode redundant hysteresis characteristic according to claim 3, characterized in that The classic PTAT current source circuit includes: a first NPN transistor npn1, a second NPN transistor npn2, a fifth resistor R5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first capacitor C1; The source of the fourth PMOS transistor P4 is respectively connected to the source of the second PMOS transistor P2, one end of the first capacitor C1, the source of the fifth PMOS transistor P5, and the output circuit; the gate of the fourth PMOS transistor P4 is respectively connected to the gate of the fifth PMOS transistor P5, the other end of the first capacitor C1, the gate of the second PMOS transistor P2, the collector of the second NPN transistor npn2, and the output circuit; the drain of the fourth PMOS transistor P4 is respectively connected to the drain of the third PMOS transistor P3, the collector of the first NPN transistor npn1, and the base of the first NPN transistor npn1; the emitter of the first NPN transistor npn1 is connected to the source of the first NMOS transistor N1, one end of the fifth resistor R5, and the output circuit; the base of the first NPN transistor npn1 is connected to the base of the second NPN transistor npn2; the emitter of the second NPN transistor npn2 is connected to the other end of the fifth resistor R5; the collector of the second NPN transistor npn2 is connected to the drain of the fifth PMOS transistor P5.

5. A undervoltage lockout circuit structure with dual-mode redundant hysteresis characteristics according to claim 4, characterized in that, The output circuit includes: a sixth PMOS transistor P6, a sixth resistor R6, and a third NPN transistor npn3; The source of the sixth PMOS transistor P6 is connected to the source of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor P6 is connected to one end of the sixth resistor R6 and the output Vref of the voltage reference circuit I1; the collector of the third NPN transistor npn3 is connected to the other end of the sixth resistor R6 and the base of the third NPN transistor NPN; the emitter of the third NPN transistor npn3 is connected to one end of the fifth resistor R5.

6. The under-voltage lockout circuit structure with dual-mode redundant hysteresis characteristics according to claim 5, characterized in that The reference comparison circuit I2 includes a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; The source of the seventh PMOS transistor P7 is respectively connected to the source of the eighth PMOS transistor P8, the source of the ninth PMOS transistor P9, the source of the eleventh PMOS transistor P11, and the power supply VCC; the gate of the seventh PMOS transistor P7 is respectively connected to the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the gate of the ninth PMOS transistor P9, the drain of the third NMOS transistor N3, and the drain of the tenth PMOS transistor P10; The gate of the third NMOS transistor N3 is the negative terminal input of the reference comparison module I2; the source of the third NMOS transistor N3 is respectively connected to the source of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5; the gate of the fourth NMOS transistor N4 is the positive terminal input of the reference comparison module I2; the drain of the fourth NMOS transistor N4 is respectively connected to the drain of the eighth PMOS transistor P8 and the gate of the eleventh PMOS transistor P11; the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10; the gate of the fifth NMOS transistor N5 is connected to the gate of the sixth NMOS transistor N6; the source of the fifth NMOS transistor N5 is respectively connected to the source of the sixth NMOS transistor N6 and the ground; the drain of the eleventh PMOS transistor P11 is respectively connected to the drain of the sixth NMOS transistor N6 and the input of the delay inverter INV1; the gate of the tenth PMOS transistor P10 is respectively connected to the output of the delay inverter INV1 and the input of the inverter INV2; the output of the inverter INV2 is the output COMP of the reference comparator module I2.

7. A under-voltage lockout circuit structure with dual-mode redundant hysteresis characteristics according to claim 6, characterized in that, The level detection and reset module I3 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a second capacitor C2, a third capacitor C3, a seventh resistor R7 and an eighth resistor R8; The source of the twelfth PMOS transistor P12 is connected to the sources of the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, and the power supply VCC respectively; the drain of the twelfth PMOS transistor P12 is connected to the source of the thirteenth PMOS transistor P13; the gate of the twelfth PMOS transistor P12 is connected to the gate of the thirteenth PMOS transistor P13 and one end of the seventh resistor R7 respectively; the other end of the seventh resistor R7 is connected to the ground; the drain of the thirteenth PMOS transistor P13 is connected to the gate of the fourteenth PMOS transistor P14, one end of the second capacitor C2, the drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, the gate of the twelfth NMOS transistor N12, and the gate of the thirteenth NMOS transistor N13 respectively; the other end of the second capacitor C2 is connected to the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, the source of the twelfth NMOS transistor N12, the source of the thirteenth NMOS transistor N13, the source of the fourteenth NMOS transistor N14, one end of the third capacitor C3, and the ground respectively; the drain of the fifteenth PMOS transistor P15 is connected to the source of the fourteenth PMOS transistor P14; the gate of the fifteenth PMOS transistor P15 is connected to one end of the eighth resistor R8, the gate of the sixteenth PMOS transistor P16, and the gate of the seventeenth PMOS transistor P17 respectively; the other end of the eighth resistor R8 is connected to the ground; the drain of the sixteenth PMOS transistor P16 is connected to the source of the seventeenth PMOS transistor P17; the drain of the fourteenth PMOS transistor P14 is connected to the drain of the eighth NMOS transistor N8, the drain of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11 respectively; the source of the tenth NMOS transistor N10 is connected to the drain of the ninth NMOS transistor N9, and the drain of the seventeenth PMOS transistor P17 is connected to the drain of the eleventh NMOS transistor N11, the gate of the tenth NMOS transistor N10, the gate of the twentieth PMOS transistor P20, and the gate of the fourteenth NMOS transistor N14 respectively; the source of the eleventh NMOS transistor N11 is connected to the drain of the twelfth NMOS transistor N12; the drain of the eighteenth PMOS transistor P18 is connected to the drain of the thirteenth NMOS transistor N13 respectively; the gate of the eighteenth PMOS transistor P18 is connected to the gate of the nineteenth PMOS transistor P19; the drain of the nineteenth PMOS transistor P19 is connected to the source of the twentieth PMOS transistor P20; the drain of the twentieth PMOS transistor P20 is connected to the drain of the fourteenth NMOS transistor N14, the other end of the third capacitor C3, and the output OUT of the level detection and reset module I3 respectively.

8. A undervoltage lockout circuit structure with a dual-mode redundant hysteresis characteristic according to claim 7, characterized in that The current provided by the classical PTAT current source circuit generates a PTAT voltage reference Vref through the output circuit, specifically: Among them, is the voltage between the base and the emitter of the third NPN transistor npn3.

9. A undervoltage lockout circuit structure with dual - mode redundant hysteresis characteristics according to claim 1, characterized in that, The positive input of the reference comparison circuit I2 is a reference signal reflecting the VCC power-on level generated by the self-biased voltage division structure of the first resistor R1, the third resistor R3, and the first PMOS transistor P1. The negative input of the reference comparison circuit I2 is the reference voltage Vref; when 0.48VCC > Vref + , the comparator outputs a high level and the power-on lock is ended; When the power supply VCC loses power, when the divided voltage ratio signal level of the VCC power-on level is less than the reference level, the comparator outputs a low-level reference locking signal; Obtain The process is as follows: The aspect ratios of the eighth PMOS transistor P8 and the seventh PMOS transistor P7 are 2:

1. At this time, the overdrive voltages of the third NMOS transistor N3 and the fourth NMOS transistor N4 are respectively: Among them, represents the gate oxide capacitance per unit area; represents the gate width / gate length; represents the electron mobility; The current Iref flowing through the fifth NMOS transistor N5 is: Among them, represents the current flowing through P7; represents the current flowing through P8; When the power supply loses power, the output signal of the first-stage inverter is fed back to the gate of the tenth PMOS transistor P10 at this time, controlling it to be in the conducting state, and injecting the mirror current of the ninth PMOS transistor P9 into the third NMOS transistor N3. Among them, the aspect ratios of the seventh PMOS transistor P7, the ninth PMOS transistor P9, and the eighth PMOS transistor P8 are P7:P9:P8 = 1:1:

2. Therefore, there is the following formula: Therefore, when 0.48VCC < Vref, the comparator outputs a low-level reference locking signal.

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