Programmable communication network and preparation method thereof for constructing multi-core particle microsystem

Abstract

The invention relates to the technical field of integrated circuit packaging. The invention provides a programmable communication network and a preparation method of the programmable communication network for constructing a multi-core particle microsystem. The programmable communication network comprises a control unit and a signal guide array, the control unit is provided with an input port, an output port and a path repair port, the output port is used for outputting a communication path configuration signal, and the path repair port receives an external input signal when a communication fault occurs and drives the control unit to regenerate the communication path configuration signal to realize path self-repair. The signal guide array comprises a plurality of guide switches, the plurality of core particles are arranged on the periphery of the signal guide array, the guide switches are connected with the output port, and communication paths are established among the core particles according to the configuration signals. According to the preparation method, the multi-core particle microsystem comprising the programmable communication network can be constructed. The method has the dynamic configuration and fault self-recovery capability of a communication path, can support the function reconstruction and stable operation of the multi-chip microsystem, and is suitable for the high-reliability requirement in a complex application scene.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and more specifically, to a programmable communication network and a preparation method for constructing a multi-die micro-system thereof. Background Art

[0002] As the integration scale of micro-systems in intelligent computing, signal processing, and edge applications continues to expand, the complexity of system construction also continues to increase. Integrating multiple dies on a silicon interposer as needed and achieving high-speed interconnection between dies through a local communication structure has become an important way to construct a multi-die micro-system. This type of multi-die integration structure helps to improve the modularity and process compatibility of the system, and shows advantages in supporting partition deployment, function separation, and scalable architecture.

[0003] However, in existing multi-die micro-systems, the communication paths between dies often rely on fixed interconnection methods determined before packaging. Once the communication paths are configured, it is difficult to modify them during system operation, resulting in the communication topology tending to be solidified and lacking flexible path reconstruction capabilities. This static interconnection method limits the adaptability of the system in multi-task switching and multi-scenario configuration, making it difficult to meet the flexible requirements of loading different function combinations on demand, and reducing the scalability and reusability of the micro-system. In addition, most current designs do not set up an abnormal detection and response mechanism for communication paths. During the system operation cycle, once the communication path is interrupted or the connection becomes unstable due to factors such as stress mismatch, electromigration, and material fatigue, it usually causes the corresponding functional unit to fail, and may also affect the interruption of the entire system task chain, resulting in insufficient reliability of the micro-system during long-term operation or extreme working conditions, and making it difficult to meet application scenarios with strict requirements for high stability, high maintainability, and high adaptability.

[0004] Therefore, there is an urgent need to propose a communication network with the ability to dynamically configure communication paths and self-recoverable connection states, as a key module for die interconnection in a micro-system, to support the function reconstruction and operation stability of the multi-die micro-system and meet the long-term use requirements in complex application environments. Summary of the Invention

[0005] The purpose of the present invention is to provide a programmable communication network and a preparation method for constructing a multi-die micro-system thereof, aiming at the deficiencies in the above-mentioned existing technologies, to solve the problems of low functional flexibility of the communication structure and inability to respond to path failures in the existing technologies.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows: The present application provides a programmable communication network, including a control unit and a signal guiding array. The control unit includes an input port and multiple output ports, and the output ports are used to output communication path configuration signals; the control unit further includes a path repair port, which is used to receive external input signals when a communication path fails, and the control unit regenerates communication path configuration signals according to the input signals to achieve self-repair of the communication path. The signal guiding array includes multiple guiding switches, and the guiding switches are connected to the output ports. Multiple die chips are arranged on the peripheral edge of the signal guiding array, and the guiding switches establish programmable selective communication paths between the die chips according to the communication path configuration signals.

[0007] The present application realizes the on-demand establishment and dynamic reconstruction of communication paths between die chips by constructing a configurable connection mechanism between the control unit and the signal guiding array, and solves the problems of fixed communication networks and inability to respond to path anomalies in the prior art. The control unit generates communication path configuration signals according to input signals and distributes them to the guiding switches to achieve precise control of the signal path. The guiding switches are distributed in the signal guiding array as switching nodes, and the combination of their switch states determines the formation of communication paths. Instead of relying on preset wiring, the path is constructed through dynamic configuration, enhancing the functional adaptability and flexibility of the communication network. When a path fails during system operation, the control unit can receive external input signals through the path repair port, update the communication path configuration signals, and drive the guiding switches to rebuild the connection relationship, quickly completing the restoration of the communication path and ensuring that the system task chain is not interrupted. This mechanism supports dynamically configuring communication relationships according to system functions and adaptively reconstructing connections when a fault occurs, breaking the static limitations of traditional interconnection structures, constructing a reconfigurable and recoverable communication system, and enhancing the robustness and expansion ability of multi-die micro-systems.

[0008] Furthermore, the control unit can output communication path configuration signals of different combinations to construct communication paths between die chips corresponding to different system functions. By regulating the connection states of the guiding switches, this mechanism can establish targeted communication paths between die chips according to task requirements, realize flexible organization and rapid reconstruction of functional modules, and enhance the system's adaptability to multi-scenario applications.

[0009] Furthermore, the guiding switch is composed of at least two NMOS transistors and an inverter. This structure has the characteristics of fast response speed and simple control logic, facilitating the stable conduction and reliable disconnection of communication paths, and is suitable for communication connection control between a large number of die chips.

[0010] Furthermore, the types of guiding switches include single-pole single-throw switches and single-pole double-throw switches.

[0011] Furthermore, the control signal lines in the signal guiding array adopt a hierarchical wiring method, and decoupling capacitors and pull-up resistors or pull-down resistors are provided to achieve fast switching of the guiding switches.

[0012] Furthermore, a metal layer is provided in the signal guiding array, and the metal layer is located in the angular region between the control signal lines and the transmission signal lines of the guiding switches, so as to reduce the crosstalk influence of the control signal jump on the data transmission path.

[0013] Furthermore, the signal guiding array supports expansion according to a 1×2 or 2×2 topology structure, and can realize the orderly extension of the communication network in the horizontal and vertical directions, meeting the flexible integration requirements of the multi-die system under different scales.

[0014] The present application also provides a preparation method for constructing a multi-die microsystem with a programmable communication network. The multi-die microsystem includes the above-mentioned programmable communication network, and the preparation method includes the following steps: S1. Prepare a programmable communication network bare chip; S2. Prepare through-silicon vias on the first silicon wafer; S3. Prepare a redistribution layer on the surfaces of the first silicon wafer and the second silicon wafer; S4. Place multiple dies and the programmable communication network bare chip on the upper surfaces of the first silicon wafer and the second silicon wafer respectively, and bond and fix them; S5. Prepare micro-bumps on the lower surface of the first silicon wafer and the upper surface of the second silicon wafer, and then bond and fix the first silicon wafer and the second silicon wafer; S6. Perform dicing on the bonded wafers and encapsulate to obtain a microsystem with a programmable communication network.

[0015] Furthermore, in S1, laser heat treatment is performed on the signal guiding array region to improve the thermal stability and connection reliability of the metal wiring structure in the guiding switch region.

[0016] Furthermore, the laser heat treatment uses a laser beam with a wavelength of 532 nm, a pulse width of 60 ns, a pulse energy of 100 μJ, and a spot diameter of 15 μm.

[0017] Furthermore, in S4, cross-shaped alignment marks are provided on the upper surfaces of the first silicon wafer and the second silicon wafer to assist in the precise positioning and bonding alignment of the dies and the programmable communication network bare chip, improving the assembly accuracy and interconnection consistency.

[0018] Furthermore, in S4, before bonding the dies and the programmable communication network bare chip, a filling material is provided between them and the first silicon wafer or the second silicon wafer to enhance the thermal conduction performance after bonding and improve the heat dissipation efficiency of the microsystem packaging structure.

[0019] Advantages of the present invention compared with the prior art: (1) The present application constructs a communication path configuration mechanism in which the control unit outputs a configuration signal and drives the guiding switch to conduct dynamically, breaking the limitation of relying on pre-packaging wiring for communication connection in traditional microsystems, and enabling the communication structure to remain variable after packaging. Compared with the existing fixed interconnection structure, this solution supports flexible switching of the communication relationship between dielets according to task changes or functional reconstruction requirements during the operation stage, greatly improving the configuration freedom and scenario adaptation ability of the system.

[0020] (2) The present application introduces a path repair port as an external response interface for communication abnormal states. After receiving a fault input signal, the control unit can regenerate a path configuration signal, and then control the guiding switch to adjust the connection state to achieve structural-level recovery of the communication path. This method effectively replaces the existing method that relies on external bypass or manual intervention to restore communication, improving the adaptive ability and long-term operation stability of the system in the scenario of channel faults.

[0021] (3) In the present application, dielets are arranged around the edge of the guiding switch array, and the guiding structure has the ability of topological expansion, forming a communication network framework that can grow horizontally or vertically in structure. This design enables the communication network to have good module scalability while maintaining overall controllability, and can adapt to the packaging requirements of multi-type and multi-scale dielet systems, significantly superior to the existing point-to-point fixed connection scheme that cannot adapt to structural expansion. Brief Description of the Drawings

[0022] Figure 1 Schematic diagram of the basic unit structure of a programmable communication network provided by the present invention; Figure 2 For Figure 1 Schematic diagram of the single-pole single-throw switch structure in a programmable communication network; Figure 3 For Figure 1 Schematic diagram of the single-pole double-throw switch structure in a programmable communication network; Figure 4 For the present invention Figure 1 Schematic diagram of the structure of the expanded 1×2 programmable communication network; Figure 5 For the present invention Figure 1 Schematic diagram of the structure of the expanded 2×2 programmable communication network; Figure 6 Schematic diagram of a three-dimensional local structure of a multi-dielet microsystem constructed by a programmable communication network provided by the present invention; Figure 7 For Figure 6 Schematic diagram of the three-dimensional structure of the multi-dielet microsystem after packaging; Figure 8 ForFigure 7 Flowchart of a method for preparing a multi-dielet microsystem.

[0023] Icons: 1 - Control unit; 2 - Signal guiding array; 3 - Guiding switch; 4 - Dielet; 5 - Programmable communication network bare chip; 6 - First silicon wafer; 7 - Second silicon wafer; 8 - Through-silicon via; 9 - Redistribution layer; 10 - FR-4 packaging substrate. Detailed implementation manners

[0024] To make the implementation process of the present invention clearer, the following will be described in detail with reference to the accompanying drawings.

[0025] Example 1: The present invention provides a programmable communication network, as Figure 1 shown. The programmable communication network includes a control unit 1 and a signal guiding array 2. The control unit 1 includes an input port and a plurality of output ports. The output ports are used to output communication path configuration signals. The control unit 1 further includes a path repair port, which is used to receive external input signals when a communication path fails. The control unit 1 regenerates communication path configuration signals according to the input signals to achieve self-repair of the communication path. The signal guiding array 2 includes a plurality of guiding switches 3, and the guiding switches 3 are connected to the output ports. Multiple dielets 4 are arranged on the peripheral edge of the signal guiding array 2. The guiding switches 3 establish programmable selective communication paths between the dielets 4 according to the communication path configuration signals.

[0026] In this embodiment, a total of 20 ports are provided in the programmable communication network control unit 1. Among them, Ix is the signal input port of the programmable communication network control unit 1, which is used to receive function setting signals sent by the system host computer or an external controller. O1 - O10, C11 - C42 represent the output ports of the programmable communication network control unit 1, which are used to output communication path configuration signals generated after the Ix input signals are encoded and decoded by the control unit 1. The control unit 1 further includes a path repair port Ixx, which is used to receive external input signals to trigger repair when a communication path between the dielets 4 fails. After the control unit 1 encodes and decodes the input signals, it outputs new communication path configuration signals to the corresponding output ports to control the conduction state of the guiding switches 3, thereby realizing the construction or switching of the communication path between the dielets 4.

[0027] Twenty guiding switches 3 are provided in the programmable communication network signal guiding array 2. The guiding switches 3 are represented as S1 - S 10 , C 11 - C 42, are respectively connected in one-to-one correspondence with the output ports of the control unit 1 to establish a matching relationship. The guiding switch 3 is used to establish a communication path between the dies 4 or switch the path, and supports the configuration of various structural scenarios such as point-to-point communication, multi-input selection, and cross-link switching. To support system expansion and path redundancy, in this embodiment, the signal guiding array 2 can also reserve several unconnected channels and vacant interfaces for future expansion of die 4 nodes, increasing redundant conduction paths, or integrating relay modules, with good structural scalability and path fault tolerance.

[0028] The guiding switch 3 includes two types: single-pole single-throw switch and single-pole double-throw switch, which are respectively applicable to the on / off control of the communication path and multi-channel path switching. The specific structure of the guiding switch 3 is as Figure 2 and Figure 3 shown. Both use NMOSFET transistors and inverters to form a low-power control circuit, with advantages such as fast response, low power consumption, and good signal integrity. The output level of the control unit 1 can use 1.8V or 3.3V standard IO level signals. To improve the compatibility of system wiring, all control lines adopt a hierarchical wiring method and are equipped with decoupling capacitors and pull-up or pull-down resistors to achieve fast and stable switching and state holding functions. The guiding switch 3 conducts when the gate voltage of the NMOSFET transistor is high and turns off when the gate voltage of the NMOSFET transistor is low.

[0029] As Figure 2 shown, the structure of the single-pole single-throw switch consists of two NMOSFET transistors (Q1, Q2) and an inverter. Figure 2 (a) is the on state of this single-pole single-throw switch, Figure 2 (b) is the off state of this single-pole single-throw switch. The single-pole single-throw switch sets a signal input port P in and a signal output port P out , and O x is the control signal output by the programmable communication network control unit 1. When O x is high, the inverter outputs a low level, making Q1 conduct and Q2 turn off. The signal is input from the P in port and output through the P out port to form a communication path. When O x is low, the inverter outputs a high level. At this time, Q1 turns off and Q2 conducts, and the P in port is connected to the ground, and the communication path is disconnected, forming a high isolation state. This switch structure provides a low-resistance path in the on state and suppresses interference by signal bypass in the off state through the combined control of Q1 and Q2, thereby improving the stability and anti-interference ability of the communication path.

[0030] As Figure 3As shown, the single-pole double-throw switch structure is composed of two single-pole single-throw switches, including four NMOSFET transistors (Q1, Q2, Q3, Q4) and an inverter. It has two input ports P in1 , P in2 and an output port P out , and O x is the control signal. When O x is at a high level, Q1 and Q4 are turned on, and Q2 and Q3 are turned off. As shown in Figure 3 (a), the signal is output from the P in1 port through the guiding switch 3 to the P out port; when O x is at a low level, Q2 and Q3 are turned on, and Q1 and Q4 are turned off. As shown in Figure 3 (b), the signal is transmitted from the P in2 port to the P out port. This structure is suitable for the selection control of multiple input channels in the communication path of the die 4, and can flexibly switch the communication direction according to the control signal to ensure the selectivity and mutual exclusion of the path.

[0031] In order to reduce the interference of the control signal on the data signal line during the switching process of the guiding switch 3, a metal layer design is introduced into the wiring structure of the signal guiding array 2. This metal layer is set in the angular region between the control signal line and the transmission signal line, playing a role in shielding the electromagnetic radiation of the control signal, effectively isolating the electromagnetic coupling path, suppressing the crosstalk effect caused by high-frequency jumps, and thus improving the anti-interference ability and signal integrity of the communication link between dies 4. The metal layer can be made of aluminum, copper or metallized composite materials, with excellent electrical conductivity and electromagnetic shielding characteristics, and can be integrated into the structure of the signal guiding array 2 through standard CMOS-compatible processes or multi-layer wiring processes. Further, this metal layer also has the function of adjusting the distributed capacitance. In the structure where multiple signal lines are intertwined, there is often an asymmetric distributed capacitance between the control signal and the data path, which is likely to cause problems such as signal rising edge distortion and jitter. By introducing a metal layer in the middle position and grounding it or keeping it at a constant potential, the mutual capacitance between the control signal line and the transmission signal line can be balanced, thereby improving the signal edge integrity and suppressing high-frequency reflections. In addition, this metal layer can also form a charge release channel during the high-speed guiding switch switching, reducing the ground bounce noise caused by voltage mutations and enhancing the overall electromagnetic compatibility performance of the system.

[0032] The control unit 1 outputs different combinations of communication path configuration signals by generating different control commands to construct the communication paths between dies 4 corresponding to different system functions. In this embodiment, 4 dies 4 are set, represented by C1, C2, C3, and C4 respectively. The following lists four task configurations of functions A, B, C, and D to illustrate the communication path configuration logic and the self-repair process: Under the function A configuration, the control unit 1 receives the signal I1, completes the encoding and decoding of the signal internally, and outputs a high level to the output ports O1, C11, C41, O4, C21, C31, and a low level to the remaining ports. This enables the corresponding S1, C 11 , C 41 and S4, C 21 , C 31 in the signal guiding array 2 to turn on the guiding switches 3, and turn off the remaining guiding switches 3, constructing two independent communication paths of C1 - C4 and C2 - C3 to achieve parallel task distribution under system function A. When this communication path is interrupted due to environmental stresses such as high temperature and high impact, the control unit 1 can receive the path repair signal I 11 through the path repair port, generate a control signal after completing the encoding and decoding of the signal in the control unit 1, output a high level to O7, C12, C42 and O9, C22, C32, and a low level to the remaining ports, driving S7, C 12 , C 42 and S9, C 22 , C 32 in the guiding switches 3 to turn on, and turn off other guiding switches 3 to replace the original path, complete path reconstruction and signal path self - repair, and achieve stable operation of function A.

[0033] Under the function B configuration, the control unit 1 receives the signal I2 and controls the output ports O3, C11, C21, O5, C31, C41 to be at a high level, and the remaining ports to output a low level, driving S3, C 11 , C 21 and S5, C 31 , C 41 to turn on, and turn off the remaining guiding switches 3 to form a communication path of C1 - C2 and C3 - C4 to achieve the communication structure required by system function B. If the path fails, the control unit 1 receives the path repair signal I 22 , and thus outputs a high level to O8, C12, C22 and O10, C32, C42, and a low level to the remaining ports, turning on S8, C 12 , C 22 and S 10 , C 32 , C 42 , and turning off the remaining guiding switches 3 to construct a backup path to achieve stable operation of function B.

[0034] Under the function C configuration, the control unit 1 receives the signal I3 and controls the output ports O2, C11, C31 and O6, C41, C21 to be at a high level, and the remaining ports to output a low level, driving S2, C 11 , C 31 and S6, C 41 , C21 conducts, and the remaining guiding switches 3 are turned off to construct a communication path between C1-C3 and C2-C4, which is applicable to an asymmetric functional communication structure. When a break occurs in C1-C3 in the communication path, the control unit 1 receives the path repair signal I 33 , and thus outputs a high level to O6, C41, C21 and O8, O9, C12, C32, and the remaining ports output a low level to turn on S6, C 41 , C 21 and S8, S9, C 12 , C 32 , and the remaining guiding switches 3 are turned off to re-establish the C1-C3 path and achieve the path recovery of function C.

[0035] In the functional D configuration, the control unit 1 receives the signal I4 and controls the output ports O1, O3, C41, C11 and O4, O5, C21, C31 to be at a high level, and the remaining ports output a low level to drive S1, S3, C 41 , C 11 and S4, S5, C 21 , C 31 to conduct, and the remaining guiding switches 3 are turned off to achieve the full interconnection between C1-C2-C3-C4. When a break occurs in C1-C3 or C3-C4 in the communication path, the control unit 1 receives the path repair signal I 44 , and thus outputs a high level to O7, O8, C42, C12 and O9, O10, C22, C32, and the remaining ports output a low level to turn on S7, S8, C 42 , C 12 and S9, S 10 , C 22 , C 32 , and the remaining guiding switches 3 are turned off to re-construct the signal routing path between C1, C2, C3 and C4, complete the alternative construction of the complete path, and achieve the path recovery of function D.

[0036] Through the above functional configuration, the programmable communication network structure described in this embodiment can output communication path configuration signals of different combinations according to the system function requirements, construct a programmable communication connection between the chiplets 4, and is applicable to the communication organization and reconstruction of various functional tasks. When a communication path fails, the control unit 1 can control the standby guiding switches 3 to switch states according to external input signals to complete the alternative configuration of the communication path, thereby maintaining the communication continuity between the chiplets 4. This structure has the flexibility of path configuration and the self-recovery ability of the communication path, which is beneficial to improving the function reconfiguration ability and operation stability of the microsystem.

[0037] Embodiment 2: This embodiment provides a programmable communication network with two-dimensional topology expansion ability, such asFigure 4 , Figure 5 As shown in Figure 5 , based on the communication basic unit described in Embodiment 1, it is structurally expanded in the horizontal and vertical directions through a modular array method to form a grid-like interconnection architecture covering more dielets 4. This structure is suitable for microsystem integration applications with a large number of dielets 4, clear task area division, or high communication density requirements. It can support flexible path configuration and cross-region communication scheduling among multiple modules, improving the structural adaptability and functional reconfigurability of the microsystem under large-scale integration.

[0038] As Figure 4 shown in Figure 4 , in a 1×2 topology structure, the programmable communication network includes two signal guiding arrays 2 arranged in parallel, which are respectively used to connect dielets 4 in different functional areas. A total of 6 dielets 4 are provided. The left signal guiding array 2 is connected to C1, C5, and C6, and the right signal guiding array 2 is connected to C2, C3, and C4. The two signal guiding arrays 2 communicate with each other through a middle path, forming a connected path configuration network as a whole. The control unit 1 controls the guiding switches 3 in the signal guiding array 2 to conduct or turn off, and flexibly establishes communication paths between dielets 4 according to the system function requirements according to the working principle described in Embodiment 1. For example, when a communication path between C1 and C3 needs to be constructed, C1-C2-C3 can be configured as a signal channel; when communication is required between C2 and C6, the path C2-C1-C6 can be configured as a signal channel. If a connection fails in the above path, the control unit 1 can also reconfigure the combination of guiding switches 3 according to the path exception signal input from the outside, and construct standby paths such as C1-C4-C3 and C2-C5-C6 to achieve rapid recovery of the communication link. This structure not only supports intra-region communication but also cross-region communication configuration, has a high degree of path flexibility and structural reuse ability, and is suitable for multi-task parallel and region cooperation application scenarios.

[0039] As Figure 5As shown, in the 2×2 topology structure, the programmable communication network structure is formed by arranging multiple signal guiding array units 2 in an array in the horizontal and vertical directions, overall constituting a two-dimensional grid-like path configuration structure. A total of 8 die chips 4 are provided and distributed on the outer periphery of the signal guiding array 2, and C1-C8 are used to represent the die chips 4. Each signal guiding array 2 is connected to adjacent die chips 4 or other signal guiding arrays 2 through multiple internal guiding switches 3 to construct a programmable communication interconnection network structure. The control unit 1 uniformly outputs a set of communication path configuration signals, which respectively act on the control nodes of each guiding switch 3 in the two-dimensional array to drive the combined conduction of the row and column guiding paths. Through the combined configuration of the guiding switches 3, the required communication paths can be established between multiple die chips 4 to achieve signal forwarding and task chain reconstruction within the region or across regions. For example, the communication path between C1-C6 can be constructed by controlling the path configuration; when a communication path fails, the control unit 1 can receive the fault identification signal input from the outside through the path repair port and generate a new communication path configuration signal, enabling other combinations of guiding switches 3, such as C1-C8-C7-C6, to complete the connection switch and achieve dynamic self-repair of the path. This structure is applicable to multi-module integrated systems that require high communication density and regional cooperation, and can support the parallel processing and dynamic scheduling of complex tasks in the micro-system.

[0040] Based on the basic communication logic and control mechanism in Embodiment 1, the above topology expansion scheme realizes the scale expansion and layout flexibility of the communication network through the structure replication of the signal guiding array 2 and the unified configuration of the control path. This structure improves the organization density and function mapping ability between die chips 4 in the micro-system, and at the same time enhances the redundant configuration of the path level and the ability to handle exceptions during the communication process, and is applicable to the multi-die micro-system integration scenario that supports regional deployment, task dynamic scheduling, and system stable operation.

[0041] Embodiment 3: This embodiment provides a multi-die micro-system based on a programmable communication network and its manufacturing method, aiming to realize the application of the programmable communication network described in Embodiment 1 or Embodiment 2 in micro-system integration. Based on the 1×2 programmable communication network in Embodiment 2, the structure of the constructed multi-die micro-system is as Figure 6 and Figure 7 shown. Figure 6 shows the three-dimensional micro-system structure before dicing. The system includes 6 die chips 4 and 1 1×2 programmable communication network bare chip 5, which are respectively arranged on the surfaces of the first silicon wafer 6 and the second silicon wafer 7, and vertical communication paths are formed by means of through-silicon vias 8 and redistribution layers 9. Figure 7It is a schematic diagram of the overall structure after dicing and packaging the microsystem. A complete package structure is formed on the periphery, and the internal communication path and functional chips have been integrated into the microsystem packaging unit. While ensuring the programmable configuration of the communication path, this structure guarantees the compactness of package integration and the stability of communication interconnection.

[0042] Based on the above structural layout, this embodiment further proposes a preparation method for constructing a multi-die microsystem with a programmable communication network, as Figure 8 shown, which specifically includes the following steps: S1. Fabricate a programmable communication network bare chip 5; the fabricated programmable communication network bare chip 5 is a communication network unit with a 1×2 structure, which is monolithically integrated on a whole silicon wafer using a triple-well CMOS process, integrating a signal guiding array 2 and a control unit 1 to meet the performance requirements of low insertion loss and high isolation. Subsequently, the silicon wafer is precisely diced using a laser device with a power of 1.5 kW to obtain N pieces of 1×2 structure programmable communication network bare chips 5 with consistent size and complete structure for subsequent microsystem integration and packaging.

[0043] S2. Fabricate through-silicon vias 8 on the first silicon wafer 6; on the surface of the first silicon wafer 6 with a thickness of 155 μm, a conical through-silicon via 8 is etched using a laser device with a frequency of 50 kHz, a wavelength of 400 nm, a pulse width of 60 ns, a pulse energy of 400 μJ, and a spot diameter of 10 μm; then the through-hole is filled with polymer, and the polymer is ablated using a laser with a power of 2 kW to obtain a through-hole with an insulating inner wall structure; on the surface of the through-hole inner wall, a TiN barrier layer is deposited using physical vapor deposition technology under an argon protection environment with TiN as the sputtering target, at a radio frequency source frequency of 13.56 MHz, a pre-sputtering power of 50 W, a sputtering power of 25 W, and a sputtering time of 8 minutes; continue to use physical vapor deposition technology to prepare a metal seed layer on the barrier layer, and with a CuSO4 electroplating solution with a concentration of 0.3 mol / L, metal filling is completed under the condition of a current density of 50 A / cm², finally forming a conical through-silicon via 8 structure with metal conduction ability and insulating coating characteristics.

[0044] S3. Prepare the redistribution layer 9 on the surfaces of the first silicon wafer 6 and the second silicon wafer 7; use the damascene process to deposit and form the redistribution layer 9 on the upper and lower surfaces of the first silicon wafer 6 and the upper surface of the second silicon wafer 7 in sequence. First, deposit a silicon nitride diffusion barrier layer and a SiO2 dielectric layer on the upper and lower surfaces of the first silicon wafer 6 and the upper surface of the second silicon wafer 7 respectively. Subsequently, perform patterning on the SiO2 dielectric layer, and etch the excess dielectric layer outside the patterned area to form a wiring channel; then deposit a new diffusion barrier layer and a metal seed layer in the etched patterned area, and perform electroplating under the electroplating conditions in step 2, select copper as the material to complete the wiring metal filling; finally, perform chemical mechanical polishing on the surfaces of the first silicon wafer 6 and the second silicon wafer 7 to remove the excess material and obtain a flat-surfaced redistribution layer 9 structure.

[0045] S4. Place multiple die 4 and programmable communication network bare chips 5 on the upper surfaces of the first silicon wafer 6 and the second silicon wafer 7 respectively and bond them firmly; before placement, use the negative marking process to prepare cross-shaped alignment markers on the passive areas of the upper surfaces of the first silicon wafer 6 and the second silicon wafer 7 respectively, with a line length of 140 μm and a line width of 30 μm, for accurately positioning the layout positions of the die 4 and the communication network chips; then mount the die 4 according to the positions of the alignment markers, place 6N die 4 and N programmable communication network bare chips 5 on the designated areas of the upper surfaces of the first silicon wafer 6 and the second silicon wafer 7 respectively, the programmable communication network bare chips 5 are placed in the central position on the upper surface of the first silicon wafer 6, and C5 and C6 are placed on the upper surface of the second silicon wafer 7; after placement, use the thermocompression bonding process to firmly bond all the die 4 and the programmable communication network bare chips 5 to the surfaces of the first silicon wafer 6 and the second silicon wafer 7, and apply epoxy resin in the surrounding areas for reinforcement to prevent displacement or vibration during subsequent packaging.

[0046] S5. Prepare micro-bumps on the lower surface of the first silicon wafer 6 and the upper surface of the second silicon wafer 7, and then bond and fix the first silicon wafer 6 and the second silicon wafer 7; use the ball-planting process to electroplate copper-based micro-bumps on the lower surface of the first silicon wafer 6 and the upper surface of the second silicon wafer 7 respectively, control the electroplating rate to 0.3 μm / min, and the obtained micro-bumps are cylindrical as a whole, for realizing the electrical connection between the first silicon wafer 6 and the second silicon wafer 7; after completing the preparation of the micro-bumps, under the conditions of a bonding pressure of 300 kPa, a bonding temperature of 250 °C, and a temperature rise rate of 5 °C / min, use the thermocompression bonding process to align and firmly connect the first silicon wafer 6 and the second silicon wafer 7 to ensure stable and reliable micro-structure interconnection.

[0047] S6. Perform dicing on the bonded wafers and encapsulate them to obtain a microsystem with a programmable communication network. Use a laser with a power of 2 kW to precisely cut the bonded wafers to obtain N three-dimensional reconstructed microsystem units with communication functions. Each unit contains 6 dielets 4 and 1 programmable communication network bare chip 5. After dicing, integrate the obtained microsystem units on the FR-4 packaging substrate 10 and perform housing encapsulation to finally form a highly integrated multi-dielet microsystem with function reconstruction and communication path self-healing capabilities.

[0048] Before completing the laser cutting of the silicon wafer in the preparation of the programmable communication network bare chip 5 in step 1, to improve the working stability of the programmable communication network bare chip 5, a laser heat treatment operation can be performed on the wiring area of the guiding switch 3 in the signal guiding array 2. This area usually contains multiple metal wires and electrical connection nodes, with a dense structure and complex layout, and is prone to generating microscopic defects in the deposition process and local topography control. By locally heating with a laser with controllable pulse energy before cutting, and irradiating the wiring area of the guiding switch 3 with a laser beam with a wavelength of 532 nm, a pulse width of 60 ns, a pulse energy of 100 μJ, and a spot diameter of 15 μm, it can prompt the metal wires to undergo morphological reorganization at the microscopic level, making the wire edges smoother and the cross-sectional thickness more uniform, thereby reducing the contact impedance fluctuations caused by uneven current density and improving the conduction stability and long-term conduction reliability of the guiding switch 3. On the other hand, the local thermal field change caused by the laser irradiation can also prompt the release of residual stress in the wiring area, avoiding structural cracking or delamination induced by stress concentration in subsequent high-temperature processes or environmental loads, and effectively improving the overall thermal stability and packaging reliability of the microsystem structure. This treatment method is particularly suitable for programmable communication network structures with a high integration density and small wire spacing in the signal guiding array 2, and can enhance the functional stability and environmental adaptability of key areas without changing the original structure layout.

[0049] In step 4, before attaching the die 4 and the programmable communication network bare chip 5 to the surface of the first silicon wafer 6 or the second silicon wafer 7, a filling material can be set between their contact interfaces. The filling material can be a pre-coated thermally conductive epoxy adhesive, a highly thermally conductive silica gel doped with metal oxide particles, or a metal adhesive with a relatively low melting point. It has excellent thermal conductivity and is suitable for the thermocompression bonding process, capable of optimizing the heat conduction path between the die 4 and the programmable communication network bare chip 5 and enhancing the mounting stability. The filling material also has a buffering property, with elastic fillers uniformly dispersed therein and forming a micron-scale pore structure, making it compressible and interface-compliant during the thermocompression welding process. This structure can alleviate the local uneven contact between the die 4, the programmable communication network bare chip 5, and the silicon wafer caused by thickness deviation, surface unevenness, or loading pressure fluctuations, contributing to improving the interface fitting quality and structural stability during the mounting process and reducing the risk of bonding defects. When arranging, the filling material can be applied in a zoned manner as needed, set in the areas with a relatively large thermal load at the bottom of the die 4 and the programmable communication network bare chip 5, rather than covering the entire bottom of the die 4 and the programmable communication network bare chip 5. This can ensure efficient heat conduction in key parts while reducing the material usage and avoiding interference of the filling material with the thermocompression welding process, thereby improving the process consistency and controllability of the thermal management path. According to the sizes and power densities of the dies in actual applications, the thickness of the filling material can be adjusted regionally, with a preferred range of 50 - 200 microns, to achieve a comprehensive balance of thermal conductivity, packaging strength, and fitting accuracy. As a supplement to the thermocompression welding and epoxy resin reinforcement measures, this design helps to improve the thermal control ability and long-term structural stability of the system under high-load operating conditions.

[0050] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A programmable communication network, comprising a control unit and a signal guiding array, characterized in that: The control unit includes an input port and multiple output ports. The output ports are used to output communication path configuration signals. The control unit further includes a path repair port, which is used to receive an external input signal when a communication path fails. The control unit regenerates the communication path configuration signal according to the input signal to achieve self-repair of the communication path. The signal guiding array includes multiple guiding switches, and the guiding switches are connected to the output ports. Multiple die chips are arranged on the peripheral edge of the signal guiding array. The guiding switches establish a programmable selective communication path between the die chips according to the communication path configuration signal.

2. The programmable communication network according to claim 1, wherein: The control unit can output different combinations of the communication path configuration signals to construct a communication path between the die chips corresponding to different system functions.

3. The programmable communication network according to claim 2, wherein: The guiding switch is composed of at least two NMOS transistors and an inverter.

4. The programmable communication network according to claim 3, characterized in that: The types of the guiding switches include single-pole single-throw switches and single-pole double-throw switches.

5. The programmable communication network according to claim 4, characterized in that: In the signal guiding array, the control signal lines adopt a hierarchical wiring method, and decoupling capacitors and pull-up resistors or pull-down resistors are provided.

6. The programmable communication network according to claim 5, wherein: A metal layer is provided in the signal guiding array, and the metal layer is located in the angular region between the control signal line and the transmission signal line of the guiding switch.

7. The programmable communication network according to claim 6, wherein: The signal guiding array supports expansion according to a 1×2 or 2×2 topology structure.

8. A preparation method for fabricating a multi-die microsystem in a programmable communication network, characterized in that: The microsystem includes the programmable communication network described in claim 1. The manufacturing method includes the following steps: S1. Fabricate a bare chip of the programmable communication network. S2. Fabricate through-silicon vias on the first silicon wafer. S3. Fabricate a redistribution layer on the surfaces of the first silicon wafer and the second silicon wafer. S4. Place multiple die chips and the bare chip of the programmable communication network on the upper surfaces of the first silicon wafer and the second silicon wafer respectively, and bond and fix them. S5. Fabricate micro-bumps on the lower surface of the first silicon wafer and the upper surface of the second silicon wafer, and then bond and fix the first silicon wafer and the second silicon wafer. S6. Perform dicing on the bonded wafers and package them to obtain a multi-die microsystem with a programmable communication network.

9. The preparation method of a multi-die microsystem for a programmable communication network according to claim 8, characterized in that: In S1, laser heat treatment is performed on the signal guiding array area.

10. The preparation method of constructing a multi-die micro-system in a programmable communication network according to claim 9, characterized in that: The laser heat treatment uses a laser beam with a wavelength of 532 nm, a pulse width of 60 ns, a pulse energy of 100 μJ, and a spot diameter of 15 μm.

11. The preparation method of a multi-die microsystem for a programmable communication network according to claim 10, characterized in that: In S4, cross-shaped alignment marks are provided on the upper surfaces of the first silicon wafer and the second silicon wafer to assist in the precise positioning and bonding alignment of the die chips and the bare chip of the programmable communication network.

12. The preparation method of the multi-die micro-system for a programmable communication network according to claim 11, wherein: In S4, a filling material is provided between the die chips and the bare chip of the programmable communication network and the first silicon wafer or the second silicon wafer before bonding.

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