Homologous clock structure applied to ultra-high-speed signal acquisition and processing system and configuration method

Abstract

The invention belongs to a clock structure in the field of communication, and relates to a homologous clock structure applied to an ultra-high-speed signal acquisition and processing system and a configuration method, and the homologous clock structure comprises a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel double-loop phase-locked loop, a third-stage high-frequency phase-locked loop and a clock expansion network which are connected in sequence, the clock source is composed of a differential crystal oscillator and an external clock. The first-stage low-jitter clock distribution network consists of two double-path low-jitter clock buffers; the second-stage multi-channel double-loop phase-locked loop is composed of two ultra-low phase noise oscillators and two double-loop phase-locked circuits; the third-stage high-frequency phase-locked loop and clock expansion network consists of two high-frequency phase-locked loops and four 12-path clock buffers; by setting the priority of the clock source, the internal or external clock source can be flexibly selected.

Description

Technical Field

[0001] The present invention belongs to the clock structure in the communication field, and particularly relates to a homologous clock structure and a configuration method applied to an ultra-high-speed signal acquisition and processing system. Background Art

[0002] The ultra-high-speed signal acquisition and processing system mainly includes parts such as ultra-high-speed signal acquisition, sampled data transmission, high-speed data buffering, signal processing, and high-speed bus transmission. To achieve ultra-high-speed signal acquisition and processing, a dedicated clock network needs to be designed to meet the clock requirements of each part of the ultra-high-speed signal acquisition and processing system and achieve clock homology above GHz. The clock network needs to comprehensively consider factors such as clock sources, the number of clock routes, driving capabilities, and clock frequencies. In the case of multiple input clock sources, it is necessary to first set the priority of the clock sources, then use a PLL to multiply the input clock frequency, then generate the frequencies required by each device through a frequency divider, and finally buffer and route them to each device.

[0003] Currently, the ultra-high-speed signal acquisition and processing system is mainly implemented using a large-scale FPGA + ultra-high-speed ADC / DAC + single-level clock distribution chip. However, with the expansion of the system scale, the single-level clock distribution network can no longer meet the requirements of clock frequency and jitter for ultra-high-speed ADC / DAC conversion, nor can it meet the requirements of clock channel quantity and homology involved in the system, such as JESD204B / C reference clock, FPGA global clock, DDR4 working clock, and optical fiber communication, which makes the clock network design of the ultra-high-speed signal acquisition and processing system encounter bottlenecks. Summary of the Invention

[0004] To solve the above problems existing in the prior art, the present invention proposes a homologous clock structure applied to an ultra-high-speed signal acquisition and processing system. This structure includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel double-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock expansion network connected in sequence;

[0005] The clock source consists of a differential crystal oscillator and an external clock, and through the setting of priorities, the selection of the internal clock or the external clock is realized;

[0006] The first-stage low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, and the signal output by the clock source is converted through the dual-channel low-jitter clock buffers;

[0007] The second-stage multi-channel double-loop phase-locked loop consists of two ultra-low phase noise oscillators and two double-loop phase-locked circuits, and is used to process the signal converted by the first-stage low-jitter clock distribution network;

[0008] The third - level high - frequency phase - locked loop and clock expansion network consists of two high - frequency phase - locked loops and four 12 - way clock buffers, and is used to process the signals output by the second - level multi - channel double - loop phase - locked loop;

[0009] A clock network configuration method applied to an ultra - high - speed signal acquisition and processing system, the method includes:

[0010] S101. Power on the system, the FPGA loads the routing program, the MCU loads the configuration code, and sets the maximum number of configuration times;

[0011] S102. Configure the parameters of the double - loop phase - locked circuit 1, and input the signal into the first double - loop phase - locked circuit;

[0012] S103. Detect whether the double - loop phase - locked circuit 1 is locked. If so, execute step S104. If not, determine whether the current configuration times exceed the maximum number of configuration times. If so, the configuration is incorrect, otherwise return to step S102;

[0013] S104. Configure the parameters of the double - loop phase - locked circuit 2, and determine whether the double - loop phase - locked circuit 2 is locked. If not, execute step S105. If so, execute step S106;

[0014] S105. Determine whether the current configuration times are greater than the maximum number of configuration times. If not, return to step S104. If so, the configuration is incorrect;

[0015] S106. Configure the parameters of the high - frequency phase - locked loop 1, and determine whether the high - frequency phase - locked loop 1 is locked. If not, execute step S107. If so, execute step S108;

[0016] S107. Determine whether the current configuration times are greater than the maximum number of configuration times. If not, return to step S106. If so, the configuration is incorrect;

[0017] S108. Configure the parameters of the high - frequency phase - locked loop 2, and determine whether the high - frequency phase - locked loop 2 is locked. If not, execute step S109. If so, execute step S110;

[0018] S109. Determine whether the current configuration times are greater than the maximum number of configuration times. If not, return to step S108. If so, the configuration is incorrect;

[0019] S110. Configure the parameters of the ultra - high - speed DAC1, and detect whether the ultra - high - speed DAC1 has successfully established a link. If not, execute step S111. If so, execute step S112;

[0020] S111. Determine whether the current configuration times are greater than the maximum number of configuration times. If not, return to step S110. If so, the configuration is incorrect;

[0021] S112. Configure the parameters of the ultra-high-speed DAC2 and detect whether the ultra-high-speed DAC2 has successfully established a link. If not, execute step S113; if so, execute step S114;

[0022] S113. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S112; if so, the configuration is incorrect;

[0023] S114. Configure the parameters of the ultra-high-speed ADC1 and detect whether the ultra-high-speed ADC1 has successfully established a link. If not, execute step S115; if so, execute step S116;

[0024] S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114; if so, the configuration is incorrect;

[0025] S116. Configure the parameters of the ultra-high-speed ADC2 and detect whether the ultra-high-speed ADC2 has successfully established a link. If not, execute step S117; if so, the configuration is complete;

[0026] S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116; if so, the configuration is incorrect.

[0027] Advantages of the present invention:

[0028] The present invention realizes the flexible selection of internal and external clocks through the setting of clock source priorities; realizes the expansion of clock sources through 2 1-to-2 low-jitter clock buffers; realizes jitter suppression, frequency multiplication and frequency division through 2 ultra-low phase noise oscillators and 2 14-output dual-loop phase-locked circuits; realizes the generation of 4 high-frequency clocks through 2 high-frequency phase-locked loops; realizes the expansion of end clocks through 4 12-output clock buffers; realizes the stable and reliable configuration of multiple devices such as dual-loop phase-locked loops, high-speed phase-locked loops, ultra-high-speed ADCs, and ultra-high-speed DACs through the configuration process of the same-source clock structure; realizes the routing of 8 control signals to 42 configuration signals through the multi-module configuration routing scheme of MCU+FPGA. This solution solves the requirements of the ultra-high-speed signal acquisition and processing system for multi-channel, high-frequency, and low-jitter complex clocks, making the same-source clock structure based on the present invention not only meet the needs of the ultra-high-speed signal acquisition and processing system, but also meet the application requirements of similar large-scale communication and signal processing systems. Description of the Drawings

[0029] Figure 1 It is a schematic diagram of the same-source clock structure of the present invention;

[0030] Figure 2 It is a schematic diagram of the clock network configuration process of the present invention;

[0031] Figure 3 Schematic diagram of multi-module configuration routing for the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0033] A homologous clock structure applied to an ultra-high-speed signal acquisition and processing system. This structure includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock expansion network connected in sequence. The clock source consists of a differential crystal oscillator and an external clock. By setting priorities, the selection of the internal clock or the external clock is realized. The first-stage low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, which convert the signal output by the clock source through the dual-channel low-jitter clock buffers. The second-stage multi-channel dual-loop phase-locked loop consists of two ultra-low phase-noise oscillators and two dual-loop phase-locked circuits, which are used to process the signal converted by the first-stage low-jitter clock distribution network. The third-stage high-frequency phase-locked loop and the clock expansion network consist of two high-frequency phase-locked loops and four 12-channel clock buffers, which are used to process the signal output by the second-stage multi-channel dual-loop phase-locked loop and provide the required clock signals for devices such as two ultra-high-speed ADCs, two large-scale FPGAs, and two ultra-high-speed DACs in the ultra-high-speed signal acquisition and processing system.

[0034] In this embodiment, as Figure 1 shown, a preferred implementation manner of a homologous clock structure applied to an ultra-high-speed signal acquisition and processing system includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock expansion network.

[0035] The clock source serves as the input of the homologous clock network of the ultra-high-speed signal acquisition and processing system and is composed of a differential crystal oscillator 1 and an external clock 1. The clock frequency is 10 MHz. The differential crystal oscillator 1 is integrated on the PCB, and the external clock 1 is input through an SSMA connector. The output of the differential crystal oscillator uses LVDS level, and the external clock is LVCMOS level. The differential crystal oscillator 1 is used for the board-level clock network to work independently, and the external clock 1 is used to achieve system-level clock homology.

[0036] The first - stage low - jitter clock distribution network consists of a dual - channel low - jitter clock buffer 1 and a dual - channel low - jitter clock buffer 2. The dual - channel low - jitter clock buffer 1 is used to convert a 1 - channel differential crystal oscillator input clock into 2 - channel LVDS output clocks, and the dual - channel low - jitter clock buffer 2 is used to convert a 1 - channel external clock into 2 - channel LVDS output clocks. The maximum input frequency of the dual - channel low - jitter clock buffer can reach 650 MHz, with a jitter ≤ 50 fs. It supports a wide frequency range, introduces little jitter, and effectively realizes the expansion of the clock source.

[0037] The second - stage multi - channel dual - loop phase - locked loop consists of an ultra - low phase - noise oscillator 1, an ultra - low phase - noise oscillator 2, a dual - loop phase - locked circuit 1, and a dual - loop phase - locked circuit 2. The ultra - low phase - noise oscillator 1 provides a stable de - jittered clock for the PLL in the dual - loop phase - locked circuit 1, and cooperates with CPOUT to fine - tune the frequency of the ultra - low phase - noise oscillator 1 to achieve synchronization with the clock source. The ultra - low phase - noise oscillator 2 provides a stable de - jittered clock for the PLL in the dual - loop phase - locked circuit 2, and cooperates with CPOUT to fine - tune the frequency of the ultra - low phase - noise oscillator 2 to achieve synchronization with the clock source. The two input clocks in the dual - loop phase - locked circuit 1 and the dual - loop phase - locked circuit 2 are selected through internal register configuration. CLKIN0 is the internal differential crystal oscillator input, and CLKIN1 is the external clock source input, with both clock frequencies being 10 MHz.

[0038] The connection relationships of each device in the second - stage multi - channel dual - loop phase - locked loop are as follows: The CLKIN0 terminal of the dual - loop phase - locked circuit 1 is connected to the first output terminal of the clock buffer 1 in the first - stage low - jitter clock distribution network, and the CLKIN1 terminal of the dual - loop phase - locked circuit 1 is connected to the first output terminal of the first - stage clock buffer 2; The CPOUT signal of the dual - loop phase - locked circuit 1 is connected to the voltage - controlled terminal of the low - phase - noise oscillator 1, the reference - signal input terminal of the dual - loop phase - locked circuit 1 is connected to the output terminal of the low - phase - noise oscillator 1, and the respective output terminals of the dual - loop phase - locked circuit 1 are connected to the third - stage high - frequency phase - locked loop and the clock expansion network.

[0039] The CLKIN0 terminal of the dual - loop phase - locked circuit 2 is connected to the second output terminal of the clock buffer 1 in the first - stage low - jitter clock distribution network, and the CLKIN1 terminal of the dual - loop phase - locked circuit 2 is connected to the second output terminal of the first - stage clock buffer 2; The CPOUT signal of the dual - loop phase - locked circuit 2 is connected to the voltage - controlled terminal of the low - phase - noise oscillator 2, the reference - signal input terminal of the dual - loop phase - locked circuit 2 is connected to the output terminal of the low - phase - noise oscillator 2, and the respective output terminals of the dual - loop phase - locked circuit 2 are connected to the third - stage high - frequency phase - locked loop and the clock expansion network.

[0040] The dual-loop phase-locked loop circuits 1 and 2 internally contain two-stage phase-locked loops PLL1, PLL2 and a clock frequency division unit. PLL1 realizes debouncing of the input clock, PLL2 realizes the generation of the core clock, and through the configuration of the R and N coefficients, any clock can be output. The clock frequency division unit realizes the routing and frequency division of the PLL2 core clock. Each dual-loop phase-locked loop circuit supports LVDS, LVPECL, and CML level standards, the output clock can reach up to 3.2 GHz, and the typical value of the clock jitter is 44 fs, which can effectively realize the debouncing of the clock.

[0041] The dual-loop phase-locked loop circuit 1 outputs 5 clocks: CLKOUT0, SCLKOUT1, CLKOUT2, SCLKOUT3, SCLKOUT5. CLKOUT0 provides the reference clock for the ultra-high-speed ADC1 and ADC2, and the clock frequency is 10.23 MHz; SCLKOUT1 and SCLKOUT3 provide the SYSREF clock for the JESD204B interfaces of the ultra-high-speed ADC1 and ultra-high-speed ADC2; CLKOUT2 provides the REFCLK clock for the GTY unit in the large-scale FPGA1; SCLKOUT5 provides the SYSREF clock for the JESD204B interface of the large-scale FPGA1.

[0042] The dual-loop phase-locked loop circuit 2 outputs 11 clocks: CLKOUT0, CLKOUT2, CLKOUT4, CLKOUT6, CLKOUT8, CLKOUT10, CLKOUT12, SCLKOUT1, SCLKOUT3, SCLKOUT5, SCLKOUT7. CLKOUT0 provides the global clock for the large-scale FPGA1;

[0043] SCLKOUT1 provides the SYSREF clock for the JESD204B of the large-scale FPGA1; CLKOUT2 provides the DDR4 clock for the large-scale FPGA1; CLKOUT4 provides the REFCLK clock for the GTY unit of the large-scale FPGA1; CLKOUT6 provides the REFCLK clock for the GTY unit of the large-scale FPGA2; CLKOUT8 provides the global clock for the large-scale FPGA2; CLKOUT10 provides the DDR4 clock for the large-scale FPGA2; CLKOUT12 provides the REFCLK clock for the GTY unit of the large-scale FPGA2; SCLKOUT3 is used to provide the SYSREF clock for the JESD204B interface of the ultra-high-speed DAC1, SCLKOUT5 is used to provide the reference clock for the ultra-high-speed DAC1 and DAC2, and the clock frequency is 10 MHz; SCLKOUT7 is used to provide the SYSREF clock for the JESD204B interface of the ultra-high-speed DAC2.

[0044] The third - level high - frequency phase - locked loop and clock expansion network consists of 2 high - frequency phase - locked loops and 4 12 - channel clock buffers, namely: high - frequency phase - locked loop 1, high - frequency phase - locked loop 2, 12 - channel clock buffer 1, 12 - channel clock buffer 2, 12 - channel clock buffer 3, and 12 - channel clock buffer 4. The 2 high - frequency phase - locked loops generate high - frequency clocks, with the output frequency up to 15 GHz and a clock jitter of 45 fs, which is beneficial to improving the performance of ultra - high - speed ADC and DAC data conversion. The 4 12 - channel clock buffers are used for clock expansion. The highest clock frequency of the 12 - channel clock buffer is 1.2 GHz, the jitter is 54 fs, and the difference between channels is 70 ps, which is beneficial to the clock homologous expansion of the ultra - high - speed signal acquisition and processing system, especially for large - scale FPGA circuits that require multiple pairs of homologous clocks.

[0045] The high - frequency phase - locked loop 1 converts the 10.23 MHz reference clock output by the second - level clock network into the sampling clocks of ultra - high - speed ADC1 and ultra - high - speed ADC2. The output frequency is 5.115 GHz, which is used as the sampling clock of ultra - high - speed ADC1 and ultra - high - speed ADC2. The ultra - high - speed ADC uses both the rising and falling edges of the clock for sampling. By inputting a 5.115 GHz sampling clock, an ultra - high - speed sampling of 10.23 GSPS can be achieved. The high - frequency phase - locked loop 2 converts the 10 MHz reference clock output by the second - level clock network into the conversion clocks of ultra - high - speed DAC1 and ultra - high - speed DAC2. The output frequency is 12 GHz, enabling ultra - high - speed data conversion of 12 GSPS.

[0046] The input clock of the 12 - channel clock buffer 1 comes from the 165 MHz clock output by the second - level clock network. Through the clock buffer, 8 channels of 165 MHz are output to the GTY units of large - scale FPGA1 as the reference clocks of the GTY units. The 8 clocks are: 5200A_GTYCLK0, 5200A_GTYCLK1, 5200A_GTYCLK2, 5200A_GTYCLK3, 5200B_GTYCLK0, 5200B_GTYCLK1, 5200B_GTYCLK2, 5200B_GTYCLK3, where

[0047] 5200A_GTYCLK0 to 5200A_GTYCLK3 are provided to the GTY222 to GTY225 units to achieve data transmission between ultra - high - speed ADC1 and large - scale FPGA1. The transmission line rate is 10.23 Gbps.

[0048] 5200B_GTYCLK0 to 5200B_GTYCLK3 are provided to the GTY226 to GTY229 units to achieve data transmission between ultra - high - speed ADC2 and large - scale FPGA1. The transmission line rate is 10.23 Gbps.

[0049] The input clock of the 12-channel clock buffer 2 comes from the 125 MHz output of the second-level clock network. Through the clock buffer, 12 channels of 125 MHz are output to the GTY units of the large-scale FPGA 1 as the reference clock for the GTY units. The 12 clocks are: 9081A_GTYCLK0, 9081A_GTYCLK1, 9081B_GTYCLK0, 9081B_GTYCLK1, A_ETH_GTYCLK, A_OPT_GTYCLK, FPGA1_GTYCLK0, FPGA1_GTYCLK1, FPGA1_GTYCLK2, FPGA1_GTYCLK3, FPGA1_GTYCLK4, FPGA1_GTYCLK5. Among them, 9081A_GTYCLK0 and 9081A_GTYCLK1 are provided to the GTY130 - GTY131 units to achieve data transmission between FPGA 1 and the ultra-high-speed DAC 1, with a transmission rate of 15 Gbps; 9081B_GTYCLK0 and 9081B_GTYCLK1 are provided to the GTY230 - GTY231 units to achieve data transmission between FPGA 1 and the ultra-high-speed DAC 2, with a transmission rate of 15 Gbps; A_ETH_GTYCLK is provided to the GTY132 unit of FPGA 1 to achieve gigabit Ethernet transmission of FPGA 1, with a line rate of 1 Gbps; A_OPT_GTYCLK is provided to the GTY129 module of FPGA 1 to achieve optical fiber communication of FPGA 1, with a line rate of 10 Gbps;

[0050] FPGA1_GTYCLK0 to FPGA1_GTYCLK5 are respectively provided to the GTY125 - GTY128, GTY220, GTY221 units of FPGA 1 to achieve large-bandwidth data transmission between the large-scale FPGA 1 and the large-scale FPGA 2, with a line rate of 15 Gbps.

[0051] The input clock of the 12-channel clock buffer 3 comes from the 125 MHz output of the second-stage clock network. Through the clock buffer, 12 channels of 125 MHz are output to the large-scale FPGA 1 and the large-scale FPGA 2 as the reference clock of the GTY unit. The 12 clocks are respectively: FPGA1_GTYCLK6, FPGA2_GTYCLK0, FPGA2_GTYCLK1, FPGA2_GTYCLK2, FPGA2_GTYCLK3, FPGA2_GTYCLK4, FPGA2_GTYCLK5, FPGA2_GTYCLK6, B_OPT_GTYCLK, B_ETH_GTYCLK. Among them, FPGA1_GTYCLK6 is provided to the GTY124 unit of FPGA1 to achieve high-bandwidth data transmission with FPGA1, and the transmission line rate is 15 Gbps; FPGA2_GTYCLK0 to FPGA2_GTYCLK6 are provided to the GTY225 to GTY231 units of FPGA2 to achieve high-bandwidth data transmission with FPGA2, and the transmission line rate is 15 Gbps. B_OPT_GTYCLK is provided to the GTY131 unit of FPGA2 to achieve fiber-optic transmission of FPGA2, and the transmission line rate is 10 Gbps. B_ETH_GTYCLK is provided to the GTY130 unit of FPGA2 to achieve gigabit Ethernet transmission of FPGA2, and the line rate is 1 Gbps.

[0052] The input clock of the 10-channel clock buffer 4 comes from the output of the second-stage clock network and is used for the communication between FPGA2 and the FMC1 and FMC2 daughter cards. The clock frequency can be adjusted according to the requirements of the actually connected FMC daughter card. The 10 clocks output through the clock buffer are respectively: FMC1_GTYCLK0 to FMC1_GTYCLK3, FMC2_GTYCLK0 to FMC2_GTYCLK3, FMC1_EXTCLK, FMC2_EXTCLK. Among them, FMC1_GTYCLK0 to FMC1_GTYCLK3 are connected to the GTY119, GTY120, GTY125, and GTY126 units of FPGA2 to provide the GTY reference clock and achieve high-speed communication between the FMC1 daughter card and FPGA2; FMC2_GTYCLK0 to FMC2_GTYCLK3 are connected to the GTY121, GTY123, GTY122, and GTY124 units of the large-scale FPGA2 to provide the GTY reference clock and achieve high-speed communication between the FMC2 daughter card and FPGA2; FMC1_EXTCLK provides the same-source clock for the FMC1 daughter card, and FMC2_EXTCLK provides the same-source clock for the FMC2 daughter card.

[0053] In this embodiment, a clock network configuration method applied to an ultra-high-speed signal acquisition and processing system is as Figure 2As shown, the method includes:

[0054] S101. Power on the system, load the routing program in the FPGA, load the configuration code in the MCU, and set the maximum number of configurations;

[0055] S102. Configure the parameters of the dual-loop phase-locked circuit 1 and input the signal into the first dual-loop phase-locked circuit;

[0056] S103. Detect whether the dual-loop phase-locked circuit 1 is locked. If it is, execute step S104. If not, determine whether the current number of configurations exceeds the maximum number of configurations. If it does, the configuration is incorrect. Otherwise, return to step S102;

[0057] S104. Configure the parameters of the dual-loop phase-locked circuit 2 and determine whether the dual-loop phase-locked circuit 2 is locked. If not, execute step S105. If it is, execute step S106;

[0058] S105. Determine whether the current number of configurations is greater than the maximum number of configurations. If not, return to step S104. If it is, the configuration is incorrect;

[0059] S106. Configure the parameters of the high-frequency phase-locked loop 1 and determine whether the high-frequency phase-locked loop 1 is locked. If not, execute step S107. If it is, execute step S108;

[0060] S107. Determine whether the current number of configurations is greater than the maximum number of configurations. If not, return to step S106. If it is, the configuration is incorrect;

[0061] S108. Configure the parameters of the high-frequency phase-locked loop 2 and determine whether the high-frequency phase-locked loop 2 is locked. If not, execute step S109. If it is, execute step S110;

[0062] S109. Determine whether the current number of configurations is greater than the maximum number of configurations. If not, return to step S108. If it is, the configuration is incorrect;

[0063] S110. Configure the parameters of the ultra-high-speed DAC1 and detect whether the ultra-high-speed DAC1 has successfully established a link. If not, execute step S111. If it is, execute step S112;

[0064] S111. Determine whether the current number of configurations is greater than the maximum number of configurations. If not, return to step S110. If it is, the configuration is incorrect;

[0065] S112. Configure the parameters of the ultra-high-speed DAC2 and detect whether the ultra-high-speed DAC2 has successfully established a link. If not, execute step S113. If it is, execute step S114;

[0066] S113. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S112. If so, it is a configuration error.

[0067] S114. Configure the parameters of the ultra-high-speed ADC1 and detect whether the ultra-high-speed ADC1 has successfully established a link. If not, execute step S115. If so, execute step S116.

[0068] S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114. If so, it is a configuration error.

[0069] S116. Configure the parameters of the ultra-high-speed ADC2 and detect whether the ultra-high-speed ADC2 has successfully established a link. If not, execute step S117. If so, the configuration is completed.

[0070] S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116. If so, it is a configuration error.

[0071] Specifically, after the ultra-high-speed signal acquisition and processing system is powered on, the FPGA loads the routing program from the configuration Flash, and at the same time the MCU loads the configuration code. Subsequently, the configuration parameters of the double-loop phase-locked circuit 1 are sent to complete the configuration of the internal PLL1 and PLL2 of the phase-locked circuit 1, and the division factor of the output path of the phase-locked circuit 1 is sent to complete the configuration of the SCLKOUT1, CLKOUT0, SCLKOUT3, CLKOUT2, SCLKOUT5 channels. The MCU detects the lock signal output by the phase-locked circuit 1 through the GPIO port. If the lock is not completed, it will check whether the configuration count of the phase-locked circuit 1 has been exceeded. If the configuration count has not been exceeded, the configuration is executed again and the configuration counter is incremented by 1. If the configuration count has been exceeded, the configuration is stopped and the fault code 1 is reported. When the double-loop phase-locked circuit 1 is locked, the configuration counter is cleared, and the configuration of the double-loop phase-locked circuit 2 is continued. The configuration parameters of the internal PLL1, PLL2 and output channels of the phase-locked circuit 2 are sent to complete the configuration of the CLKOUT0, SCLKOUT1, CLKOUT2, CLKOUT4, CLKOUT6, CLKOUT8, CLKOUT10, CLKOUT12, SCLKOUT3, SCLKOUT5, SCLKOUT7 channels. The MCU detects the lock signal output by the phase-locked circuit 2 through the GPIO port. If the configuration is not completed and the configuration count has not been exceeded, the configuration is executed again and the configuration counter is incremented by 1. When the configuration count has been exceeded, the configuration is stopped and the fault code 2 is reported.

[0072] In this embodiment, when the dual-loop phase-locked circuit 2 completes locking, the configuration counter is cleared, and the configuration of the high-frequency phase-locked loop 1 starts. The MCU determines whether the locking is completed by reading the configuration register of the high-frequency phase-locked loop 1. If the locking is not completed and the configuration times have not been exceeded, the high-frequency phase-locked loop 1 is configured again, and the configuration counter is incremented by 1. When the configuration times are exceeded, the configuration is stopped and the fault code 3 is reported. When the high-frequency phase-locked loop 1 completes locking, the configuration counter is cleared, and the configuration of the high-frequency phase-locked loop 2 starts. The MCU determines whether the locking is completed by reading the configuration register of the high-frequency phase-locked loop 2. If the locking is not completed and the configuration times have not been exceeded, the high-frequency phase-locked loop 2 is configured again, and the configuration counter is incremented by 1. When the configuration times are exceeded, the configuration is stopped and the fault code 4 is reported.

[0073] In this embodiment, when the high-frequency phase-locked loop 2 completes locking, the configuration counter is cleared, and the MCU starts to configure the internal clock of the ultra-high-speed DAC1, the JESD204B interface, and the signal link parameters. The MCU determines whether the link between the DAC1 and the FPGA is successfully established by detecting the SYNCOUTB1 signal. If the link is not successfully established and the configuration times have not been exceeded, the DAC1 configuration parameters are sent again, and the configuration counter is incremented by 1. If the configuration times are exceeded, the configuration is stopped and the fault code 5 is reported. If the link between the DAC1 and the FPGA is successfully established, the configuration counter is cleared, and the MCU configures the internal clock of the ultra-high-speed DAC2, the JESD204B interface, and the signal link parameters. The MCU determines whether the link between the DAC2 and the FPGA is successfully established by detecting the SYNCOUTB2 signal. If the link is not successfully established and the configuration times have not been exceeded, the DAC2 configuration parameters are sent again, and the configuration counter is incremented by 1. If the configuration times are exceeded, the configuration is stopped and the fault code 6 is reported.

[0074] In this embodiment, when the link establishment of DAC2 is successful, the MCU clears the configuration counter and starts to configure the ultra-high-speed ADC1 to configure the JESD204B interface clock and signal link parameters. The MCU determines whether the link establishment between the ultra-high-speed ADC1 and the FPGA is successful by detecting the SYNCSE1 signal. If the link establishment is not successful and the configuration times have not exceeded, the MCU sends the ultra-high-speed ADC1 configuration parameters again and increments the configuration counter by 1. If the configuration times exceed, the MCU stops the configuration and reports the fault code 7. If the link establishment of the ultra-high-speed ADC1 is successful, the MCU clears the configuration counter and starts to configure the ultra-high-speed ADC2 to configure the JESD204B interface clock and signal link parameters. The MCU determines whether the link establishment between the ultra-high-speed ADC2 and the FPGA is successful by detecting the SYNCSE2 signal. If the link establishment is not successful and the configuration times have not exceeded, the MCU sends the ultra-high-speed ADC2 configuration parameters again and increments the configuration counter by 1. If the configuration times exceed, the MCU stops the configuration and reports the fault code 8. When ADC2 detects the successful link establishment, the configuration of the entire system is completed. The MCU sends a configuration completion signal to the FPGA, and the internal algorithm logic of the FPGA starts to run.

[0075] The working mode of the multi-module configuration routing in the above clock structure is described below: In this embodiment, a schematic diagram of the multi-module configuration routing applied to the ultra-high-speed signal acquisition clock structure is as Figure 3 shown, and the specific implementation method is as follows:

[0076] 1) The MCU is used as the main control device to transmit the configuration information of each module through 8 GPIO ports. Specifically, GPIO0 to GPIO3 are used as chip select signals to select the modules to be configured. GPIO4 is used as the clock signal to provide the serial clock of the module to be configured. GPIO5 is used as the data output to provide the serial data of the module to be configured. GPIO6 is used as the data input to receive the feedback parameters of the module to be configured. GPIO7 is used as the control signal to provide additional control information to the module to be configured.

[0077] 2) The FPGA is used as the routing device for multi-module configuration, integrating routing logic internally to route the GPIO signals from the MCU to the subsequent configuration modules. In the way of GPIO time-division multiplexing, 8 GPIO control signals are converted into 42 configuration signals. Specifically, it includes 5 MUX units: CS_MUX, CLK_MUX, SDO_MUX, SDI_MUX, CTL_MUX.

[0078] 3) The CS_MUX realizes the combination and routing of 4 GPIOs. GPIO0 - GPIO3 are combined into a 4-bit chip select encoding, and the corresponding chip select functions are as follows: Encoding 1 corresponds to the 7044A_SLEN signal, realizing the chip select of the dual-loop phase-locked circuit 1; Encoding 2 corresponds to the 7044B_SLEN signal, realizing the chip select of the dual-loop phase-locked circuit 2; Encoding 3 corresponds to the 2594A_CSB signal, realizing the chip select of the high-frequency phase-locked loop 1; Encoding 4 corresponds to the 2594B_CSB signal, realizing the chip select of the high-frequency phase-locked loop 2; Encoding 5 corresponds to the 9081A_CSB signal, realizing the chip select of the ultra-high-speed DAC1; Encoding 6 corresponds to the 9081B_CSB signal, realizing the chip select of the ultra-high-speed DAC2; Encoding 7 corresponds to the 5200A_SCSn signal, realizing the chip select of the ultra-high-speed ADC1; Encoding 8 corresponds to the 5200B_SCSn signal, realizing the chip select of the ultra-high-speed ADC2. Encoding 9 enables the link establishment signal of the ultra-high-speed ADC1, corresponding to the detection of SYNCSE1; Encoding 10 enables the link establishment signal of the ultra-high-speed ADC2, corresponding to the detection of SYNCSE2; Encoding 11 enables the link establishment signal of the ultra-high-speed DAC1, corresponding to the detection of SYNCOUTB1; Encoding 12 enables the link establishment signal of the ultra-high-speed DAC2, corresponding to the detection of SYNCOUTB2; Encoding 15 indicates the completion of configuration.

[0079] 4) The CLK_MUX unit realizes the routing of the clock, routing the GPIO4 signal to the clock inputs of 8 configuration modules: 7044A_CLK, 7044B_CLK, 2594A_SCK, 2594B_SCK, 9081A_SCLK, 9081B_SCLK, 5200A_SCLK, 5200B_SCLK. The routing selection is determined by the CS_MUX encoding. When the CS_MUX selects a certain configuration module, the GPIO4 is routed to the clock channel of that module.

[0080] 5) The SDO_MUX realizes the routing of the output configuration data, corresponding to the data inputs of 8 configuration modules: 7044A_SDATA, 7044B_SDATA, 2594A_SDI, 2594B_SDI, 9081A_SDIO, 9081B_SDIO, 5200A_SDI, 5200B_SDI. The routing selection is determined by the CS_MUX encoding. When the CS_MUX selects a certain configuration module, the GPIO5 is routed to the input data channel of that module.

[0081] 6) The SDI_MUX implements the routing of input data for receiving status information, corresponding to the configuration signals of 8 modules: 7044A_LOCK, 7044B_LOCK, 2594A_MUXout, 2594B_MUXout, 9081A_SDO, 9081B_SDO, 5200A_SDO, 5200B_SDO, and 4 link - building signals inside the FPGA: SYNCSE1, SYNCSE2, SYNCOUTB1, SYNCOUTB2. The routing selection is determined by the CS_MUX encoding. When CS_MUX selects a certain configuration module, GPIO6 is routed to the status information output channel of that module.

[0082] 7) The CTL_MUX unit implements the routing of control signals for expanding additional control signals: 7044A_RESET, 7044B_RESET, 9081A_RESETB, 9081B_RESETB, 5200A_PD, 5200B_PD. The expanded control signals can achieve the reset and restart of the configuration module. The routing selection is determined by the CS_MUX encoding. When CS_MUX selects a certain configuration module, GPIO7 is routed to the control signal channel of that module.

[0083] By adopting this synchronous clock network structure, not only can the clock management function of the multi - channel ultra - high - speed signal acquisition and processing system be realized, but also the clock management requirements of most communication systems and signal processing systems can be covered.

[0084] The homogenous clock structure of the present invention applied to the ultra - high - speed signal acquisition and processing system provides a complete clock solution for the ultra - high - speed signal acquisition and processing system. Adopting a three - level clock network structure, it realizes the homogenous source of 54 clocks. Using the MCU, the configuration of multiple double - loop phase - locked loops, high - speed phase - locked loops, ultra - high - speed ADCs, and ultra - high - speed DACs is realized. Using the FPGA to execute the routing and bridging of multiple configuration interfaces, it realizes the routing and expansion of 8 control signals to 42 configuration signals.

[0085] The features of the present invention are as follows: By setting the clock source priority, the internal or external clock source can be flexibly selected; By using the double - loop phase - locked loop + high - frequency phase - locked loop + multi - path clock buffer structure, the requirements of the ultra - high - speed signal acquisition and processing system for multi - channel, high - frequency, and low - jitter complex clocks are solved; By performing closed - loop detection on the configuration results and adding a redundant configuration mechanism, the stable and reliable configuration of multiple devices is realized, ensuring the reliability of the system clock network; By routing and bridging the configuration interfaces, simplifying the complexity, and using a small number of control signals and logics, the unified configuration of the ultra - high - speed signal acquisition and processing system is realized.

[0086] The above-described embodiments have further elaborated in detail the objectives, technical solutions, and advantages of the present invention. It should be understood that the above-described embodiments are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made to the present invention within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A homologous clock structure applied to an ultra-high-speed signal acquisition and processing system, characterized in that, It includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock expansion network connected in sequence; The clock source consists of a differential crystal oscillator and an external clock. By setting the priority, the selection of the internal clock or the external clock can be realized; The first-stage low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, which convert the signal output by the clock source through the dual-channel low-jitter clock buffers; The second-stage multi-channel dual-loop phase-locked loop consists of two ultra-low phase-noise oscillators and two dual-loop phase-locked circuits, and is used to process the signal converted by the first-stage low-jitter clock distribution network; The third-stage high-frequency phase-locked loop and the clock expansion network consist of two high-frequency phase-locked loops and four 12-channel clock buffers, and are used to multiply and expand the signal output by the second-stage multi-channel dual-loop phase-locked loop; The expanded clock network is used to drive two ultra-high-speed ADCs, two large-scale FPGAs, two ultra-high-speed DACs, and two FMC interfaces.

2. The homologous clock structure applied to the ultra-high speed signal acquisition and processing system according to claim 1, characterized in that, The clock frequency of the clock source is 10 MHz; the differential crystal oscillator is integrated on the PCB board and outputs LVDS level; the external clock is input through an SSMA connector and is LVCMOS level.

3. The same-source clock structure applied to the ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that, The output frequency of the dual-channel low-jitter clock buffer can reach 650 MHz, and the jitter ≤ 50 fs.

4. The same-source clock structure applied to the ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that The connection relationships of the devices in the second-stage multi-channel dual-loop phase-locked loop include: the two input ends of the dual-loop phase-locked circuit 1 and the dual-loop phase-locked circuit 2 are respectively connected to the output end of the first-stage low-jitter clock distribution network; the CPOUT signal and the reference signal input end of the dual-loop phase-locked circuit 1 are connected to the ultra-low phase-noise oscillator 1; the CPOUT signal and the reference signal input end of the dual-loop phase-locked circuit 2 are connected to the ultra-low phase-noise oscillator 2; the output ends of the dual-loop phase-locked circuit 1 and the dual-loop phase-locked circuit 2 are respectively connected to the third-stage high-frequency phase-locked loop and the clock expansion network.

5. The same-source clock structure applied to a ultra-high speed signal acquisition and processing system according to claim 4, characterized in that The dual-loop phase-locked circuit 1 includes two-stage phase-locked loops PLL1, PLL2 and a clock frequency division unit; PLL1 realizes debouncing of the input clock, PLL2 realizes the generation of the core clock, and the clock frequency division unit realizes the routing and frequency division of the core clock of PLL2; the dual-loop phase-locked circuit 2 has a similar structure to the dual-loop phase-locked circuit 1.

6. The homologous clock structure applied to the ultra-high speed signal acquisition and processing system according to claim 1, wherein The connection relationships of the devices in the third-stage high-frequency phase-locked loop and the clock expansion network include: The input end of the high-frequency phase-locked loop 1 is connected to the output end of the dual-loop phase-locked circuit 1 of the second stage, and the two output ends of the high-frequency phase-locked loop 1 are respectively connected to the clock input ends of the ultra-high-speed ADC1 and the ultra-high-speed ADC2; The input end of the 12-channel clock buffer 1 is connected to the SCLKOUT1 output end of the second-stage dual-loop phase-locked circuit 1, and the output end of the 12-channel clock buffer 1 is connected to the GTY input end of the large-scale FPGA1; The input ends of the 12-channel clock buffer 2, the 12-channel clock buffer 3, the 12-channel clock buffer 4, and the high-frequency phase-locked loop 2 are all connected to the output end of the second-stage dual-loop phase-locked circuit 2; all the output ends of the 12-channel clock buffer 2 are connected to the GTY input ends of the large-scale FPGA 1; the respective ends of the 12-channel clock buffer 3 are sequentially connected to the GTY input ends of the large-scale FPGA 1 and the GTY input ends of the large-scale FPGA 2; the output ends of the 12-channel clock buffer 4 are sequentially connected to the input ends of the large-scale FPGA 2, the FMC interface 1, and the FMC interface 2; the two output ends of the high-frequency phase-locked loop 2 are respectively connected to the clock input ends of the ultra-high-speed DAC 1 and the ultra-high-speed DAC 2.

7. The homologous clock structure applied to the ultra-high speed signal acquisition and processing system according to claim 6, wherein The 12-channel clock buffer is used for clock expansion, with a maximum clock frequency of 1.2 GHz, a jitter of 54 fs, and a difference between channels of 70 ps.

8. A clock network configuration method applied to an ultra-high-speed signal acquisition and processing system, which is used to configure the homologous clock structure described in any one of claims 1 to 7, characterized in that, Including: S101. Power on the system, the FPGA loads the routing program, the MCU loads the configuration code, and sets the maximum number of configuration times; S102. Configure the parameters of the dual-loop phase-locked circuit 1 and input the signal into the first dual-loop phase-locked circuit; S103. Detect whether the dual-loop phase-locked circuit 1 is locked. If so, execute step S104. If not, determine whether the current number of configuration times exceeds the maximum number of configuration times. If so, the configuration is incorrect. Otherwise, return to step S102; S104. Configure the parameters of the dual-loop phase-locked circuit 2 and determine whether the dual-loop phase-locked circuit 2 is locked. If not, execute step S105. If so, execute step S106; S105. Determine whether the current number of configuration times is greater than the maximum number of configuration times. If not, return to step S104. If so, the configuration is incorrect; S106. Configure the parameters of the high-frequency phase-locked loop 1 and determine whether the high-frequency phase-locked loop 1 is locked. If not, execute step S107. If so, execute step S108; S107. Determine whether the current number of configuration times is greater than the maximum number of configuration times. If not, return to step S106. If so, the configuration is incorrect; S108. Configure the parameters of the high-frequency phase-locked loop 2 and determine whether the high-frequency phase-locked loop 2 is locked. If not, execute step S109. If so, execute step S110; S109. Determine whether the current number of configuration times is greater than the maximum number of configuration times. If not, return to step S108. If so, the configuration is incorrect; S110. Configure the parameters of the ultra-high-speed DAC 1 and detect whether the ultra-high-speed DAC 1 has successfully established a link. If not, execute step S111. If so, execute step S112; S111. Determine whether the current number of configuration times is greater than the maximum number of configuration times. If not, return to step S110. If so, the configuration is incorrect; S112. Configure the parameters of the ultra-high-speed DAC 2 and detect whether the ultra-high-speed DAC 2 has successfully established a link. If not, execute step S113. If so, execute step S114; S113. Determine whether the current number of configuration times is greater than the maximum number of configuration times. If not, return to step S112. If so, the configuration is incorrect; S114. Configure the parameters of the ultra-high-speed ADC1, and detect whether the ultra-high-speed ADC1 has successfully established a link. If not, execute step S115; if so, execute step S116; S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114; if so, the configuration is incorrect; S116. Configure the parameters of the ultra-high-speed ADC2, and detect whether the ultra-high-speed ADC2 has successfully established a link. If not, execute step S117; if so, the configuration is completed; S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116; if so, the configuration is incorrect.

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