Digital calibration method for SAR ADC

Abstract

The invention requests to protect a digital calibration method for an ADC (Analog to Digital Converter). The SAR ADC calibration circuit is mainly composed of a 16bit 1Ms / s SAR ADC circuit model and a calibration circuit model. A string of digital codes is input to the CDAC circuit by utilizing the calibration circuit, a capacitor mismatch value of the CDAC is obtained by utilizing switching of code words, the mismatch value is returned to the calibration circuit, and each bit weight of an output binary code of the ADC is recalibrated. The fast Fourier transform (FFT) is carried out on the output result of the ADC to obtain a correlation result spectrogram before and after the method, and the correlation result is evaluated. According to the calibration algorithm, the significant digits of the SAR ADC can be effectively improved, and compared with an analog calibration circuit, the digital calibration circuit is smaller in area.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a digital front-end calibration technology for SAR ADCs. Background Art

[0002] A successive approximation analog-to-digital converter (SAR ADC) is an analog-to-digital converter with medium speed and accuracy. Facing different application scenarios, it has different requirements for speed, power consumption, and accuracy. For high-precision SAR ADCs, capacitor mismatch caused by process errors is the primary problem limiting the circuit accuracy. To achieve high-precision SAR ADCs, a calibration module is an essential part. The calibration module can correct the mismatch errors generated during the manufacturing process of capacitors. According to different implementation methods, there are two types: analog calibration and digital calibration. Analog calibration uses additional analog circuits to compensate the output voltage of the capacitor DAC in real time to offset the error voltage caused by bit capacitor mismatch. The greatest advantage of analog calibration is that there is no complex digital circuit, which makes the chip design process simpler and less difficult. However, the disadvantages are also obvious. The additional calibration DAC brings a larger area. Digital calibration is to further approximate the obtained quantization value to the ideal value in the digital domain through digital algorithms, that is, to compensate for the mismatch of the SAR ADC to eliminate their impact on the ADC accuracy.

[0003] After retrieval, the prior art CN202110790055.7, a successive approximation analog-to-digital converter with digital calibration, relates to the field of analog-to-digital converter calibration. The invention is based on a digital calibration technology of a probability model. After the successive approximation control logic circuit issues a termination quantization signal, the comparator is triggered an additional M times. After the digital calibration circuit analyzes the output results of the comparator M times based on the probability model, it outputs an estimated voltage margin. The sum of the DAC digital output and the estimated voltage margin is the final output. The following deficiencies exist:

[0004] (1) It requires an additional comparison period and has more requirements for the speed of the comparator;

[0005] (2) It requires an additional comparison period, requires a faster circuit sampling time, and requires a larger switch area. Summary of the Invention

[0006] The present invention aims to solve the above problems of the prior art. A digital calibration method for SAR ADCs is proposed. The technical solution of the present invention is as follows:

[0007] A digital calibration method for SAR ADCs, which includes the following steps:

[0008] a) The calibration module reads the capacitance mismatch error amount of the capacitive digital-to-analog converter (CDAC) in the successive approximation analog-to-digital converter (SAR ADC). The calibration module consists of a data generator, a weight calibration circuit, and an output calibration circuit;

[0009] b) Perform a correlation operation on the read capacitance mismatch error amount and the ideal bit weight to extract the correlation result between the error amount and the weight. The ideal bit weight is where VFS is the full-scale voltage of the SAR ADC;

[0010] c) Send the correlation result into the output calibration circuit, and weight it with the binary code output by the ADC to achieve calibration of the output bit weight.

[0011] Furthermore, in step a), the CDAC circuit of the capacitive digital-to-analog converter consists of two symmetric capacitor arrays, A and B. Among them, the capacitor array A is connected to the non-inverting terminal of the comparator, and the capacitor array B is connected to the inverting terminal of the comparator. By measuring the error voltage of the capacitors with the same weight bits in group A and group B, the total capacitance mismatch value of this bit is calculated.

[0012] Furthermore, in step a), by multiplexing part of the ADC circuit, the CDAC and the comparator circuit in the ADC are multiplexed, and the error voltage is generated and measured for the capacitors with the same bit in group A and group B of the capacitive digital-to-analog converter CDAC respectively. Each time, only one-sided capacitors are switched, and the state of the other end capacitors is kept as 1, so as to obtain the one-sided capacitance mismatch error amount.

[0013] Furthermore, the step of measuring the error voltage includes:

[0014] a) The data generator generates a specific digital code and inputs it to the capacitor array A, and only the capacitor to be measured inputs the digital code 1, and the other capacitors input the code 0;

[0015] b) The capacitors with the corresponding weight bits in group B and all the capacitors below input the digital code 1;

[0016] c) After switching the state, the capacitor to be measured in group A inputs the digital code 0, and the other capacitors input the code 1, and the state of the capacitors in group B remains unchanged;

[0017] d) Use the comparator to quantify the generated difference voltage to form a digital code for subsequent calibration.

[0018] Furthermore, the error of the i-th capacitor in the CDAC can be expressed as: ΔV i = ΔV A,i + ΔV B,i , the error of the i-th capacitor will cause a change in the output weight of the i-th bit of the ADC. ΔV A,i , ΔV B,iRespectively represent the error voltage of the i-th capacitor on the A side and the error voltage of the i-th capacitor on the B side

[0019] Furthermore, the weight calibration process includes: using W i To represent the weight value of the ADC's i-th output, ideally, the weight W of the ADC's i-th output i The value of should be exact binary, i.e. V FS is the full-scale voltage of the SAR ADC; after calibration, the weight W of the ADC’s i-th bit output i The value of The weight W of the i-1th output i-1 The value of The weight W of the i-2th output i-2 The value of And so on; the overall output of the ADC Wherein, Din is the ADC output before ADC calibration, and Dout is the ADC output after calibration.

[0020] The advantages and beneficial effects of the present invention are as follows:

[0021] 1. A new fully differential capacitor mismatch error self-measurement technology is designed. The capacitor mismatch measurement method used in traditional calibration technology requires an additional DAC to implement. This paper uses a method of measuring the two ends separately and then performing superposition calculations. Not only does it not require an additional DAC, but it can also offset the comparator static offset voltage in the calculation, making the measurement result independent of the comparator static offset.

[0022] 2. A new capacitor mismatch digital calibration technology is designed. The LMS-based iterative algorithm requires a long convergence time. The digital calibration technology of the present invention only requires simple calculations in the process of calculating and calibrating the bit weight after the mismatch error measurement, which can be completed in one go, thus avoiding the disadvantage of the long convergence time of the mainstream digital calibration technology based on the LMS algorithm.

[0023] Beneficial effects:

[0024] 1. The present invention can accurately measure the error of CDAC capacitance, thereby improving the calibration accuracy. The output of ADC is calibrated through corresponding weighted calculation, so that SAR ADC can still maintain good conversion performance when there is capacitance mismatch.

[0025] 2. Short calibration time: The present invention does not need to go through a large number of conversions for LMS iterative convergence, and completes the calibration of weights at one time, and does not need to be calibrated again afterwards, thus reducing the calibration time.

[0026] 3. This digital calibration technology does not require too many special requirements for circuit design, and almost all fully differential SAR ADCs can be adapted for use. Description of the Drawings

[0027] Figure 1 It is a calibration schematic diagram adopted by the calibration method of the preferred embodiment provided by the present invention;

[0028] Figure 2 It is a CDAC schematic diagram provided by an embodiment of the present invention;

[0029] Figure 3 It is the process of measuring the unilateral error provided by an embodiment of the present invention;

[0030] Figure 4 It is the process of measuring the unilateral error provided by an embodiment of the present invention;

[0031] Figure 5 It is the process of measuring the unilateral error provided by an embodiment of the present invention;

[0032] Figure 6 It is the specific process of error measurement provided by an embodiment of the present invention;

[0033] Figure 7 It is the ADC simulation result before calibration provided by an embodiment of the present invention;

[0034] Figure 8 It is the ADC simulation result after calibration provided by an embodiment of the present invention. Detailed Embodiment

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and detailedly described in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention.

[0036] The technical solution of the present invention to solve the above technical problems is:

[0037] A calibration method for a SAR ADC, which includes the following steps:

[0038] S1: The calibration module reads the error amount of the CDAC in the SAR ADC;

[0039] S2: Perform a correlation operation on the error amount read in S1 with the ideal bit weight, and extract the correlation result;

[0040] S3: Send the correlation result generated in S2 into the iterative network, and perform weighting with the output of the ADC to achieve calibration.

[0041] In step S1, by mainly multiplexing a part of the ADC circuit, the error voltage generation and measurement are respectively performed on the same-bit capacitors of group A and group B. During each error voltage generation process, only the unilateral capacitor is switched, and the state of the other capacitor is kept unchanged at 1, so as to obtain the unilateral error amount ΔV.

[0042] Further, the CDAC circuit consists of a group A capacitor array and a group B capacitor array. The CDAC in this example is as shown in Figure 2 , and the capacitance value of the i-th bit can be expressed as C i = 2 i-1 C, where C is the unit capacitance. The more unit capacitances it contains, the greater the weight of the bit capacitance. First, it is necessary to convert the mismatch of the bit capacitance into an error voltage that can be measured. Under ideal matching, the bit capacitance should be equal to the sum of all capacitances with lower bits than it. Assume that 1 represents the lower plate of the capacitance connected to V ref , and 0 represents connected to GND. When the CDAC switches from the Figure 3 state to the Figure 4 state, when the bit capacitance state changes between 011…1 and 100…0, the voltage at the input of the comparator should remain unchanged. Conversely, if there is a capacitance mismatch, a difference ΔV will be generated.

[0043] When measuring the error voltage of the i-th bit capacitance, the digital code 100...0 generated by the digital circuit is input into the group A capacitor array, and the digital code 111...1 is input into the group B capacitor array. According to the comparator result, the digital code is sequentially changed from the high-weight capacitance to the low-weight capacitance until the digital code change of the first group is completed. Repeat the above process until the error measurement of group A and group B is completed.

[0044] Further, the error amount of the i-th group of capacitors in the CDAC is composed of the errors of the error amounts of group A and group B, expressed as: ΔV i = ΔV A,i + ΔV B,i .

[0045] Further, the weight calibration has the following process: Use W i to represent the weight value of the output of the i-th bit of the ADC. Under ideal conditions, the weight W i value of the output of the i-th bit of the ADC should be an accurate binary number, that is V FS is the full-scale voltage of the SAR ADC. After calibration, the weight W i value of the output of the i-th bit of the ADC is The weight W i-1 value of the output of the (i - 1)-th bit is The weight W i-2 value of the output of the (i - 2)-th bit is And so on. The overall output of the ADC Among them, Din is the output digital code of the ADC before calibration, and Dout is the output digital code after calibration.

[0046] The present invention is a digital foreground calibration technology, which uses the SAR ADC's own circuit to complete the measurement of mismatch errors, does not add additional analog circuit modules, completes the calibration of weights at one time, does not add additional calibration cycles, and therefore has no additional requirements for comparator performance. Unlike the traditional LMS iterative convergence calibration method, the present invention does not require a large amount of calculations, and the digital calibration part only involves simple addition, subtraction and shift operations, which shortens the calculation time and simplifies the digital circuit. Since it is a foreground calibration, no external input signal is required during calibration.

[0047] First, the capacitance mismatch measurement method does not require additional circuit assistance and is a self-measurement technology. By multiplexing the ADC part circuit, the error voltage is generated and measured once for the same capacitor of group A and group B, and the mismatch of the capacitor is converted into an error voltage that can be measured. During each error voltage generation process, only the single-side capacitor is switched, and the state of the other end capacitor is kept unchanged at 1, thereby obtaining the single-side error ΔV.

[0048] In this example, the CDAC Figure 2 As shown, the capacitance value of the i-th position can be expressed as C i =2 i-1 C, where C is the unit capacitance. The more unit capacitances it contains, the greater the weight of the bit capacitance.

[0049] The measurement error includes two steps: measurement and quantification. Figure 3 As shown in the figure, when the capacitance error of group A is to be measured, the data generator generates the digital code 000000100000000 and inputs it into the capacitance array of group A. Only the capacitance to be measured (group 9) inputs the digital code 1, and the capacitance below the weight of this group (group 8 to group 1) inputs the digital code 0. The digital code 000000111111111 generated by the digital circuit is input into the capacitance array of group B. The corresponding weight of group B (group 9) and the capacitance below the weight (group 8 to group 1) all input the digital code 1. After a certain period of time, as shown in the figure, Figure 4 As shown, the digital code 000000011111111 generated by the digital circuit is input into the capacitor array of group A. The bit capacitance to be measured (group 9) is input with digital code 0, and the bit capacitances with lower weights (groups 8 to 1) are all input with digital code 1. The digital code input into group B remains unchanged. Under ideal matching, the size of the bit capacitance should be equal to the sum of all the capacitances with lower weights. 1 indicates that the lower plate of the capacitor is connected to V ref , 0 means connected to GND. Figure 3 Status switch to Figure 4When in the [state], when the bit capacitance state changes between 011…1 and 100…0, the voltage at the comparator input should remain unchanged. Conversely, if there is a capacitance mismatch, a differential voltage ΔV will be generated. This differential voltage needs to be quantified into a digital code by the comparator. As Figure 5 shown, when the comparator result is 1, the data generator will change the digital code of the lowest-weight bit capacitance in Group A from 1 to 0 (Group 1), and the digital code in Group B remains unchanged; when the comparator result is 0, the digital code in Group A remains unchanged, and the data generator will change the digital code of the lowest-weight bit capacitance (Group 1) in Group B from 1 to 0. As Figure 6 shown, according to the result of each comparator, the capacitance on one side is gradually changed from low weight to high weight until the comparator result flips, and then the ΔV at this time can be measured. Next, the error of the bit capacitance with the same weight in Group B is measured in the same way. Repeat the above process until all the errors of the bit capacitances are measured.

[0050] The error of the i-th bit capacitance in the CDAC can be expressed as: ΔV i =ΔV A,i +ΔV B,i . The error of the i-th bit capacitance will cause a change in the output weight of the i-th bit of the ADC.

[0051] The calibration of each bit is mainly divided into two steps. The first step is to calibrate the weight of this bit, subtracting 1 / 2△V i to make it correctly match the actual size of the capacitance. After calibration, the weight W i of the output of the i-th bit of the ADC is The second step is to perform gain calibration on the weights of all bits lower than this bit. The weight W i-1 of the output of the (i - 1)-th bit is The weight W i-2 of the output of the (i - 2)-th bit is

[0052] And so on.

[0053] The output of the calibrated ADC is where Din is the output digital code of the ADC before calibration, and Dout is the output digital code after calibration.

[0054] Without calibration, the effective number of bits of the ADC is only 10.61 bits, as Figure 7 shown. After calibration, the effective number of bits of the SARADC is increased to 15.41 bits, as Figure 8 shown.

[0055] 1. Fully differential capacitor mismatch error self-measurement technology: This invention proposes a new method for measuring capacitor mismatch in SAR ADC. By reusing part of the ADC circuit, no additional analog circuit (such as auxiliary DAC) is required, thereby realizing self-measurement of capacitor mismatch. This method can measure the capacitor mismatch error without increasing hardware cost by measuring at both ends of CDAC separately and then superimposing the calculation. In addition, the influence of the comparator static offset voltage can be offset in the calculation process, ensuring the accuracy of the measurement result and being unaffected by the error of the comparator itself.

[0056] 2. Capacitor mismatch digital calibration technology: Compared with the traditional digital calibration technology based on the LMS algorithm, the calibration technology of the present invention only requires simple addition, subtraction and shift operations in the calculation and calibration process, avoiding the iterative convergence process of the LMS algorithm, which greatly reduces the calibration time and the complexity of the digital circuit. The traditional LMS algorithm requires a long time to iteratively optimize the weights, while the calibration method of the present invention can complete the calibration in one go after the mismatch error measurement, thereby improving the calibration efficiency.

[0057] Beneficial effects:

[0058] 1. Improve calibration accuracy: Since the mismatch error of the capacitor in the CDAC can be accurately measured and calibration is performed through a simple weighted operation, the present invention can significantly increase the effective number of bits of the SAR ADC and improve the conversion performance, thereby improving the calibration accuracy.

[0059] 2. Reduced calibration time: The long iteration process of the LMS algorithm is avoided and the calibration is completed in one go, which is particularly critical in high-speed, real-time calibration scenarios. Reduced calibration time means that the ADC can reach a stable operating state faster, which has significant advantages for applications that require fast response, such as high-speed data acquisition systems.

[0060] 3. Simplified circuit design: No additional auxiliary circuit is required, which reduces the chip area, design cost and power consumption. At the same time, due to the digital nature of the calibration technology, it has fewer restrictions on circuit design and is suitable for most fully differential SARADC architectures, improving the versatility and adaptability of the technology.

[0061] Why is it not easy to think of:

[0062] 1. Challenges of technology integration: Combining digital calibration technology with the fully differential characteristics of SAR ADC and realizing the measurement of capacitance mismatch without adding additional hardware requires in-depth understanding and innovative thinking of the working principle of SAR ADC, the impact of capacitance mismatch and digital calibration methods.

[0063] 2. Difficulty of algorithm optimization: The LMS algorithm has become a mainstream calibration technology due to its convergence and wide application in the field of signal processing. Stepping out of the framework of the LMS algorithm and designing an algorithm that can complete calibration in one go and is computationally simple requires finding a balance between theoretical analysis and practical verification, which is methodologically challenging.

[0064] 3. Power consumption and area considerations: While pursuing high performance, reducing power consumption and chip area is an eternal theme in integrated circuit design. Designing a method that can achieve high-precision calibration without the need for additional circuits requires a deep understanding of every part of the circuit and innovative optimization ideas, which is often not easily considered in actual design.

[0065] In summary, the innovation of the present invention lies in that it cleverly combines the fully differential characteristics of the SAR ADC and the digital calibration technology to achieve self-measurement and fast calibration of capacitance mismatch. This design idea and method are not easy to think of in the prior art. It not only improves the calibration accuracy, but also simplifies the circuit design, saves area and power consumption, and shortens the calibration time, and has significant technical and application value.

[0066] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0067] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0068] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A digital calibration method for a SAR ADC, characterized in that, including the following steps: a) The calibration module reads the capacitance mismatch error amount of the capacitive digital-to-analog converter (CDAC) in the successive approximation analog-to-digital converter (SAR ADC). The calibration module consists of a data generator, a weight calibration circuit, and an output calibration circuit; b) Correlate the read capacitance mismatch error amount with the ideal bit weight to extract the correlation result between the error amount and the weight. The ideal bit weight is VFS is the full-scale voltage of the SAR ADC; c) Send the relevant results into the output calibration circuit, and weight them with the binary code output by the ADC to achieve calibration of the output bit weights.

2. The digital calibration method according to claim 1, wherein In the step a), the CDAC circuit of the capacitive digital-to-analog converter consists of two symmetric capacitor arrays A and B. Among them, the capacitor array A is connected to the non-inverting terminal of the comparator, and the capacitor array B is connected to the inverting terminal of the comparator. By measuring the error voltage of the capacitors with the same weight bits in group A and group B, the total capacitance mismatch value of this bit is calculated.

3. The digital calibration method according to claim 1, characterized in that, In the step a), the CDAC and the comparator circuit in the ADC are multiplexed to generate and measure the error voltage of the capacitors with the same bit in group A and group B of the capacitive digital-to-analog converter CDAC respectively. Each time, only one-sided capacitors are switched, and the state of the other end capacitors is kept as 1, so as to obtain the one-sided capacitance mismatch error amount.

4. The digital calibration method according to claim 2, wherein The step of measuring the error voltage includes: a) The data generator generates a specific digital code and inputs it to the capacitor array A, and only the capacitor to be measured inputs the digital code 1, and the other capacitors input the code 0; b) The capacitors with the corresponding weights in group B and all the capacitors below input the digital code 1; c) After switching the state, the capacitor to be measured in group A inputs the digital code 0, and the other capacitors input the code 1, and the state of the capacitors in group B remains unchanged; d) Use the comparator to quantify the generated difference voltage to form a digital code for subsequent calibration.

5. The digital calibration method according to claim 4, characterized in that, The error of the i-th capacitor in the CDAC can be expressed as: ΔV i = ΔV A,i + ΔV B,i , the error of the i-th capacitor will cause a change in the output weight of the i-th bit of the ADC. ΔV A,i , ΔV B,i represent the error voltage of the i-th capacitor on the A side and the error voltage of the i-th capacitor on the B side, respectively.

6. The digital calibration method according to claim 5, wherein The weight calibration process includes: using W i to represent the weight value of the output of the i-th bit of the ADC. In an ideal situation, the weight W i of the output of the i-th bit of the ADC should be an accurate binary, that is V FS is the full-scale voltage of the SAR ADC; after calibration, the weight W i of the output of the i-th bit of the ADC is The weight W i-1 of the output of the (i - 1)-th bit is The weight W i-2 of the output of the (i - 2)-th bit is and so on; the overall output of the ADC where Din is the ADC output before calibration of the ADC, and Dout is the ADC output after calibration.

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