Calibration circuit for time constant of continuous time sigma-delta modulator

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a calibration circuit for a time constant of a continuous-time sigma-delta modulator, which not only reduces the requirement on an extra high-frequency calibration clock, but also reduces the cost by using a fixed-time integration method and using a multiple of a system sampling clock period of the sigma-delta modulator as integration time. And high-precision time constant calibration can be realized even under the condition that a system clock has an error. The design can significantly reduce the deviation between the system transfer function of the actual sigma-delta modulator circuit and the ideal system, and ensures the high performance of the modulator. Meanwhile, due to the fact that an operational amplifier which is the same as the modulator circuit and a capacitor resistor which is proportional to the modulator circuit are adopted, the real integration process is simulated to the maximum extent, and calibration accuracy is further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a calibration circuit for the time constant of a continuous-time sigma-delta modulator. Background Art

[0002] In the design of a continuous-time sigma-delta modulator, the time constant of the integrator (determined by resistor R and capacitor C) is crucial for ensuring system performance. However, during the actual chip manufacturing process, due to process variations, the actual values of the resistor and capacitor may deviate significantly from the designed values, resulting in a time constant deviation of more than 50%. When the integrator coefficient changes by more than 10%, the performance of the sigma-delta modulator will be significantly reduced, especially in systems with a higher out-of-band gain. Therefore, how to more accurately calibrate the time constant of the integrator has become one of the key challenges in ensuring the performance of continuous-time sigma-delta modulators.

[0003] Existing calibration methods, such as the analog calibration scheme based on current mirror integration, have multiple error sources, including current mirror mismatch, parasitic capacitance effects, and kickback noise in dynamic comparators. These factors will all lead to inaccurate calibration results and thus affect the overall performance of the modulator. Summary of the Invention

[0004] The purpose of the present invention is to provide a calibration circuit for the time constant of a continuous-time sigma-delta modulator, and a static comparator is adopted to avoid the defects existing in some traditional calibration circuits and has higher calibration accuracy, so as to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention adopts the following technical solution: A calibration circuit for the time constant of a continuous-time sigma-delta modulator, comprising an integrator, a static comparator, and a digital logic circuit; wherein, the integrator is replicated from the integrator circuit in the sigma-delta modulator, and includes an input resistor R1, an integration capacitor array C, a fixed resistor R2, an operational amplifier, and switches S1, S2, and S3; the access area of the integration capacitor array C is adjusted by a digital codeword control switch; the input end of the integrator is connected to reference voltages V REFP and V REFN , and the output end is connected to the integration capacitor array C; the output end of the integrator is connected to the input end of the static comparator, and the output end of the static comparator is connected to the digital logic circuit through a D flip-flop; the digital logic circuit adjusts the digital code value of the integration capacitor array C according to the output result of the comparator.

[0006] Preferably, the working modes of the integrator include a differential amplification mode and an integrator mode.

[0007] Preferably, the input end of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; switches S1 and S3 are controlled by the same clock control, and switch S2 is controlled by the clock control; the switching of the switches realizes the switching of the integrator between the differential amplification mode and the integrator mode.

[0008] Preferably, in the differential amplification mode, switches S1 and S3 are closed, and the operational amplifier works as a differential amplifier. The input end V IP is connected to the V REFP -R1-S1 branch, and the input end V IN is connected to the V REFN -R1-S1 branch; in the integrator mode, switches S1 and S3 are disconnected, switch S2 is closed, and the operational amplifier works in the integrator mode. The input end V IP is connected to the V REFN -R1-S2 branch, and the input end V IN is connected to the V REFP -R1-S2 branch.

[0009] Preferably, in the integrator mode, the integration capacitor array C is charged and discharged under the action of a constant differential current. The charging and discharging time is controlled by the system sampling clock frequency division. The integration process lasts for n system sampling clock cycles, where n is a preset integer; after the integration is completed, the differential output voltage of the operational amplifier is compared by a static comparator to determine whether the actual value of the integration capacitor array C meets the designed time constant.

[0010] Preferably, the output result of the static comparator is delayed after the integration is completed and latched by a D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by a digital logic circuit for adjusting the digital code value of the integration capacitor array C.

[0011] Preferably, the digital logic circuit adjusts the digital code value of the integration capacitor array C by the dichotomy method; if the output result of the comparator is 0, the access area of the integration capacitor array C is reduced; if the output result of the comparator is 1, the access area of the integration capacitor array C is increased; after N cycles, N is the number of digits of the digital code of the integration capacitor array C, and finally the calibrated time constant is obtained.

[0012] Preferably, the static comparator is of a fully differential structure, and its positive input end is connected to the output end V ON of the integrator, and the negative input end is connected to the output end V OP of the integrator.

[0013] Technical effects and advantages of the present invention: A calibration circuit for the time constant of a continuous-time sigma-delta modulator proposed by the present invention has the following advantages compared with the prior art: The present invention adopts a differential structure and a static comparator to replace the traditional dynamic comparator, effectively avoiding calibration errors caused by current mirror mismatch, parasitic capacitance error, and dynamic comparator kickback noise. By using the method of fixed-time integration and using the system sampling clock period of the sigma-delta modulator as the integration time, not only the need for an additional high-frequency calibration clock is reduced, but also high-precision time constant calibration can be achieved even when there is a deviation in the system clock period. This design can significantly reduce the deviation between the system transfer function of the actual sigma-delta modulator circuit and the ideal system, ensuring the high-performance performance of the modulator. At the same time, since the same operational amplifier and proportional capacitance and resistance as the modulator circuit are adopted, the real integration process is simulated to the greatest extent, thereby further improving the accuracy of calibration. Description of the Drawings

[0014] Figure 1 is the circuit diagram of the calibration circuit of the present invention; Figure 2 is the timing logic diagram of the present invention. Detailed Embodiments

[0015] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0016] The present invention provides a calibration circuit for the time constant of a continuous-time sigma-delta modulator, including an integrator, a static comparator, and a digital logic circuit; Among them, the integrator is replicated from the integrator circuit in the sigma-delta modulator, and includes an input resistor R1, an integration capacitor array C, a fixed resistor R2, an operational amplifier, and switches S1, S2, and S3; The access area of the integration capacitor array C is adjusted by a digital codeword control switch; the input end of the integrator is connected to the reference voltages V REFP and V REFN, the output terminal is connected to the integrating capacitor array C; the output terminal of the integrator is connected to the input terminal of the static comparator, and the output terminal of the static comparator is connected to the digital logic circuit through a D flip-flop; the static comparator is of a fully differential structure, and its positive input terminal is connected to the output terminal V of the integrator ON , and the negative input terminal is connected to the output terminal V of the integrator OP . The digital logic circuit adjusts the digital code value of the integrating capacitor array C according to the output result of the comparator.

[0017] Furthermore, the working modes of the integrator include a differential amplification mode and an integrator mode.

[0018] Specifically, the input terminal of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; the switches S1 and S3 are controlled by the same clock , and the switch S2 is controlled by the clock ; the switching of the switches realizes the switching of the integrator between the differential amplification mode and the integrator mode.

[0019] Among them, in the differential amplification mode, the switches S1 and S3 are closed, and the operational amplifier works as a differential amplifier. The input terminal V IP is connected to the V REFP -R1-S1 branch, and the input terminal V IN is connected to the V REFN -R1-S1 branch; in the integrator mode, the switches S1 and S3 are disconnected, the switch S2 is closed, and the operational amplifier works in the integrator mode. The input terminal V IP is connected to the V REFN -R1-S2 branch, and the input terminal V IN is connected to the V REFP -R1-S2 branch.

[0020] Among them, in the integrator mode, the integrating capacitor array C is charged and discharged under the action of a constant differential current. The charging and discharging time is controlled by the system sampling clock frequency division. The integration process lasts for n system sampling clock cycles, where n is a preset integer; after the integration is completed, the differential output voltage of the operational amplifier is compared by the static comparator to determine whether the actual value of the integrating capacitor array C meets the designed time constant.

[0021] Furthermore, the output result of the static comparator is delayed after the integration is completed and latched by the D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by the digital logic circuit for adjusting the digital code value of the integrating capacitor array C.

[0022] In addition, the digital logic circuit adjusts the digital code value of the integration capacitor array C by the dichotomy method; if the output result of the comparator is 0, the access area of the integration capacitor array C is reduced; if the output result of the comparator is 1, the access area of the integration capacitor array C is increased; after N cycles, where N is the number of digits of the digital code of the integration capacitor array C, the calibrated time constant is finally obtained.

[0023] The following will be described in detail with reference to the accompanying drawings: As Figure 1 shown, the integrator in the calibration circuit is replicated based on the integrator circuit in the sigma-delta modulator. It includes capacitors, resistors, and operational amplifiers, and ensures that the capacitance and resistance values maintain a specific proportional relationship with the prototype circuit. In this design, the resistance value is fixed, while the integration capacitor is designed to be adjustable, and the capacitance connected to the integrator is adjusted by switches controlled by digital codewords.

[0024] First, the operational amplifier is configured in the voltage amplifier mode and a specific input voltage is applied to charge the integration capacitor. Subsequently, the amplifier is switched to the integrator mode and the input voltage is adjusted to ensure that the integrator capacitor is charged and discharged under a constant current. The duration of the charge and discharge is controlled by the division of the system sampling clock, so that both the system clock and the capacitance and resistance participate in the calibration process, thereby obtaining a result that is more consistent with the actual situation.

[0025] The output of the integrator is connected to a static comparator. After the integration capacitor completes a charge and discharge cycle, the comparator outputs a comparison result, which is sampled by a D flip-flop and sent to the digital logic circuit for further processing. Finally, the digital logic circuit adjusts the coding of the capacitor array according to the output result of the comparator and repeats the above process. After multiple cycles, a stable capacitance code value is obtained, which is the final result of the time constant calibration.

[0026] There are four branches at the input end of the integrator. Two groups of input reference voltages V REFP and V REFN are respectively connected to the input resistor R1, and the other ends of the resistor R1 are respectively connected to two groups of switches S1 and S2, forming four branches of V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2. The other ends of the switches S1 and S2 of the two branches of V REFP -R1-S1 and V REFN -R1-S2 are connected to the input terminal V IP of the operational amplifier. V REFP -R1-S1, V REFPThe other ends of the switches S1 and S2 of the -R1-S2 two branches are connected to the input terminal V of the operational amplifier. IN Connected. At the input and output terminals of the operational amplifier, V IP and V ON , and between V IN and V OP , a parallel path composed of an integration capacitor array C, a resistor R2, and a switch S3 is connected, where the resistor R2 is in series with the switch S3. The switches S1 and S3 are controlled by the same clock control, and the switch S2 is controlled by the clock control.

[0027] The output terminals V OP and V ON of the integrator are respectively connected to the negative input terminal and the positive input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the D flip-flop, and the clock input terminal of the D flip-flop receives a signal from the clock CLKD. When the rising edge of CLKD arrives, the system samples the output result of the comparator. The output terminal of the D flip-flop is further connected to a digital logic circuit, which is responsible for processing the output result and feeding back a digital code to control the capacitor array in the integrator.

[0028] As Figure 2 shown, when the switches S1 and S3 are closed, the operational amplifier works as a differential amplifier. The input terminal V IP of the operational amplifier is connected to S1, R1, and V REFP , and the input terminal V IN is connected to S1, R1, and V REFN . The output voltage , so the difference in the charge amounts of the positive and negative integration capacitors C at this time is .

[0029] It should be noted that by appropriately increasing the resistance R1 and reducing the voltage value, the output voltage of the operational amplifier can be limited within its output range. Take , , where is a constant, so is obtained.

[0030] Immediately afterwards, after the switches S1 and S3 are disconnected, the switch S2 is closed. At this time, the operational amplifier works in the integrator mode, and R2 is disconnected from the input terminal of the operational amplifier. The input terminal V IP of the operational amplifier is connected to S2, R1, and V REFN , and the input terminal V IN is connected to S2, R1, and V REFP . A constant differential current flows through the capacitor C., after integration over n system sampling clock cycles, the differential output voltage of the operational amplifier is .

[0031] Given that the time constant is , by adjusting the resistors R1 and R2, and the number of clock cycles n of the integration, the determined values m and n are obtained. So that under ideal conditions, , that is . Since m and n are determined constants, so when the output differential voltage approaches 0, approaches the required time constant. In the present invention, only the capacitor is adjustable, so when the capacitance and resistance are affected by the manufacturing process, the designed time constant is approximated by adjusting the capacitor code.

[0032] The output terminal of the operational amplifier is connected to a static comparator. When the operational amplifier operates in the differential amplification mode, , the output of the comparator remains 0. During the integrator process, once the output of the comparator flips to 1. For a period of time after switch S2 is opened, switch S1 is also in the open state. During this period, the output of the operational amplifier maintains the voltage value at the end of the integration to leave sufficient setup time for the comparator.

[0033] Due to a certain delay in the static comparator, after the integrator finishes integrating, after a period of delay, the output of the comparator is latched in the output of the D flip-flop through the clock CLKD. After that, the output D of the D flip-flop O does not change with the output of the comparator until the next clock rising edge of CLKD arrives. The digital logic has sufficient time to process the output and feedback a new capacitor code value to start a new round of amplification, integration, and comparison processes. After multiple repeated operations, approaches .

[0034] The processing principle of the digital logic is as follows: If the actual capacitance value is too large, then , the integration final value is obtained, and the output of the comparator is 0. After the digital logic detects the output 0, it changes the capacitor code value to decrease the integration capacitance value. On the contrary, if the actual capacitance value is too small, then , the integration final value is obtained, and the output of the comparator is 1. After the digital logic detects the output 1, it changes the capacitor code value to increase the integration capacitance value. The feedback capacitor code value logic can be implemented by the dichotomy method. If the number of bits of the capacitor code value is N bits, then the calibrated capacitor code value can be obtained after N cycles.

[0035] The time constant error of this calibration circuit is determined by the minimum unit capacitance of the capacitor array. The ideal time constant is , and the time constant with error after calibration is , where is the minimum unit capacitance. Therefore, the relative error of the time constant is , and the maximum relative error rate can be deduced as . If the variation range of the capacitor array is to cover a 20% process deviation of the capacitance resistance, can be obtained. Therefore: when, ; when, ; when, ; when, . If it is necessary to ensure that the deviation of the time constant from the ideal value is less than 10%, the number of bits N of the capacitor code value needs to be greater than or equal to 4.

[0036] The calibration circuit of the present invention abandons the traditional clock counting calibration method and instead adopts the fixed-time integration and successive approximation technology, without the intervention of an additional high-frequency comparator clock. The integrator circuit completes the integration within n system clock cycles and maintains the output state, and then the static comparator outputs a 1-bit comparison result. The digital logic part is responsible for judging and adjusting the capacitance. By repeating this process multiple times, the time constant of the integrator gradually approaches the design value.

[0037] This solution incorporates all three key parameters of the time constant: the system sampling clock, capacitance, and resistance into the calibration process, and the calibration result is jointly determined by these three parameters. Even if there is a deviation in the system clock cycle, this solution can still obtain the correct integration time constant through the calibration process. By adjusting the resistance ratio and integration time, the calibrated result can achieve a more accurate time constant.

[0038] Compared with the traditional calibration technology, the present invention avoids the current mirror ratio error, the correlation between the calibration error and the counting clock, and the comparison result error caused by the kickback noise in the dynamic comparator. In addition, it also eliminates the error caused by the parasitic capacitance of the integration capacitor. In the differential amplification mode of the operational amplifier, the capacitor charging voltage is only related to the ratio of resistors R1 and R2. During the manufacturing process of the integrated circuit, although the absolute values of the resistors or capacitors cannot be precisely controlled, the matching degree of the relative values of the resistors and capacitors can be more precisely controlled, so that the capacitor charging voltage can also be more precisely managed.

[0039] In summary, the present invention has successfully achieved high-precision calibration of the time constant of a continuous-time sigma-delta modulator, and its error is only related to the number of bits of the capacitor array and the offset voltage of the comparator. By using the same operational amplifier and proportional capacitor and resistor in the modulator circuit, the integration process is simulated to the greatest extent, thereby reducing the mismatch error caused by the introduction of additional devices and circuit structures.

[0040] The present invention uses a multiple of the system sampling clock period of the sigma-delta modulator as the integration time of the calibration circuit, effectively avoiding the problem of the correlation between the calibration error and the calibration clock frequency in the traditional calibration circuit. Even when there is an error in the system clock frequency, a relatively accurate time constant can still be obtained.

[0041] By adopting a fully differential amplification structure, the integration current only charges and discharges the capacitor connected across the input and output terminals, regardless of the parasitic capacitance, thereby avoiding the error caused by the parasitic capacitance in the traditional calibration circuit. In addition, using a static comparator to replace the traditional dynamic comparator effectively avoids the incorrect comparison result caused by the kickback noise in the dynamic comparator.

[0042] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A calibration circuit for the time constant of a continuous-time sigma-delta modulator, characterized in that, It includes an integrator, a static comparator, and digital logic circuits; Among them, the integrator is replicated from the integrator circuit in the sigma-delta modulator, and includes an input resistor R1, an integration capacitor array C, a fixed resistor R2, an operational amplifier, and switches S1, S2, and S3; The access area of the integration capacitor array C is adjusted by a digital codeword control switch; the input end of the integrator is connected to a reference voltage V REFP and V REFN , the output end is connected to the integration capacitor array C; the output end of the integrator is connected to the input end of a static comparator, and the output end of the static comparator is connected to a digital logic circuit through a D flip-flop; the digital logic circuit adjusts the digital code value of the integration capacitor array C according to the output result of the comparator.

2. The calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 1, wherein The working modes of the integrator include a differential amplification mode and an integrator mode.

3. A calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 2, characterized in that, The input terminal of the integrator includes four branches: V REFP -R1-S1, V REFN -R1-S2, V REFN -R1-S1, V REFP -R1-S2; switches S1 and S3 are controlled by the same clock control, switch S2 is controlled by the clock control; the switching of the switches realizes the switching of the integrator between the differential amplification mode and the integrator mode.

4. A calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 3, characterized in that In differential amplification mode, switches S1 and S3 are closed, and the operational amplifier operates as a differential amplifier. The input terminal V IP is connected to V REFP -R1-S1 branch, and the input terminal V IN is connected to V REFN -R1-S1 branch; in integrator mode, switches S1 and S3 are open, switch S2 is closed, and the operational amplifier operates in integrator mode. The input terminal V IP is connected to V REFN -R1-S2 branch, and the input terminal V IN is connected to V REFP -R1-S2 branch.

5. The calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 3, wherein In the integrator mode, the integration capacitor array C is charged and discharged under the action of a constant differential current, and the charging and discharging time is controlled by the system sampling clock division. The integration process lasts for n system sampling clock cycles, where n is a preset integer; After the integration ends, the differential output voltage of the operational amplifier is compared by the static comparator to determine whether the actual value of the integration capacitor array C meets the designed time constant.

6. The calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 1, characterized in that, The output result of the static comparator is delayed after the integration ends and is latched by a D flip-flop at the rising edge of the clock; the output signal of the D flip-flop is sampled by the digital logic circuit for adjusting the digital code value of the integration capacitor array C.

7. A calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 6, characterized in that, The digital logic circuit adjusts the digital code value of the integration capacitor array C by the dichotomy method; if the output result of the comparator is 0, the access area of the integration capacitor array C is reduced; if the output result of the comparator is 1, the access area of the integration capacitor array C is increased; after N cycles, where N is the number of digits of the digital code of the integration capacitor array C, the calibrated time constant is finally obtained.

8. A calibration circuit for the time constant of a continuous-time sigma-delta modulator according to claim 1, characterized in that, The static comparator has a fully differential structure, and its positive input terminal is connected to the output terminal V of the integrator ON , and its negative input terminal is connected to the output terminal V of the integrator OP .

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