Equalizer and transmitter including equalizer

Abstract

An equalizer and a transmitter including the equalizer are provided. The equalizer includes: a delay circuit configured to generate at least one delayed signal based on at least one input signal; an encoding circuit configured to generate a connection switching signal and a plurality of driving signals based on an input signal and a delay signal; a pre-driver configured to generate a plurality of driving switch signals based on the plurality of driving signals; a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals; a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals; and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

Description

[0001] This application claims the benefit of priority based on and claiming priority to Korean Patent Application No. 10-2024-0008287, filed with the Korean Intellectual Property Office on January 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various exemplary embodiments of the inventive concept relate to an equalizer including a connection circuit, a system including the equalizer, and / or a method of operating the equalizer, etc. Background Art

[0003] An electronic device may transmit an electrical signal to another electronic device through a channel to exchange information. When a signal is transmitted and / or received between electronic devices, signal distortion may occur due to the response characteristics of the channel. Various types of equalizers are used to compensate for signal distortion.

[0004] An equalizer may transmit a signal through a plurality of switching elements. In this case, when the states of the plurality of switching elements change based on the pattern of the signal input to the equalizer, the output resistance of the equalizer may change. When the output resistance of the equalizer changes, impedance matching may fail and / or degrade, causing problems such as reflection and / or distortion of the signal transmitted between the transmitter and the channel. Therefore, it is desirable and / or necessary to develop an equalizer that performs more accurate impedance matching and / or has improved impedance matching, etc. Summary of the Invention

[0005] Various exemplary embodiments of the inventive concept provide an equalizer that can perform impedance matching more accurately and / or can have improved impedance matching performance, a system including the equalizer, and / or a method of operating the equalizer, etc.

[0006] An equalizer according to at least one exemplary embodiment includes: a delay circuit configured to generate at least one delayed signal based on at least one input signal; an encoding circuit configured to generate a connection switch signal and a plurality of driving signals based on the input signal and the delayed signal; a pre-driver configured to generate a plurality of driving switch signals based on the plurality of driving signals; a first differential circuit configured to generate a first differential output signal based on the plurality of driving switch signals; a second differential circuit configured to generate a second differential output signal based on the plurality of driving switch signals; and a connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the connection switch signal.

[0007] An equalizer according to at least one example embodiment includes: a delay circuit configured to generate one or more delayed signals based on at least one input signal; an encoding circuit configured to generate a plurality of drive signals and one or more connection switch signals based on the input signal and the one or more delayed signals; a pre-driver configured to generate a plurality of drive switch signals based on the plurality of drive signals; a first differential circuit configured to generate a first differential output signal based on the plurality of drive switch signals; a second differential circuit configured to generate a second differential output signal based on the plurality of drive switch signals; and a connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the one or more connection switch signals.

[0008] A transmitter for transmitting an input signal through a channel according to at least one example embodiment includes: a serializer configured to convert the input signal into a serial input signal; and an equalizer configured to generate a first differential output signal and a second differential output signal based on the serial input signal, the equalizer including: a delay circuit configured to generate one or more delayed signals based on at least one input signal, an encoding circuit configured to generate a plurality of drive signals and one or more connection switch signals based on the at least one input signal and the one or more delayed signals, a pre-driver configured to generate a plurality of drive switch signals based on the plurality of drive signals, a first differential circuit configured to generate a first differential output signal based on the plurality of drive switch signals, a second differential circuit configured to generate a second differential output signal based on the plurality of drive switch signals, and a connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the one or more connection switch signals. Brief Description of the Drawings

[0009] Various example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram showing a communication device according to at least one example embodiment.

[0011] Figure 2 is a block diagram showing an equalizer according to at least one example embodiment.

[0012] Figure 3 is a circuit diagram showing an example of a delay circuit of an equalizer according to at least one example embodiment.

[0013] Figure 4 is a circuit diagram showing an example of an encoding circuit of an equalizer according to at least one example embodiment.

[0014] Figure 5A circuit diagram showing an example of a pre-driver of an equalizer according to at least one example embodiment.

[0015] Figure 6 A circuit diagram showing an example of a driver of an equalizer according to at least one example embodiment.

[0016] Figures 7A to 7C A graph showing the output of a circuit for a signal applied to the equalizer shown in Figures 3 to 6 according to some example embodiments.

[0017] Figure 8 A circuit diagram showing a resistor equivalent circuit of a driver of an equalizer according to at least one example embodiment.

[0018] Figure 9 A circuit diagram showing another example of a delay circuit of an equalizer according to at least one example embodiment.

[0019] Figure 10A and Figure 10B A circuit diagram showing another example of an encoding circuit of an equalizer according to at least one example embodiment.

[0020] Figure 11 A circuit diagram showing another example of a pre-driver of an equalizer according to at least one example embodiment.

[0021] Figure 12 A circuit diagram showing another example of a driver of an equalizer according to at least one example embodiment.

[0022] Figure 13 A diagram showing a system including an equalizer according to at least one example embodiment.

[0023] Figure 14 A diagram showing a system-on-chip including an equalizer according to at least one example embodiment. Detailed Description

[0024] Hereinafter, various example embodiments will be described in detail with reference to the drawings.

[0025] Figure 1 A block diagram showing a communication device 1 according to at least one example embodiment.

[0026] Referring to Figure 1 , the communication device 1 (e.g., a first communication device, etc.) can perform serial communication with another communication device (e.g., a second communication device, etc.) (not shown) via a transmission (TX) channel 2 and a reception (RX) channel 3, but the example embodiments are not limited thereto. In Figure 1In [the figure], it is shown that the communication device 1 communicates with another communication device through a full-duplex communication scheme (e.g., through two channels such as a TX channel 2 and an RX channel 3, etc.), but the exemplary embodiments of the inventive concept are not limited thereto. In other exemplary embodiments, the communication device 1 may communicate with another communication device through a half-duplex communication scheme (e.g., through one channel) and / or by using three or more channels, etc.

[0027] The TX channel 2 and / or the RX channel 3 may represent a connection between the communication device 1 and another communication device, and the serial signals S1 and S2 may move through the TX channel 2 and / or the RX channel 3, respectively. For example, the TX channel 2 and / or the RX channel 3 may include at least one of wires of an integrated circuit, patterns of a printed circuit board (PCB), connectors, and / or cables, etc. As Figure 1 shown in [the figure], the serial signals S1 and S2 passing through the TX channel 2 and the RX channel 3, respectively, may each be differential signals, but are not limited thereto.

[0028] The communication device 1 may be a device that serially communicates with another communication device through the TX channel 2 and the RX channel 3, but is not limited thereto. In at least one exemplary embodiment, the communication device 1 may be a die included in a semiconductor package and may serially communicate with another communication device included in the same semiconductor package, but is not limited thereto. In at least one exemplary embodiment, the communication device 1 may be a semiconductor package mounted on a PCB and may serially communicate with another communication device mounted on the same PCB and / or a different PCB, etc. In at least one exemplary embodiment, the communication device 1 may be a system (e.g., a storage device, a computing system, etc.) including at least one semiconductor package and / or a PCB, etc., and may serially communicate with another system.

[0029] The communication device 1 may include, but is not limited to, a processor 10, a transmitter 20, and / or a receiver 30, and may include, for example, a greater or lesser number of constituent components. In at least one example embodiment, the transmitter 20 and the receiver 30 may be combined into a single transceiver and may be implemented as one block. The processor 10, the transmitter 20, and the receiver 30 may provide a physical layer for communication and may be referred to as a serializer / deserializer (SerDes) for serial communication. According to some example embodiments, one or more of the processor 10, the transmitter 20, and / or the receiver 30, etc. may be implemented as processing circuitry. The processing circuitry may include: hardware or a hardware circuit including logic circuits; a hardware / software combination (such as a processor that executes software and / or firmware); or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc., but is not limited thereto.

[0030] The processor 10 may provide at least one transmission signal (the at least one transmission signal is at least one signal to be transmitted through the TX channel 2) to the transmitter 20, and / or may receive at least one reception signal (the at least one reception signal is at least one signal received through the RX channel 3) from the receiver 30. The transmission signal and / or the reception signal may move through a plurality of signal lines (i.e., a bus).

[0031] The processor 10 may generate a transmission signal and / or may process a reception signal based on at least one desired communication protocol (e.g., a protocol specified by the Optical Internetworking Forum (OIF), the Institute of Electrical and Electronics Engineers (IEEE), etc.). For example, the processor 10 may process source data received from another element included in the communication device 1 and / or outside the communication device 1 (e.g., outside the communication device 1) to generate a transmission signal. In addition, the processor 10 may provide, for example, result data generated by processing the reception signal to another element included in the communication device 1 and / or outside the communication device 1 (e.g., outside the communication device 1), etc. The processor 10 may include at least one of a hardware block designed by logic synthesis and / or a software block including a plurality of computer-readable instructions, but is not limited thereto. Hereinafter, the transmission signal provided to the transmitter 20 may be referred to as an input signal.

[0032] The transmitter 20 may receive a transmission signal from the processor 10 and may output a serial signal S1 to the TX channel 2. As Figure 1As shown, the transmitter 20 may include a serializer 21 and / or a TX equalizer 22, etc., but is not limited thereto. In at least one exemplary embodiment, the transmitter 20 may be included in an integrated circuit manufactured by a semiconductor process, but is not limited thereto.

[0033] The serializer 21 may convert the transmission signal received through the bus into a serial transmission signal and send the serial transmission signal to the TX equalizer 22. For example, the serial transmission signal may include a series of symbols each having a unit interval (UI) of "1 / baud rate", and when n is an integer greater than 1, the serializer 21 may latch n-bit transmission signals at a frequency of "baud rate / n", but is not limited thereto.

[0034] The TX equalizer 22 may receive the serial transmission signal from the serializer 21 and may generate a serial signal S1. The TX equalizer 22 may perform equalization to compensate for distortion (e.g., inter-symbol interference (ISI), etc.) of the serial signal S1 that occurs in the TX channel 2. The TX equalizer 22 may output the serial signal S1 to the TX channel 2.

[0035] In at least one exemplary embodiment, as described below with reference to Figure 2 the TX equalizer 22 may include a connection circuit, and the connection circuit may adjust the connection between the first differential circuit and / or the second differential circuit to maintain the output resistance of the equalizer. As described above, when the output resistance of the equalizer is maintained, impedance matching may be accurately performed and / or improved impedance matching may be observed, thereby reducing and / or preventing signal reflection and / or distortion.

[0036] The receiver 30 may receive the serial signal S2 through the RX channel 3 and may provide the received signal to the processor 10. As Figure 1 shown, the receiver 30 may include an RX equalizer 31 and / or a deserializer 32, etc., but is not limited thereto. In at least one exemplary embodiment, the receiver 30 may be included in an integrated circuit manufactured by a semiconductor process, but is not limited thereto.

[0037] The RX equalizer 31 may generate a received signal based on the serial signal S2 that is a differential signal, but is not limited thereto. In addition, the RX equalizer 31 may have an input impedance for performing impedance matching. The RX equalizer 31 may perform equalization to compensate for distortion of the serial signal S2 that occurs in the RX channel 3, etc.

[0038] The deserializer 32 may convert the received signal received from the RX equalizer 31. For example, the received signal may include a series of symbols each having a UI of "1 / baud rate", and when n is an integer greater than 1, the deserializer 32 may output n-bit received signals at a frequency of "baud rate / n", but the exemplary embodiment is not limited thereto.

[0039] Figure 2 It is a block diagram showing an equalizer 100 according to at least one exemplary embodiment.

[0040] Referring to Figure 2 , the equalizer 100 according to at least one exemplary embodiment may include a delay circuit 110, an encoding circuit 120, a pre-driver 130, and / or a driver 140, etc., but the exemplary embodiment is not limited thereto. According to some exemplary embodiments, one or more of the equalizer 100, the delay circuit 110, the encoding circuit 120, the pre-driver 130, and / or the driver 140, etc., may be implemented as a processing circuitry. The processing circuitry may include: hardware or a hardware circuit including a logic circuit; a hardware / software combination (such as a processor executing software and / or firmware); or a combination thereof. For example, the processing circuitry may more specifically include but is not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc., but is not limited thereto.

[0041] The delay circuit 110 may generate one or more delayed signals based on the input signal IN. The delay circuit 110 may include one or more latches, but is not limited thereto. The delay circuit 110 may generate a delayed signal by delaying the input signal IN using one or more latches. For example, when the input signal IN is x[0], the delay circuit 110 may generate a delayed signal (such as x[1] or x[2], etc.) by delaying x[0] using a latch. The delay circuit 110 may output the generated delayed signal to the encoding circuit 120.

[0042] The following will refer to Figure 3 and Figure 9 describe the more detailed structure and operation of the delay circuit 110.

[0043] The encoding circuit 120 may generate a plurality of driving signals and / or connection switch signals based on the input signal IN and one or more delayed signals.

[0044] The encoding circuit 120 may generate a plurality of driving signals based on the input signal IN and one or more delayed signals. The encoding circuit 120 may output the generated plurality of driving signals to the pre-driver 130, etc.

[0045] In addition, the encoding circuit 120 may generate one or more connection switch signals based on the plurality of driving signals. In this case, the encoding circuit 120 may generate one or more connection switch signals based on "the plurality of driving signals generated according to the same delayed signal among one or more delayed signals", but is not limited thereto. The encoding circuit 120 may output the generated one or more connection switch signals to the driver 140, etc.

[0046] Hereinafter, reference will be made to Figure 4 , Figure 10A and Figure 10B describe the more detailed structure and operation of the encoding circuit 120.

[0047] The pre-driver 130 can generate a plurality of driving switch signals based on a plurality of driving signals. For example, the pre-driver 130 can perform at least one inversion operation on the plurality of driving signals to generate a plurality of driving switch signals, but is not limited thereto. According to some example embodiments, the pre-driver 130 can perform at least one inversion operation on some of the plurality of driving signals (e.g., the first set of driving signals) by using a ground voltage and perform at least one inversion operation on the remaining driving signals (e.g., the second set of driving signals) of the plurality of driving signals by using an operating voltage, etc. to generate a plurality of driving switch signals. The pre-driver 130 can output the generated plurality of driving switch signals to the driver 140, etc.

[0048] Hereinafter, reference will be made to Figure 5 and Figure 11 describe the more detailed structure and operation of the pre-driver 130.

[0049] The driver 140 can generate, for example, a first differential output signal V outp and a second differential output signal V outn based on a plurality of driving switch signals and one or more connection switch signals, but the example embodiments are not limited thereto.

[0050] The driver 140 can include a first differential circuit and / or a second differential circuit, etc., but is not limited thereto.

[0051] The first differential circuit can generate a first differential output signal V outp based on a plurality of driving switch signals. The first differential circuit can include a plurality of positive output taps, etc. When a plurality of switching elements included in the plurality of positive output taps are turned on or off by the plurality of driving switch signals, the plurality of positive output taps can generate a first differential output signal V outp , but is not limited thereto.

[0052] The second differential circuit can generate a second differential output signal V outn based on a plurality of driving switch signals. The second differential circuit can include a plurality of negative output taps, but is not limited thereto. When a plurality of switching elements included in the plurality of negative output taps are turned on or off by the plurality of driving switch signals, the plurality of negative output taps can generate a second differential output signal V outn , but is not limited thereto.

[0053] The connection circuit can adjust the connection between the first differential circuit and / or the second differential circuit based on one or more connection switch signals, etc. The connection circuit can include one or more connection switch elements, but is not limited thereto. When the positive output tap and the negative output tap respectively connected to each of the one or more switch elements are in an open state, each of the one or more connection switch elements can connect the positive output tap to the negative output tap. As described above, the equalizer 100 according to at least one example embodiment can adjust the connection between the first differential circuit and the second differential circuit by using the connection circuit to maintain the output resistance of the equalizer 100. As described above, when the output resistance is maintained, impedance matching can be accurately performed and / or the impedance matching can be improved, so that signal reflection and / or distortion, etc. can be reduced and / or prevented.

[0054] The following will refer to Figure 6 and Figure 12 to describe the more detailed structure and operation of the driver 140.

[0055] Figure 3 FIG. is a circuit diagram showing an example of the delay circuit 110 of the equalizer 100 according to at least one example embodiment.

[0056] Referring to Figure 3 , the delay circuit 110 of the equalizer 100 according to at least one example embodiment can include at least one latch 111, etc., but is not limited thereto. In Figure 3 at least one example embodiment of, the equalizer 100 including the delay circuit 110 can be a 2-tap equalizer, where two output taps are included in the driver 140, but the example embodiment is not limited thereto, and for example, it can be an equalizer with a greater or smaller number of taps, etc. When the equalizer 100 is a 2-tap equalizer, the delay circuit 110 can include one latch 111.

[0057] The delay circuit 110 of the equalizer 100 according to at least one example embodiment can include at least one latch 111, etc. The latch 111 can delay the input signal IN by a desired and / or predetermined delay time D to generate at least one delayed signal. For example, when the input signal IN is x[0] and the delay time D of the latch 111 is 1, the latch 111 can output x[1] obtained through a 1-time delay caused by the latch 111, etc.

[0058] In Figure 3 at least one example embodiment of, the delay circuit 110 can output the input signal IN that has not passed through the latch 111 as the reference input signal D IN_main to the encoding circuit 120. The delay circuit 110 can output the input signal IN that has passed through the latch 111 as the first post-input signal D IN_post1Output to the encoding circuit 120.

[0059] Figure 4 FIG. is a circuit diagram showing an example of the encoding circuit 120 of the equalizer 100 according to at least one exemplary embodiment.

[0060] Referring to Figure 4 , the encoding circuit 120 of the equalizer 100 according to at least one exemplary embodiment may include a plurality of NOR gates, a plurality of NAND gates, and / or exclusive-OR (XOR) gates, etc., but is not limited thereto. In Figure 4 at least one exemplary embodiment of Figure 3 , similar to at least one exemplary embodiment of Figure 4 , the equalizer 100 including the encoding circuit 120 may be a 2-tap equalizer, where two output taps are included in the driver 140. However, the exemplary embodiment is not limited thereto, and for example, it may be an equalizer with a greater or smaller number of taps. When the equalizer 100 is a 2-tap equalizer, the encoding circuit 120 may be configured as shown in

[0061] The encoding circuit 120 may perform at least one logic operation on the input signal and / or the delayed signal through a plurality of NOR gates and a plurality of NAND gates to generate a plurality of drive signals.

[0062] The NOR gate IP may receive the ground voltage V SS and the reference input signal D IN_main as inputs, and may perform a NOR operation on the received inputs to output the result of the NOR operation.

[0063] The NOR gate OPM may receive the ground voltage V SS and the output signal of the NOR gate IP as inputs, and may perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate OPM may be the drive signal O_P_D main .

[0064] The NOR gate OPP1 may receive the first post-input signal D IN_post1 and the output signal of the NOR gate IP as inputs, and may perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate OPP1 may be the drive signal O_P_P post1 .

[0065] The NAND gate OPN1 may receive the first post-input signal D IN_post1 and the output signal of the NOR gate IP as inputs, and may perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate OPN1 may be the drive signal O_P_N post1 .

[0066] The NOR gate IN1 can receive the grounded voltage V SS and the first post-input signal D IN_post1 as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation.

[0067] The NOR gate ONM can receive the grounded voltage V SS and the reference input signal D IN_main as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate ONM can be the drive signal O_N_D main .

[0068] The NOR gate ONP1 can receive the reference input signal D IN_main and the output signal of the NOR gate IN1 as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate ONP1 can be the drive signal O_N_P post1 .

[0069] The NAND gate ONN1 can receive the reference input signal D IN_main and the output signal of the NOR gate IN1 as inputs, and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate ONN1 can be the drive signal O_N_N post1 .

[0070] The encoding circuit 120 can generate at least one connection switch signal based on a plurality of drive signals, and the plurality of drive signals are generated based on a delay signal. For example, the encoding circuit 120 can perform an XOR operation on the plurality of drive signals generated based on the delay signal through an XOR gate to generate a connection switch signal, but is not limited thereto.

[0071] The XOR gate X1 can receive the drive signal O_P_P post1 and the drive signal O_P_N post1 as inputs, and can perform an XOR operation on the received inputs to output the result of the XOR operation, and the drive signal O_P_P post1 and the drive signal O_P_N post1 are each generated based on the first post-input signal D as a delay signal IN_post1 . The output of the XOR gate X1 can be the connection switch signal EN post1 .

[0072] Figure 5 is a circuit diagram showing an example of the pre-driver 130 of the equalizer 100 according to at least one exemplary embodiment.

[0073] Refer toFigure 5 According to at least one exemplary embodiment, the pre-driver 130 of the equalizer 100 may include a plurality of NOR gates and a plurality of NAND gates, but is not limited thereto. In Figure 5 at least one exemplary embodiment of Figure 3 and Figure 4 at least one exemplary embodiment of Figure 5 as well, the equalizer 100 including the pre-driver 130 may be a 2-tap equalizer, where two output taps are included in the driver 140, but the exemplary embodiment is not limited thereto, and for example, the equalizer may include a greater or lesser number of taps, etc. When the equalizer 100 is a 2-tap equalizer, the pre-driver 130 may be configured as shown in Figure 5 but is not limited thereto.

[0074] The pre-driver 130 may perform an inversion operation on a plurality of drive signals through a plurality of NOR gates and a plurality of NAND gates to generate a plurality of drive switch signals.

[0075] The plurality of NOR gates included in the pre-driver 130 may receive a ground voltage V SS as one of the inputs. Accordingly, the plurality of NOR gates included in the pre-driver 130 may invert the plurality of drive signals received as the other input to generate a plurality of drive switch signals, and may output the generated plurality of drive switch signals.

[0076] In addition, the plurality of NAND gates included in the pre-driver 130 may receive an operating voltage V DD as one of the inputs. Accordingly, the plurality of NAND gates included in the pre-driver 130 may invert the plurality of drive signals received as the other input to generate a plurality of drive switch signals, and may output the generated plurality of drive switch signals.

[0077] More specifically, the NOR gate PM may receive a ground voltage V SS and a drive signal O_P_D main as inputs, and may perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate PM may be a drive switch signal D main in which the value of the drive signal O_P_D main is inverted.

[0078] The NAND gate PP1 may receive an operating voltage V DD and a drive signal O_P_P post1 as inputs, and may perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate PP1 may be a drive switch signal P_P post1 .

[0079] The NOR gate PN1 can receive the ground voltage V SS and the drive signal O_P_N post1 as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate PN1 can be the drive switch signal P_N post1 .

[0080] The NOR gate NM can receive the ground voltage V SS and the drive signal O_N_D main as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate NM can be the drive switch signal in which the value of the drive signal O_N_D main is inverted .

[0081] The NAND gate NP1 can receive the operating voltage V DD and the drive signal O_N_P post1 as inputs, and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate NP1 can be the drive switch signal N_P post1 .

[0082] The NOR gate NN1 can receive the ground voltage V SS and the drive signal O_N_N post1 as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate NN1 can be the drive switch signal N_N post1 .

[0083] Figure 6 is a circuit diagram showing an example of the driver 140 of the equalizer 100 according to at least one exemplary embodiment.

[0084] Referring to Figure 6 , the driver 140 of the equalizer 100 according to at least one exemplary embodiment may include a first differential circuit 141, a second differential circuit 142, and / or a connection circuit 143, etc., but is not limited thereto. In Figure 6 at least one exemplary embodiment of Figures 3 to 5 , similar to at least one exemplary embodiment of Figure 6 , the equalizer 100 including the driver 140 may be a 2-tap equalizer, where two output taps are included in the driver 140, but is not limited thereto, and for example, the equalizer 100 may have a greater or smaller number of taps, etc. When the equalizer 100 is a 2-tap equalizer, the driver 140 may be configured as shown in

[0085] The first differential circuit 141 can generate a first differential output signal V based on a plurality of drive switch signals outp The first differential circuit 141 may include a main positive output tap PTM and a post positive output tap PT1, etc.

[0086] The main positive output tap PTM and the post positive output tap PT1 can generate a first differential output signal V based on a plurality of drive switch signals outp .

[0087] The main positive output tap PTM may include a first output switching element PMPS and a second output switching element PMNS, but is not limited thereto. The first output switching element PMPS may be a switching element having a first polarity (e.g., positive polarity, etc.), and in at least one exemplary embodiment, the first output switching element PMPS may be a P-channel metal oxide semiconductor (PMOS), but is not limited thereto. The second output switching element PMNS may be a switching element having a second polarity (e.g., negative polarity, etc.), and in at least one exemplary embodiment, the second output switching element PMNS may be an N-channel metal oxide semiconductor (NMOS), but is not limited thereto.

[0088] The first output switching element PMPS may receive a drive switch signal D through a gate terminal main The first output switching element PMPS may be connected to an operating voltage terminal V through a first terminal (e.g., a drain terminal, etc.) DD The second output switching element PMNS may receive a drive switch signal D through a gate terminal main The second output switching element PMNS may be connected to a second terminal (e.g., a source terminal, etc.) of the first output switching element PMPS through a first terminal (e.g., a drain terminal, etc.). In addition, the second output switching element PMNS may be connected to a ground voltage terminal V through a second terminal (e.g., a source terminal, etc.) SS In addition, the output signal of the main positive output tap PTM may be output through the second terminal of the first output switching element PMPS and the first terminal of the second output switching element PMNS. The output signal of the main positive output tap PTM may configure the first differential output signal V outp .

[0089] The post positive output tap PT1 may include a first output switching element PPS1 and a second output switching element PNS1, but is not limited thereto. The first output switching element PPS1 may be a switching element having a first polarity (e.g., positive polarity, etc.), and in at least one exemplary embodiment, the first output switching element PPS1 may be a PMOS, but is not limited thereto. The second output switching element PNS1 may be a switching element having a second polarity (e.g., negative polarity, etc.), and in at least one exemplary embodiment, the second output switching element PNS1 may be an NMOS, but is not limited thereto.

[0090] The first output switching element PPS1 may receive a driving switching signal P_P through a gate terminal post1 . The first output switching element PPS1 may be connected to an operating voltage terminal V through a first terminal (e.g., drain terminal, etc.) DD . The second output switching element PNS1 may receive a driving switching signal P_N through a gate terminal post1 . The second output switching element PNS1 may be connected to a second terminal (e.g., source terminal, etc.) of the first output switching element PPS1 through a first terminal (e.g., drain terminal, etc.). In addition, the second output switching element PNS1 may be connected to a ground voltage terminal V through a second terminal (e.g., source terminal, etc.) SS . Further, the output signal of the post positive output tap PT1 may be output through the second terminal of the first output switching element PPS1 and the first terminal of the second output switching element PNS1. The output signal of the post positive output tap PT1 may configure a first differential output signal V outp .

[0091] The output signal of the main positive output tap PTM and the output signal of the post positive output tap PT1 may be summed to configure a first differential output signal V outp .

[0092] The second differential circuit 142 may generate a second differential output signal V based on a plurality of driving switching signals outn . The second differential circuit 142 may include a main negative output tap NTM and a post negative output tap NT1, but is not limited thereto.

[0093] The main negative output tap NTM and the post negative output tap NT1 may generate a second differential output signal V based on a plurality of driving switching signals outn .

[0094] The main negative output tap NTM may include a first output switching element NMPS and a second output switching element NMNS, etc. The first output switching element NMPS may be a switching element having a first polarity (e.g., positive polarity, etc.), and in at least one exemplary embodiment, the first output switching element NMPS may be a PMOS, but is not limited thereto. The second output switching element NMNS may be a switching element having a second polarity (e.g., negative polarity, etc.), and in at least one exemplary embodiment, the second output switching element NMNS may be an NMOS, but is not limited thereto.

[0095] The first output switching element NMPS may receive a driving switch signal through a gate terminal . The first output switching element NMPS may be connected to an operating voltage terminal V through a first terminal (e.g., a drain terminal, etc.) DD The second output switching element NMNS may receive a driving switch signal through a gate terminal . The second output switching element NMNS may be connected to a second terminal (e.g., a source terminal, etc.) of the first output switching element NMPS through a first terminal (e.g., a drain terminal, etc.). In addition, the second output switching element NMNS may be connected to a ground voltage terminal V through a second terminal (e.g., a source terminal, etc.) SS . Additionally, the output signal of the main negative output tap NTM may be output through the second terminal of the first output switching element NMPS and the first terminal of the second output switching element NMNS. The output signal of the main negative output tap NTM may configure a second differential output signal V outn .

[0096] The post negative output tap NT1 may include a first output switching element NPS1 and a second output switching element NNS1, but is not limited thereto. The first output switching element NPS1 may be a switching element having a first polarity (e.g., positive polarity, etc.), and in at least one exemplary embodiment, the first output switching element NPS1 may be a PMOS, but is not limited thereto. The second output switching element NNS1 may be a switching element having a second polarity (e.g., negative polarity, etc.), and in at least one exemplary embodiment, the second output switching element NNS1 may be an NMOS, but is not limited thereto.

[0097] The first output switching element NPS1 may receive a driving switch signal N_P through a gate terminal post1 . The first output switching element NPS1 may be connected to an operating voltage terminal V through a first terminal (e.g., a drain terminal, etc.) DD The second output switching element NNS1 may receive a driving switch signal N_N through a gate terminal post1。The second output switching element NNS1 can be connected to the second terminal (e.g., source terminal, etc.) of the first output switching element NPS1 through the first terminal (e.g., drain terminal, etc.). In addition, the second output switching element NNS1 can be connected to the ground voltage terminal V through the second terminal (e.g., source terminal, etc.) SS 。In addition, the output signal of the post negative output tap NT1 can be output through the second terminal of the first output switching element NPS1 and the first terminal of the second output switching element NNS1. The output signal of the post negative output tap NT1 can configure the second differential output signal V outn 。

[0098] The output signal of the main negative output tap NTM and the output signal of the post negative output tap NT1 can be summed to configure the second differential output signal V outn 。

[0099] According to at least one example embodiment, the first output switching element PMPS included in the main positive output tap PTM, the second output switching element PMNS included in the main positive output tap PTM, the first output switching element NMPS included in the main negative output tap NTM, and the second output switching element NMNS included in the main negative output tap NTM can have the same coefficient (e.g., amplification coefficient). That is to say, the main positive output tap PTM and the main negative output tap NTM can have the same coefficient.

[0100] In addition, the first output switching element PPS1 included in the post positive output tap PT1, the second output switching element PNS1 included in the post positive output tap PT1, the first output switching element NPS1 included in the post negative output tap NT1, and the second output switching element NNS1 included in the post negative output tap NT1 can have the same coefficient. That is to say, the post positive output tap PT1 and the post negative output tap NT1 can have the same coefficient.

[0101] The connection circuit 143 can adjust the connection between the first differential circuit 141 and the second differential circuit 142 based on the connection switch signal.

[0102] The connection circuit 143 can include a connection switch element CS1, but is not limited thereto. The connection switch element CS1 can be based on the connection switch signal EN post1 to adjust the connection between the post positive output tap PT1 and the post negative output tap NT1.

[0103] The connection switch element CS1 can be a switch element with a second polarity (e.g., negative polarity, etc.), and in at least one example embodiment, the connection switch element CS1 can be an NMOS, but is not limited thereto.

[0104] The connection switch element CS1 can receive a connection switch signal EN through a gate terminal. post1 The connection switch element CS1 can be connected to a node between "the first output switch element PPS1 included in the post positive output tap PT1" and "the second output switch element PNS1 included in the post positive output tap PT1" through a first terminal (e.g., a drain terminal, etc.). The connection switch element CS1 can be connected to a node between "the first output switch element NPS1 included in the post negative output tap NT1" and "the second output switch element NNS1 included in the post negative output tap NT1" through a second terminal (e.g., a source terminal, etc.).

[0105] In at least one exemplary embodiment, when the post positive output tap PT1 and the post negative output tap NT1 are in an off state, the connection switch element CS1 can connect the post positive output tap PT1 to the post negative output tap NT1. In addition, the connection switch element CS1 can have the same coefficient as the coefficients of the multiple switch elements included in each of the post positive output tap PT1 and the post negative output tap NT1. Therefore, even when the post positive output tap PT1 and the post negative output tap NT1 are in an off state, the output resistance based on the driver 140 can be maintained, so that impedance matching can be accurately performed and / or the impedance matching of the driver 140 can be improved, etc.

[0106] Figures 7A to 7C is a graph showing the output of a circuit for a signal applied to Figures 3 to 6 the equalizer shown in

[0107] Referring to Figure 7A , the equalizer 100 can have a structure according to Figures 3 to 6 one or more exemplary embodiments, and when the input signal IN input to the delay circuit 110 of the equalizer 100 has a value of 1 during the time interval between t2 and t3 and has a value of -1 during all other time intervals, the values of the signals output from the delay circuit 110 and the encoding circuit 120 can be checked and / or evaluated, but not limited thereto. In Figure 7A , it is assumed that the intervals between t0 and t1, between t1 and t2, between t2 and t3, between t3 and t4, and between t4 and t5 are equal to each other.

[0108] The delay circuit 110 can output a reference input signal D that is the same as the input signal IN IN_main . In addition, the delay circuit 110 can delay the input signal IN through the latch 111 to output a signal that has a value of 1 during the time interval between t3 and t4 and has a value of -1 during all other time intervals as a first post-input signal D IN_post1 .

[0109] The encoding circuit 120 can perform a NOR operation by using the NOR gate IP on the ground voltage V SS and the reference input signal D IN_main and can perform a NOR operation by using the NOR gate OPM on the ground voltage V SS and the output signal of the NOR gate IP, so as to output the drive signal O_P_D main The drive signal O_P_D main has a value of 1 during the time interval between t2 and t3 and has a value of 0 during all other time intervals.

[0110] The encoding circuit 120 can output the drive signal O_P_P by performing a NOR operation on the first post-input signal D IN_post1 and the output signal of the NOR gate IP by using the NOR gate OPP1 post1 The drive signal O_P_P post1 has a value of 1 during the time interval between t2 and t3 and has a value of 0 during all other time intervals.

[0111] The encoding circuit 120 can output the drive signal O_P_N by performing a NAND operation on the first post-input signal D IN_post1 and the output signal of the NOR gate IP by using the NAND gate OPN1 post1 The drive signal O_P_N post1 has a value of 0 during the time interval between t3 and t4 and has a value of 1 during all other time intervals.

[0112] The encoding circuit 120 can output the connection switch signal EN by performing an XOR operation on the output signal of the NOR gate OPP1 and the output signal of the NAND gate OPN1 by using the XOR gate X1 post1 The connection switch signal EN post1 has a value of 0 during the time interval between t2 and t4 and has a value of 1 during all other time intervals.

[0113] The encoding circuit 120 can output the drive signal O_N_D by performing a NOR operation on the ground voltage V SS and the reference input signal D IN_main by using the NOR gate ONM to output the drive signal O_N_D main The drive signal O_N_D main has a value of 0 during the time interval between t2 and t3 and has a value of 1 during all other time intervals.

[0114] The encoding circuit 120 can use the NOR gate IN1 on the ground voltage V SS and the first post-input signal D IN_post1Perform a NOR operation and output the drive signal O_N_P by performing a NOR operation on the reference input signal D IN_main and the output signal of the NOR gate IN1, such that the drive signal O_N_P post1 has a value of 0 in the time interval between t2 and t3 and a value of 1 in all other time intervals. post1 The encoding circuit 120 can output the drive signal O_N_N by performing a NAND operation on the reference input signal D

[0115] and the output signal of the NOR gate IN1 using the NAND gate ONN1 IN_main such that the drive signal O_N_N post1 has a value of 1 in the time interval between t3 and t4 and a value of 0 in all other time intervals. post1 Referring

[0116] to Figure 7B the equalizer 100 can have a structure according to Figures 3 to 6 one or more exemplary embodiments and, when multiple drive signals applied to the pre - driver 130 of the equalizer 100 are as Figure 7A shown, the value of the signal output from the pre - driver 130 can be checked and / or evaluated.

[0117] As referred to above Figure 5 the pre - driver 130 can invert multiple drive signals to generate and output multiple drive switch signals.

[0118] The pre - driver 130 can invert the drive signal O_P_D main using the NOR gate PM to output the drive switch signal D main such that the drive switch signal D main has a value of 0 in the time interval between t2 and t3 and a value of 1 in all other time intervals.

[0119] The pre - driver 130 can invert the drive signal O_P_P post1 using the NAND gate PP1 to output the drive switch signal P_P post1 such that the drive switch signal P_P post1 has a value of 0 in the time interval between t2 and t3 and a value of 1 in all other time intervals.

[0120] The pre - driver 130 can invert the drive signal O_P_N post1 using the NOR gate PN1 to output the drive switch signal P_N post1 such that the drive switch signal P_N post1The time interval between t3 and t4 has a value of 1 and has a value of 0 at all other time intervals.

[0121] The pre-driver 130 can output a driving switch signal by inverting the driving signal O_N_D using the NOR gate NM main The driving switch signal The time interval between t2 and t3 has a value of 1 and has a value of 0 at all other time intervals.

[0122] The pre-driver 130 can output a driving switch signal N_P by inverting the driving signal O_N_P using the NAND gate NP1 post1 post1 The driving switch signal N_P post1 The time interval between t2 and t3 has a value of 1 and has a value of 0 at all other time intervals.

[0123] The pre-driver 130 can output a driving switch signal N_N by inverting the driving signal O_N_N using the NOR gate NN1 post1 post1 The driving switch signal N_N post1 The time interval between t3 and t4 has a value of 0 and has a value of 1 at all other time intervals.

[0124] Referring Figure 7C to, the equalizer 100 may have a structure according to one or more exemplary embodiments of Figures 3 to 6 and when multiple driving switch signals of the driver 140 applied to the equalizer 100 are as shown in Figure 7B , the value of the signal output from the driver 140 can be checked and / or evaluated. In this case, in the driver 140, the main positive output tap PTM and the main negative output tap NTM may have a0 as a coefficient, and the post positive output tap PT1 and the post negative output tap NT1 may have a1 as a coefficient, but not limited thereto.

[0125] The first output switch element PMPS included in the main positive output tap PTM may be turned on during the time interval between t2 and t3 based on the driving switch signal D main . The second output switch element PMNS included in the main positive output tap PTM may be turned off during the time interval between t2 and t3 based on the driving switch signal D main . Therefore, the output signal V of the main positive output tap PTM outp_main may have a value of a0 during the time interval between t2 and t3 and may have a value of 0 at all other time intervals.

[0126] ​​​The first output switching element PPS1 included in the post positive output tap PT1 can be based on the drive switching signal P_P post1 is turned on during the time interval between t2 and t3. The second output switching element PNS1 included in the post positive output tap PT1 can be based on the drive switching signal P_N post1 is turned on during the time interval between t3 and t4. Therefore, the output signal V of the post positive output tap PT1 outp_post1 can have the value a1 during the time interval between t2 and t3, can have the value 0 during the time interval between t3 and t4, and can be in the off state without output during all other time intervals.

[0127] The third output switching element NMPS included in the main negative output tap NTM can be based on the drive switching signal is turned off during the time interval between t2 and t3. The fourth output switching element NMNS included in the main negative output tap NTM can be based on the drive switching signal is turned on during the time interval between t2 and t3. Therefore, the output signal V of the main negative output tap NTM outn_main can have the value 0 during the time interval between t2 and t3, and can have the value a0 during all other time intervals.

[0128] The third output switching element NPS1 included in the post negative output tap NT1 can be based on the drive switching signal N_P post1 is turned off during the time interval between t2 and t3. The fourth output switching element NNS1 included in the post negative output tap NT1 can be based on the drive switching signal N_N post1 is turned off during the time interval between t3 and t4. Therefore, the output signal V of the post negative output tap NT1 outn_post1 can have the value 0 during the time interval between t2 and t3, can have the value a1 during the time interval between t3 and t4, and can be in the off state without output during all other time intervals.

[0129] Therefore, the output signal V of the main positive output tap PTM outp_main and the output signal V of the post positive output tap PT1 outp_post1 can be summed to configure the first differential output signal V outp , and the output signal V of the main negative output tap NTM outn_main and the output signal V of the post negative output tap NT1 outn_post1 can be summed to configure the second differential output signal V outn . At this time, the first differential output signal V outp as the final output signal of the equalizer 100 and the second differential output signal V outnThe difference between them may have a value of -a0 for the time interval between t0 and t2, may have a value of a0 + a1 for the time interval between t2 and t3, may have a value of -a0 - a1 for the time interval between t3 and t4, and may have a value of -a0 for the time interval between t4 and t5.

[0130] Figure 8 is a circuit diagram showing a resistor equivalent circuit of the driver 140 of the equalizer 100 according to at least one exemplary embodiment.

[0131] Referring to Figure 8 , when the equalizer 100 has a structure according to one or more of the exemplary embodiments of Figures 3 to 6 , the resistor equivalent circuit of the driver 140 of the equalizer 100 can be checked and / or evaluated. In this case, N can be the coefficient of the main positive output tap PTM and the main negative output tap NTM, and (15 - N) can be the coefficient of the post positive output tap PT1 and the post negative output tap NT1.

[0132] In this case, the output resistance of the driver 140 can be expressed by the following Equation 1, but the exemplary embodiments are not limited thereto.

[0133] [Equation 1]

[0134] That is, it can be seen that regardless of the coefficients of the main positive output tap PTM and the main negative output tap NTM, the coefficients of the post positive output tap PT1 and the post negative output tap NT1, and the state of the switching elements included in the driver 140, the output resistance Impedance out of the driver 140 is constant. R1, R2, and R3 can be the equivalent resistances of the driver 140.

[0135] As described above, by using the equalizer 100 according to at least one exemplary embodiment, the output resistance can be maintained, so that impedance matching can be accurately performed and / or improved impedance matching can be achieved, thereby reducing and / or preventing signal reflection and / or distortion, etc.

[0136] Figure 9 is a circuit diagram showing another example of the delay circuit 110 of the equalizer 100 according to at least one exemplary embodiment.

[0137] Referring to Figure 9 , the delay circuit 110 of the equalizer 100 according to at least one exemplary embodiment may include a plurality of latches 111_1 to 111_n+1. In Figure 9In at least one exemplary embodiment, the equalizer 100 including the delay circuit 110 may be an (n + 2)-tap equalizer, where n + 2 output taps are included in the driver 140. When the equalizer 100 is an (n + 2)-tap equalizer, the delay circuit 110 may include n + 1 latches 111_1 to 111_n+1.

[0138] The delay circuit 110 of the equalizer 100 according to at least one exemplary embodiment may include a plurality of latches 111_1 to 111_n+1 (where n may be a positive integer). The plurality of latches 111_1 to 111_n+1 may delay an input signal IN by a desired and / or predetermined delay time D to generate a delayed signal. For example, when the input signal IN is x[0] and the delay time D of each of the plurality of latches 111_1 to 111_n+1 is 1, each of the plurality of latches 111_1 to 111_n+1 may output x[1], x[2] to x[n + 1] obtained by a 1-time delay, respectively.

[0139] In Figure 9 at least one exemplary embodiment, the delay circuit 110 may use the input signal IN that has not passed through the plurality of latches 111_1 to 111_n+1 as the input signal D IN_pre and output it to the encoding circuit 120. The delay circuit 110 may use the input signal IN that has passed through the first latch 111_1 among the plurality of latches 111_1 to 111_n+1 as the reference input signal D IN_main and output it to the encoding circuit 120. The delay circuit 110 may use the input signal IN that has passed through the first latch 111_1 and the second latch 111_2 among the plurality of latches 111_1 to 111_n+1 as the first post-input signal D IN_post1 and output it to the encoding circuit 120. Similarly, the delay circuit 110 may use the input signal IN that has passed through the nth latch 111_n (not shown) among the plurality of latches 111_1 to 111_n+1 as the nth post-input signal D IN_postn-1 and output it to the encoding circuit 120.

[0140] Figure 10A And Figure 10B is a circuit diagram showing another example of the encoding circuit 120 of the equalizer 100 according to at least one exemplary embodiment.

[0141] Referring to Figure 10A and Figure 10B , the encoding circuit 120 of the equalizer 100 according to at least one exemplary embodiment may include a plurality of NOR gates, a plurality of NAND gates, and / or XOR gates, etc., but is not limited thereto. In Figure 10A and Figure 10B at least one exemplary embodiment, similar to Figure 9At least one example embodiment, where the equalizer 100 including the coding circuit 120 can be a (n + 2)-tap equalizer. Among them, n + 2 output taps are included in the driver 140, but the example embodiment is not limited thereto. When the equalizer 100 is a (n + 2)-tap equalizer, the coding circuit 120 can be configured as shown in Figure 10A and Figure 10B , but not limited thereto.

[0142] First, referring to Figure 10A , the NOR gate IP, NOR gate OPM, NOR gate OPP1, NAND gate OPN1, and / or XOR gate X1 included in the coding circuit 120_1 can respectively perform the same operations as those described above with reference to Figure 4 . Therefore, for clarity and conciseness, the description of these components will be omitted, but the example embodiment is not limited thereto.

[0143] The NOR gate OPP0 can receive the pre-input signal D IN_pre and the output signal of the NOR gate IP as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate OPP0 can be the driving signal O_P_P pre .

[0144] The NAND gate OPN0 can receive the pre-input signal D IN_pre and the output signal of the NOR gate IP as inputs, and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate OPN0 can be the driving signal O_P_N pre .

[0145] The NOR gate OPPn (where n can be a natural number from 1 to n) can receive the n-th subsequent input signal D IN_postn and the output signal of the NOR gate IP as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate OPPn can be the driving signal O_P_P postn .

[0146] The NAND gate OPNn can receive the n-th subsequent input signal D IN_postn and the output signal of the NOR gate IP as inputs, and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate OPNn can be the driving signal O_P_N postn .

[0147] The XOR gate X0 can receive the driving signal O_P_P IN_pre and the driving signal O_P_N pre respectively generated based on the pre-input signal D preas an input, and can perform an XOR operation on the received input to output the result of the XOR operation. The output of the XOR gate X0 can be the connection switch signal EN pre .

[0148] The XOR gate Xn can receive respective driving signals O_P_P IN_postn generated based on the (n + 1)-th input signal D postn and the driving signal O_P_N postn as an input, and can perform an XOR operation on the received input to output the result of the XOR operation. The output of the XOR gate Xn can be the connection switch signal EN postn .

[0149] Next, referring to Figure 10B , the NOR gate IN1, the NOR gate ONM, the NOR gate ONP1, and the NAND gate ONN1 included in the encoding circuit 120_2 can respectively perform the same operations as those described above with reference to Figure 4 , and thus, for clarity and conciseness, the description of these components will be omitted, but the example embodiments are not limited thereto.

[0150] The NOR gate ONP0 can receive the reference input signal D IN_main and the output signal of the NOR gate IN0 as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate ONP0 can be the driving signal O_N_P pre .

[0151] The NAND gate ONN0 can receive the reference input signal D IN_main and the output signal of the NOR gate IN0 as inputs, and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate ONN0 can be the driving signal O_N_N pre .

[0152] The NOR gate INn can receive the ground voltage V SS and the pre-input signal D IN_postn as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation.

[0153] The NOR gate ONPn can receive the reference input signal D IN_main and the output signal of the NOR gate INn as inputs, and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate ONPn can be the driving signal O_N_P postn .

[0154] The NAND gate ONNn can receive the reference input signal D IN_mainThe output signals of the NOR gate INn are used as inputs, and a NAND operation can be performed on the received inputs to output the result of the NAND operation. The output of the NAND gate ONNn can be the drive signal O_N_N postn .

[0155] Figure 11 FIG. is a circuit diagram showing another example of the pre-driver 130 of the equalizer 100 according to at least one exemplary embodiment.

[0156] Referring to Figure 11 , the pre-driver 130 of the equalizer 100 according to at least one exemplary embodiment may include a plurality of NOR gates and a plurality of NAND gates, but is not limited thereto. In Figure 11 at least one exemplary embodiment of, similar to Figure 9 , Figure 10A and Figure 10B at least one exemplary embodiment of, the equalizer 100 including the pre-driver 130 may be an (n + 2)-tap equalizer, where n + 2 output taps are included in the driver 140 or the like. When the equalizer 100 is an (n + 2)-tap equalizer, the pre-driver 130 may be configured as shown in Figure 11 , but is not limited thereto.

[0157] The NOR gate PM, the NAND gate PP1, the NOR gate PN1, the NOR gate NM, the NAND gate NP1, and the NOR gate NN1 may respectively perform the same operations as those described above with reference to Figure 5 , and thus, for clarity and conciseness, the description of these components will be omitted, but the exemplary embodiments are not limited thereto.

[0158] The NAND gate PP0 may receive the operating voltage V DD and the drive signal O_P_P pre as inputs, and may perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate PP0 may be the drive switch signal P_P pre .

[0159] The NOR gate PN0 may receive the ground voltage V SS and the drive signal O_P_N pre as inputs, and may perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate PN0 may be the drive switch signal P_N pre .

[0160] The NAND gate NP0 may receive the operating voltage V DD and the drive signal O_N_P preas an input and can perform a NAND operation on the received input to output the result of the NAND operation. The output of the NAND gate NP0 can be the drive switch signal N_P pre .

[0161] The NOR gate NN0 can receive the ground voltage V SS and the drive signal O_N_N pre as inputs and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate NN0 can be the drive switch signal N_N pre .

[0162] The NAND gate PPn can receive the operating voltage V DD and the drive signal O_P_P postn as inputs and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate PPn can be the drive switch signal P_P postn .

[0163] The NOR gate PNn can receive the ground voltage V SS and the drive signal O_P_N postn as inputs and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate PNn can be the drive switch signal P_N postn .

[0164] The NAND gate NPn can receive the operating voltage V DD and the drive signal O_N_P postn as inputs and can perform a NAND operation on the received inputs to output the result of the NAND operation. The output of the NAND gate NPn can be the drive switch signal N_P postn .

[0165] The NOR gate NNn can receive the ground voltage V SS and the drive signal O_N_N postn as inputs and can perform a NOR operation on the received inputs to output the result of the NOR operation. The output of the NOR gate NNn can be the drive switch signal N_N postn .

[0166] Figure 12 is a circuit diagram showing another example of the driver 140 of the equalizer 100 according to at least one exemplary embodiment.

[0167] Referring to Figure 12 , the driver 140 of the equalizer 100 according to at least one exemplary embodiment may include a first differential circuit 141, a second differential circuit 142, and / or a connection circuit 143, etc., but is not limited thereto. InFigure 12 In at least one exemplary embodiment similar to Figures 9 to 11 In at least one exemplary embodiment, equalizer 100 including driver 140 may be an (n + 2)-tap equalizer, where (n + 2) output taps are included in driver 140, but are not limited thereto. When equalizer 100 is an (n + 2)-tap equalizer, driver 140 may be configured as shown in Figure 12 but is not limited thereto.

[0168] The first differential circuit 141 may include a plurality of positive output taps PTM and PT0 to PTn. The plurality of positive output taps PTM and PT0 to PTn may generate a first differential output signal V based on a plurality of drive switch signals outp .

[0169] The structure and operation of each of the main positive output tap PTM and the first post positive output tap PT1 may be as described above with reference to Figure 6 and thus, for clarity and conciseness, their description will be omitted, but the exemplary embodiments are not limited thereto.

[0170] The pre positive output tap PT0 may include a first output switching element PPS0 and a second output switching element PNS0. The first output switching element PPS0 may be a switching element having a first polarity (e.g., positive polarity, etc.). The second output switching element PNS0 may be a switching element having a second polarity (e.g., negative polarity, etc.).

[0171] The first output switching element PPS0 may receive a drive switch signal P_P through a gate terminal pre . The second output switching element PNS0 may receive a drive switch signal P_N through a gate terminal pre . The structure and operation of each of the first output switching element PPS0 and the second output switching element PNS0 of the pre positive output tap PT0 may be the same as those of each of the first output switching element PPS1 and the second output switching element PNS1 of the first post positive output tap PT1, but are not limited thereto.

[0172] The output signal of the pre positive output tap PT0 may be output through a second terminal of the first output switching element PPS0 and a first terminal of the second output switching element PNS0 of the pre positive output tap PT0. The output signal of the pre positive output tap PT0 may configure the first differential output signal V outp .

[0173] The n-th post positive output tap PTn may include a first output switching element PPSn and a second output switching element PNSn. The first output switching element PPSn may be a switching element having a first polarity (e.g., positive polarity, etc.). The second output switching element PNSn may be a switching element having a second polarity (e.g., negative polarity, etc.).

[0174] The first output switching element PPSn may receive a drive switching signal P_P through a gate terminal postn 。The second output switching element PNSn may receive a drive switching signal P_N through a gate terminal postn 。The structure and operation of each of the first output switching element PPSn and the second output switching element PNSn of the n-th post positive output tap PTn may be the same as those of each of the first output switching element PPS1 and the second output switching element PNS1 of the first post positive output tap PT1, but are not limited thereto.

[0175] The output signal of the n-th post positive output tap PTn may be output through a second terminal of the first output switching element PPSn and a first terminal of the second output switching element PNSn of the n-th post positive output tap PTn. The output signal of the n-th post positive output tap PTn may configure a first differential output signal V outp 。

[0176] The output signal of the main positive output tap PTM, the output signal of the pre positive output tap PT0, and the output signals of the first post positive output tap PT1 to the n-th post positive output tap PTn may be summed to configure a first differential output signal V outp 。

[0177] The second differential circuit 142 may include a plurality of negative output taps NTM and NT0 to NTn. The plurality of negative output taps NTM and NT0 to NTn may generate a second differential output signal V based on a plurality of drive switching signals outn 。

[0178] The structure and operation of each of the main negative output tap NTM and the first post negative output tap NT1 may be as described above with reference to Figure 6 ,therefore, for clarity and conciseness, their descriptions will be omitted, but the exemplary embodiments are not limited thereto.

[0179] The pre negative output tap NT0 may include a first output switching element NPS0 and a second output switching element NNS0. The first output switching element NPS0 may be a switching element having a first polarity (e.g., positive polarity, etc.). The second output switching element NNS0 may be a switching element having a second polarity (e.g., negative polarity, etc.).

[0180] The first output switching element NPS0 can receive a driving switching signal N_P through the gate terminal pre The second output switching element NNS0 can receive a driving switching signal N_N through the gate terminal pre The structure and operation of each of the first output switching element NPS0 and the second output switching element NNS0 of the pre-negative output tap NT0 can be the same as those of each of the first output switching element NPS1 and the second output switching element NNS1 of the first post-negative output tap NT1, but are not limited thereto

[0181] The output signal of the pre-negative output tap NT0 can be output through the second terminal of the first output switching element NPS0 and the first terminal of the second output switching element NNS0 of the pre-negative output tap NT0. The output signal of the pre-negative output tap NT0 can configure the second differential output signal V outn

[0182] The nth post-negative output tap NTn can include a first output switching element NPSn and a second output switching element NNSn. The first output switching element NPSn can be a switching element with a first polarity (e.g., positive polarity, etc.). The second output switching element NNSn can be a switching element with a second polarity (e.g., negative polarity, etc.)

[0183] The first output switching element NPSn can receive a driving switching signal N_P through the gate terminal postn The second output switching element NNSn can receive a driving switching signal N_N through the gate terminal postn The structure and operation of each of the first output switching element NPSn and the second output switching element NNSn of the nth post-negative output tap NTn can be the same as those of each of the first output switching element NPS1 and the second output switching element NNS1 of the first post-negative output tap NT1, but are not limited thereto

[0184] The output signal of the nth post-negative output tap NTn can be output through the second terminal of the first output switching element NPSn and the first terminal of the second output switching element NNSn of the nth post-negative output tap NTn. The output signal of the nth post-negative output tap NTn can configure the second differential output signal V outn

[0185] The output signal of the main negative output tap NTM, the output signal of the pre-negative output tap NT0, and the output signals of the first post-negative output tap NT1 to the nth post-negative output tap NTn can be summed to configure the second differential output signal V outn

[0186] ​​​In this case, the first output switching element PPS0 included in the prepositive output tap PT0, the second output switching element PNS0 included in the prepositive output tap PT0, the first output switching element NPS0 included in the prenegative output tap NT0, and the second output switching element NNS0 included in the prenegative output tap NT0 may have the same coefficient. That is to say, the prepositive output tap PT0 and the prenegative output tap NT0 may have the same coefficient.

[0187] In addition, the first output switching element PPSn included in the n-th postpositive output tap PTn, the second output switching element PNSn included in the n-th postpositive output tap PTn, the first output switching element NPSn included in the n-th prenegative output tap NTn, and the second output switching element NNSn included in the n-th prenegative output tap NTn may have the same coefficient. That is to say, the n-th postpositive output tap PTn and the n-th prenegative output tap NTn may have the same coefficient.

[0188] The connection circuit 143 can adjust the connection between the first differential circuit 141 and the second differential circuit 142 based on one or more connection switch signals.

[0189] The connection circuit 143 may include one or more connection switch elements CS0 to CSn. The number of one or more connection switch elements CS0 to CSn may be less than the number of taps included in the equalizer 100, but is not limited thereto. One or more connection switch elements CS0 to CSn may be based on the connection switch signals EN pre and EN post1 to EN postn respectively adjust the connection between the prepositive output tap PT0 and the prenegative output tap NT0 and the connections between the postpositive output taps PT1 to PTn and the corresponding prenegative output taps NT1 to NTn.

[0190] One or more connection switch elements CS0 to CSn may be switch elements having a second polarity (e.g., negative polarity, etc.), and in at least one exemplary embodiment, one or more connection switch elements CS0 to CSn may all be NMOS, but are not limited thereto.

[0191] One or more connection switch elements CS0 to CSn may respectively receive the connection switch signals EN pre and EN post1 to EN postnOne or more connection switch elements CS0 to CSn may be respectively connected, through their respective first terminals (e.g., drain terminals, etc.), to nodes between a first output switch element PPS0 to PPSn included in each of a plurality of positive output taps PT0 to PTn and a second output switch element PNS0 to PNSn included in each of the plurality of positive output taps PT0 to PTn. One or more connection switch elements CS0 to CSn may be respectively connected, through their second terminals (e.g., source terminals, etc.), to nodes between a first output switch element NPS0 to NPSn included in each of a plurality of negative output taps NT0 to NTn and a second output switch element NNS0 to NNSn included in each of the plurality of negative output taps NT0 to NTn.

[0192] In at least one example embodiment, one or more connection switch elements CS0 to CSn may connect the connected plurality of positive output taps PT0 to PTn to the connected plurality of negative output taps NT0 to NTn when the connected plurality of positive output taps PT0 to PTn and the connected plurality of negative output taps NT0 to NTn are in a disconnected state. Further, the connection switch element CS1 may have a coefficient same as that of each of the plurality of switch elements included in the plurality of positive output taps PT0 to PTn and the plurality of negative output taps NT0 to NTn. Thus, even when the plurality of positive output taps PT0 to PTn and the plurality of negative output taps NT0 to NTn are in a disconnected state, the output resistance based on the driver 140 may be maintained, and thus, impedance matching may be accurately performed and / or the impedance matching of the equalizer may be improved.

[0193] Figure 13 FIG. is a diagram showing a system 1000 including an equalizer according to at least one example embodiment.

[0194] Referring to Figure 13 , the memory device 1100 and the host device 1200 may communicate with each other through at least one interface 1300, and the memory device 1100 may include a controller 1110 (e.g., processing circuitry, etc.) and / or a memory 1120, etc., but the example embodiment is not limited thereto.

[0195] The interface 1300 may use electrical signals and / or optical signals, and in at least one example embodiment, the interface 1300 may be implemented as, for example, a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATA-e) interface, a Serial Attached SCSI (SAS) (serial attached SCSI) interface, etc., or any combination thereof. The interface 1300 may include, such as Figure 2The equalizer 100 shown in [figure reference], but not limited thereto. Therefore, when the output resistance of the interface 1300 is maintained, impedance matching can be accurately performed and / or impedance matching can be improved, thereby reducing and / or preventing signal reflection and / or distortion.

[0196] In at least one example embodiment, the memory device 1100 may be coupled and / or removably coupled to the host device 1200 and may communicate with the host device 1200. The memory 1120 may be a non-volatile memory, and the memory device 1100 may be referred to as a storage system. For example, in at least one example embodiment, the memory device 1100 may be implemented as, for example, a solid state drive (or solid state disk) (SSD), an embedded SSD (eSSD), a multimedia card (MMC), and / or an embedded MMC (eMMC), etc., but not limited thereto. The controller 1110 may control the memory 1120 in response to requests received from the host device 1200 via the interface 1300 or the like.

[0197] Figure 14 is a diagram showing a system on chip (SoC) 2000 including an equalizer according to at least one example embodiment.

[0198] Referring to Figure 14 , the SoC 2000 may represent a computing system and / or an integrated circuit in which components of another electronic system are integrated. For example, an application processor (AP) as a type of SoC 2000 may include at least one processor and other elements for performing other functions. As Figure 14 shown, the SoC 2000 may include a core 2100 (e.g., a processor core, etc.), a digital signal processor (DSP) 2200, a graphics processing unit (GPU) 2300, an internal memory (e.g., an embedded memory) 2400, a communication interface 2500, and / or a memory interface 2600, etc., but not limited thereto, and for example, the SoC 2000 may include a greater or lesser number of components, etc. The elements of the SoC 2000 may communicate with each other via a bus 2700. According to some example embodiments, one or more of the SoC 2000, the core 2100, the DSP 2200, the GPU 2300, the internal memory 2400, the communication interface 2500, and / or the memory interface 2600, etc., may be implemented as processing circuitry. The processing circuitry may include: hardware or a hardware circuit including a logic circuit; a hardware / software combination (such as a processor executing software and / or firmware); or a combination thereof. For example, the processing circuitry may more specifically include, but not be limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc., but not limited thereto.

[0199] The core 2100 can process computer-readable instructions and can control the operations of components included in the SoC 2000, etc. For example, the core 2100 can process a series of computer-readable instructions, so as to drive an operating system (OS) and / or applications that can execute the OS, etc. The DSP 2200 can process digital signals (e.g., digital signals provided through the communication interface 2500), so as to generate useful and / or desired data, etc. The GPU 2300 can generate data for an image to be displayed by a display device according to image data provided from the internal memory 2400 and / or the memory interface 2600, and in addition, can encode the image data, etc. The internal memory 2400 can store data required for the operations of the core 2100, the DSP 2200, and / or the GPU 2300, etc. The memory interface 2600 can provide an interface for a memory external to the SoC 2000 (e.g., a dynamic random access memory (DRAM) or a flash memory).

[0200] The communication interface 2500 can provide serial communication with the outside of the SoC 2000 (e.g., external devices, components, etc.). For example, the communication interface 2500 can access Ethernet, etc. The communication interface 2500 can include an equalizer 100 as shown in Figure 2 , but is not limited thereto. Therefore, when the output resistance of the communication interface 2500 is maintained, impedance matching can be accurately performed and / or improved, so as to reduce and / or prevent signal reflection and / or distortion, etc.

[0201] In the foregoing, various example embodiments have been described in the drawings and the specification. The example embodiments have been described by using the terms described herein, but this is only for describing the inventive concept and not for limiting the meaning of the example embodiments of the inventive concept defined in the appended claims or for limiting the scope of the example embodiments of the inventive concept defined in the appended claims. Therefore, those of ordinary skill in the art can understand that various modifications and other equivalent example embodiments can be achieved from the inventive concept. Therefore, the spirit and scope of the inventive concept can be defined based on the spirit and scope of the appended claims.

[0202] Although various example embodiments of the inventive concept have been specifically shown and described with reference to the drawings, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An equalizer, comprising: A delay circuit configured to generate at least one delayed signal based on at least one input signal; An encoding circuit configured to generate a connection switch signal and a plurality of drive signals based on the at least one input signal and the at least one delayed signal; A pre-driver configured to generate a plurality of drive switch signals based on the plurality of drive signals; A first differential circuit configured to generate a first differential output signal based on the plurality of drive switch signals; A second differential circuit configured to generate a second differential output signal based on the plurality of drive switch signals; And A connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the connection switch signal.

2. The equalizer according to claim 1, wherein, The delay circuit includes: At least one latch configured to delay the at least one input signal to generate the at least one delayed signal.

3. The equalizer according to claim 1, wherein, The encoding circuit is configured to: Generate the plurality of drive signals based on the at least one input signal and the at least one delayed signal.

4. The equalizer according to claim 3, wherein, The encoding circuit is configured to: Generate a connection switch signal based on the plurality of drive signals, the plurality of drive signals being generated based on the at least one delayed signal.

5. The equalizer according to claim 4, wherein, The encoding circuit is configured to: Perform an exclusive OR operation on the plurality of drive signals to generate a connection switch signal.

6. The equalizer according to claim 1, wherein, The pre-driver is configured to generate the plurality of drive switch signals by: Performing at least one inversion operation on a first group of the plurality of drive signals based on a ground voltage; Performing at least one inversion operation on a second group of the plurality of drive signals based on an operating voltage.

7. The equalizer according to any one of claims 1 to 6, wherein The first differential circuit includes a main positive output tap and a post positive output tap, each of the main positive output tap and the post positive output tap being configured to generate a first differential output signal based on the plurality of drive switch signals; The second differential circuit includes a main negative output tap and a post negative output tap, each of the main negative output tap and the post negative output tap being configured to generate a second differential output signal based on the plurality of drive switch signals; And The connection circuit includes a connection switch element configured to adjust the connection between the post positive output tap and the post negative output tap based on the connection switch signal.

8. The equalizer according to claim 7, wherein Each of the main positive output tap and the post positive output tap includes: A first output switch element including a first terminal and a second terminal, the first terminal being configured to receive an operating voltage, the first output switch element having a first polarity, and A second output switch element including a third terminal and a fourth terminal, the third terminal being connected to the second terminal of the first output switch element, the second output switch element having a second polarity; Each of the main negative output tap and the post negative output tap includes: A third output switch element including a fifth terminal and a sixth terminal, the fifth terminal being configured to receive an operating voltage, the third output switch element having a first polarity, and A fourth output switching element, including a seventh terminal and an eighth terminal, the seventh terminal being connected to the sixth terminal of the third output switching element, the fourth output switching element having a second polarity; and A connection switching element having a second polarity, the connection switching element including a ninth terminal and a tenth terminal, The ninth terminal being connected to a node between a first output switching element included in a post positive output tap and a second output switching element included in the post positive output tap, and The tenth terminal being connected to a node between a third output switching element included in a post negative output tap and a fourth output switching element included in the post negative output tap.

9. The equalizer according to claim 7, wherein, The connection switching element has the same coefficient as each of the coefficients of each of the multiple switching elements included in each of the post positive output tap and the post negative output tap.

10. The equalizer according to claim 7, wherein, The connection switching element is further configured to: In response to the post positive output tap and the post negative output tap being in an open state, connect the post positive output tap to the post negative output tap.

11. An equalizer, comprising: A delay circuit configured to generate one or more delayed signals based on at least one input signal; An encoding circuit configured to generate a plurality of drive signals and one or more connection switch signals based on the at least one input signal and the one or more delayed signals; A pre-driver configured to generate a plurality of drive switch signals based on the plurality of drive signals; A first differential circuit configured to generate a first differential output signal based on the plurality of drive switch signals; A second differential circuit configured to generate a second differential output signal based on the plurality of drive switch signals; And A connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the one or more connection switch signals.

12. The equalizer according to claim 11, wherein, The delay circuit includes: One or more latches configured to generate the one or more delayed signals by delaying the at least one input signal.

13. The equalizer according to claim 11, wherein, The encoding circuit is configured to: Generate the plurality of drive signals based on the at least one input signal and the one or more delayed signals.

14. The equalizer according to claim 13, wherein, The encoding circuit is configured to: Generate each of the one or more connection switch signals based on the same delayed signal among the plurality of drive signals and the one or more delayed signals.

15. The equalizer according to claim 11, wherein, The pre-driver is configured to generate the plurality of drive switch signals by: Performing at least one inversion operation on a first group of the plurality of drive signals based on a ground voltage; Performing at least one inversion operation on a second group of the plurality of drive signals based on an operating voltage.

16. The equalizer according to any one of claims 11 to 15, wherein The first differential circuit includes: a plurality of positive output taps configured to generate a first differential output signal based on the plurality of drive switch signals; The second differential circuit includes: a plurality of negative output taps configured to generate a second differential output signal based on the plurality of drive switch signals; and The connection circuit includes: one or more connection switching elements configured to adjust the connection between the plurality of positive output taps and the plurality of negative output taps based on the one or more connection switch signals.

17. The equalizer according to claim 16, wherein each of the plurality of positive output taps includes: a first output switching element including a first terminal and a second terminal, the first terminal being configured to receive an operating voltage, the first output switching element having a first polarity, and a second output switching element including a third terminal and a fourth terminal, the third terminal being connected to the second terminal of the first output switching element, the second output switching element having a second polarity; each of the plurality of negative output taps includes: a third output switching element including a fifth terminal and a sixth terminal, the fifth terminal being configured to receive an operating voltage, the third output switching element having a first polarity, and a fourth output switching element including a seventh terminal and an eighth terminal, the seventh terminal being connected to the sixth terminal of the third output switching element, the fourth output switching element having a second polarity; and each of the one or more connection switching elements has a second polarity, and each of the one or more connection switching elements includes a ninth terminal and a tenth terminal, the ninth terminal being connected to a node between the first output switching element and the second output switching element, and the tenth terminal being connected to a node between the third output switching element and the fourth output switching element.

18. The equalizer according to claim 16, wherein, Each of the one or more connection switching elements has a coefficient that is the same as the coefficient of each of the plurality of switching elements included in each of the plurality of positive output taps and the plurality of negative output taps.

19. The equalizer according to claim 16, wherein, Each of the one or more connection switching elements is configured to: connect one of the plurality of positive output taps and the corresponding negative output tap to each other in response to one of the plurality of positive output taps and the corresponding negative output tap being in an off state.

20. A transmitter for transmitting an input signal through a channel, the transmitter including: a serializer configured to convert the input signal into a serial input signal; and an equalizer configured to generate a first differential output signal and a second differential output signal based on the serial input signal, the equalizer including: a delay circuit configured to generate one or more delay signals based on at least one input signal, an encoding circuit configured to generate a plurality of drive signals and one or more connection switching signals based on the at least one input signal and the one or more delay signals, a pre-driver configured to generate a plurality of drive switching signals based on the plurality of drive signals, a first differential circuit configured to generate a first differential output signal based on the plurality of drive switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of drive switching signals, and a connection circuit configured to adjust the connection between the first differential circuit and the second differential circuit based on the one or more connection switching signals.

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