Interface request processing method, master device, slave device, interface and chip

Abstract

The invention relates to an interface request processing method, master equipment, slave equipment, an interface and a chip. Comprising the following steps: a master device queries a first count value of a first counter and a second count value of a second counter based on an access request; if the condition of sending the access request is satisfied according to the first count value and the second count value, sending an effective access request carrying command data to the slave device; in response to an indication signal sent by the slave device, subtracting one from the count value of the first counter and the count value of the second counter; the indication signal indicates that the slave device has received a valid access request; in response to a counterfeit response signal returned by the slave device, adding one to the count value of the first counter; the counterfeited response signal indicates that the slave device has stored the command data in the cache unit of the slave device. By adopting the method, the back pressure mechanism of the interface can be realized, the delay of processing the request by the main equipment is reduced, the interface throughput is improved, and the processing performance of a chip system is further improved.

Description

Technical Field

[0001] This application relates to the technical field of data transmission, and in particular, to a method for processing requests of an interface, a master device, a slave device, an interface, and a chip. Background Art

[0002] With the growth of intelligent requirements and the increasing complexity of computing tasks, the performance requirements for SOC (System on Chip) design are getting higher and higher. To avoid data loss or errors, it is necessary to design a backpressure mechanism for the interface to control the data transmission flow.

[0003] In the traditional interface backpressure mechanism, the master maintains an outstanding (uncompleted transaction) counter, which is used to reflect the master's ability to send commands. When the count value of the counter is 0, the master cannot initiate a request to the slave. After the request handshake between the master and the slave is successful, the count value of the counter is decremented by one. The master needs to wait for the slave to send the command to the destination and return a response signal before incrementing the count value of the counter to release the master's processing ability.

[0004] In this way, the time required from the master and the slave to perform a request handshake to the slave sending the command to the destination and returning a response signal is relatively long, resulting in a large delay in the master's request processing. Further, due to factors such as the access delay of the PCIe (Peripheral Component Interconnect Express) bus and multiple intermediate links involved in the data transmission path, if the destination accesses a PCIe port device, this delay will be even greater. Introducing this delay into the data path, the master and the slave wait for a long time, which will directly affect the interface efficiency and further affect the performance of the chip system. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method for processing requests of an interface, a master device, a slave device, an interface, and a chip, which can implement the backpressure mechanism of the interface, reduce the delay of the master device in processing requests, improve the interface throughput, and further improve the processing performance of the chip system.

[0006] In a first aspect, this application provides a method for processing requests of an interface. The interface includes a master device and a slave device. The method is applied to the master device and includes:

[0007] When there is an access request in the master device, query the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface;

[0008] When it is determined that the condition for sending an access request is met according to the first count value and the second count value, send a valid access request to the slave device; the valid access request carries the command data corresponding to the access request;

[0009] In response to the indication signal sent by the slave device, decrement the count values of the first counter and the second counter by one respectively; wherein, the indication signal is used to indicate that the slave device has received the valid access request;

[0010] In response to the forged response signal returned by the slave device, increment the count value of the first counter by one; wherein, the forged response signal is used to indicate that the slave device has stored the command data in the cache unit of the slave device.

[0011] In one embodiment, the method further includes:

[0012] In response to the real response signal returned by the slave device, increment the count value of the second counter by one; wherein, the real response signal is used to indicate that the destination of the access request has received the command data.

[0013] In one embodiment, the method further includes:

[0014] When it is determined that the condition for sending an access request is not met according to the first count value and the second count value, stop sending the valid access request to the slave device.

[0015] In one embodiment, the method further includes:

[0016] Receive performance configuration information, and set the initial count values of the first counter and the second counter according to the performance configuration information; wherein, the initial count values of the first counter and the second counter are the same.

[0017] In a second aspect, the present application further provides a method for processing requests of an interface. The interface includes a master device and a slave device. The method is applied to the slave device and includes:

[0018] In response to the valid access request sent by the master device, when it is determined that there is free storage space in the cache unit of the slave device, receive the valid access request and send an indication signal to the master device. The indication signal is used to indicate that the slave device has received the valid access request;

[0019] Store the command data carried in the valid access request in the free storage space of the cache unit;

[0020] Send a forged response signal to the master device, where the forged response signal is used to indicate that the slave device has stored the command data in the buffer unit.

[0021] In one embodiment, the method further includes:

[0022] Send the command data stored in the buffer unit to the destination;

[0023] In response to the real response signal returned by the destination, send the real response signal to the master device; wherein, the real response signal is used to indicate that the destination has received the command data.

[0024] In one embodiment, the method further includes:

[0025] In response to the real response signal returned by the destination, delete the corresponding command data from the buffer unit.

[0026] In a third aspect, the present application further provides a method for processing requests of an interface, the interface includes a master device and a slave device, and the method includes:

[0027] When the master device has an access request to be transmitted, query the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface;

[0028] When the master device determines that the conditions for sending the access request are met according to the first count value and the second count value, send a valid access request to the slave device; the valid access request carries the command data corresponding to the access request;

[0029] In response to the valid access request sent by the master device, when the slave device determines that there is free storage space in its buffer unit, receive the valid access request and send an indication signal to the master device; the indication signal is used to indicate that the slave device has received the valid access request;

[0030] In response to the indication signal sent by the slave device, the master device decrements the count values of the first counter and the second counter respectively;

[0031] After the slave device stores the command data in the free storage space of the buffer unit, send a forged response signal to the master device; wherein, the forged response signal is used to indicate that the slave device has stored the command data in its buffer unit;

[0032] In response to the forged response signal returned by the slave device, the master device increments the count value of the first counter.

[0033] Fourthly, the present application also provides a master device, including a first processor and a first memory storing program instructions, where the first processor is configured to execute the steps of the method described in the first aspect above when running the program instructions.

[0034] Fifthly, the present application also provides a slave device, including a second processor and a second memory storing program instructions, where the second processor is configured to execute the steps of the method described in the second aspect above when running the program instructions.

[0035] Sixthly, the present application also provides an interface, where the interface includes a master device and a slave device. The master device is used to execute the steps of the method described in the first aspect above; the slave device is used to execute the steps of the method described in the second aspect above.

[0036] Seventhly, the present application also provides a chip, where the chip includes the interface described in the sixth aspect above.

[0037] For the above request processing method, master device, slave device, interface and chip of the interface, when there is an access request in the master device, query the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface; when it is determined that the condition for sending the access request is met according to the first count value and the second count value, send a valid access request to the slave device; the valid access request carries the command data corresponding to the access request; in response to the indication signal sent by the slave device, subtract one from the count values of the first counter and the second counter respectively; where the indication signal is used to indicate that the slave device has received the valid access request; in response to the forged response signal returned by the slave device, add one to the count value of the first counter; where the forged response signal is used to indicate that the slave device has stored the command data in the buffer unit of the slave device. By the above method, monitor the request volume processed by the interface through the first counter and the second counter to implement the backpressure mechanism of the interface; compared with the traditional backpressure mechanism where the master device needs to wait for the slave device to send the command to the destination and return the response before the outstanding of the interface is released, in this method, when the master device sends a valid access request, the slave device sends an indication signal, and then when the slave device sends a forged response signal, the outstanding of the interface is released and the next request can be sent. The time spent in the present application is shorter, reducing the delay of the master device in processing requests, improving the throughput of the interface, and further improving the processing performance of the chip system; by setting a buffer unit in the slave device, after the master device transmits the command data to the slave device for caching, the request processing capacity can be released, improving the efficiency of the master device in processing requests, and further improving the data transmission efficiency of the interface. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required for the description of the embodiments of the present application or related technologies. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0039] Figure 1 It is an interaction schematic diagram of the traditional backpressure mechanism in one embodiment;

[0040] Figure 2 It is a flowchart of the request processing method of the interface in one embodiment;

[0041] Figure 3 It is a flowchart of the request processing method of the interface in another embodiment;

[0042] Figure 4 It is a flowchart of the request processing method of the interface in yet another embodiment;

[0043] Figure 5 It is a structural schematic diagram of the interface in one embodiment;

[0044] Figure 6 It is an interaction schematic diagram between the interface and the host in one embodiment;

[0045] Figure 7 It is a timing schematic diagram of the interface in one embodiment;

[0046] Figure 8 It is a timing schematic diagram of the traditional backpressure mechanism in one embodiment;

[0047] Figure 9 It is a timing schematic diagram of the interface in another embodiment. Detailed implementation manners

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] The terms "first", "second", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of the present application, the first counter may be referred to as the second counter, and similarly, the second counter may be referred to as the first counter. Both the first counter and the second counter are counters, but they are not the same counter.

[0050] It is understandable that, with reference to Figure 1 and Table 1, Figure 1 FIG. is an interaction schematic diagram of the traditional backpressure mechanism in an embodiment, and Table 1 shows Figure 1 each signal and its meaning in Figure 1 The backpressure mechanism and request processing flow shown involve three entities, namely the master, the slave, and the host.

[0051] Table 1:

[0052]

[0053] The traditional interface backpressure mechanism includes the following steps:

[0054] The access request req_i is sent to the master, and the master queries whether the count value of the current ost_cnt is 0. When the count value of ost_cnt is not 0, the master initiates an access request req_vld to the slave. When the slave determines that it can receive the current request, it sets req_rdy. When both the master's req_vld and the slave's req_rdy are high, it is called a successful req handshake. After the req handshake is successful, the access request will be successfully sent to the slave, and the master will decrement the count value of ost_cnt by one. The ost_cnt maintained by the master is used to reflect the master's ability to send commands. When the count value of ost_cnt is 0, the master will be unable to initiate a request to the slave.

[0055] The slave sends the command to the remote host, and the remote host returns a response rsp after receiving the command. After the slave receives the response rsp, it returns the request response signal rsp_vld. The master sets rsp_rdy. When both the slave's rsp_vld and the master's rsp_rdy are high, it is called a successful rsp handshake. After the rsp handshake is successful, the master will increment the count value of ost_cnt by one.

[0056] It should be noted that in the traditional interface backpressure mechanism, when the master sends a command to access the host to the slave side, due to the long access path, the cycle from the application to the release of an outstanding is relatively long. The access path is as follows: 1. The master applies for an outstanding. Specifically, it queries whether the count value of the current ost_cnt is 0. When the count value of ost_cnt is not 0, it sends a request to the slave side and performs a handshake; if ost_cnt is 0, it waits for the count value of ost_cnt to be non-zero and then sends a request to the slave side. After the handshake is successful, the count value of ost_cnt is decremented by one. 2. After the slave side and the master perform a handshake, the slave side sends a request to the host side. 3. After the host side performs a handshake, it processes the command; after the command processing is completed, it returns a response request to the slave. 4. After the slave receives the response from the host, it sends a response to the master side and performs a handshake. 5. After the master side and the slave side complete the response handshake, the count value of ost_cnt is incremented by one. At this time, the release of the outstanding for this command is successful.

[0057] It can be seen that the time required from the master and the slave performing a request handshake to the slave sending the command to the destination and returning a response signal is relatively long, resulting in a large delay in the master's request processing; furthermore, due to factors such as the access delay of the PCIe (Peripheral Component Interconnect Express) bus and the data transmission path involving multiple intermediate links, if the destination accesses a PCIe port device, this delay will be even greater. Introducing this delay into the data path, the long waiting time of the master and the slave will directly affect the interface efficiency and further affect the performance of the chip system.

[0058] Based on this, the embodiments of the present application provide a method for processing requests of an interface, a master device, a slave device, an interface, and a chip. When there is an access request in the master device, the first count value of the first counter and the second count value of the second counter are queried; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface; when it is determined that the condition for sending the access request is met according to the first count value and the second count value, a valid access request is sent to the slave device; the valid access request carries command data corresponding to the access request; in response to the indication signal sent by the slave device, the count values of the first counter and the second counter are each decremented by one; wherein, the indication signal is used to indicate that the slave device has received the valid access request; in response to the forged response signal returned by the slave device, the count value of the first counter is incremented by one; wherein, the forged response signal is used to indicate that the slave device has stored the command data in the buffer unit of the slave device. By the above method, the first counter and the second counter are used to monitor the amount of requests processed by the interface, and the backpressure mechanism of the interface is implemented; compared with the traditional backpressure mechanism in which the master device needs to wait for the slave device to send the command to the destination and return the response before the outstanding of the interface is released, in this method, when the master device sends a valid access request, the slave device sends an indication signal, and until the slave device sends a forged response signal, the outstanding of the interface is released, and the next request can be sent. The time spent in the present application is shorter, the delay of the master device in processing requests is reduced, the throughput of the interface is improved, and thus the processing performance of the chip system is improved; by setting a buffer unit in the slave device, after the master device transmits the command data to the slave device for caching, the request processing ability can be released, the efficiency of the master device in processing requests is improved, and thus the data transmission efficiency of the interface is improved.

[0059] It should be noted that, in combination with Figure 1 , assume that the moment when the master end sends a request to the slave end and the handshake is successful is T1, and the moment when the slave end returns a response to the master end and the handshake is T2. The smaller the value of T2 - T1, the smaller the cycle of the master end for applying and releasing the outstanding, the lower the delay of the master device in processing requests, and the higher the processing performance of the chip system. In the embodiments of the present application, after the slave device stores the command data in the buffer unit, the slave device does not need to wait for the response of the destination device receiving the command data. The slave device returns a forged response signal to the device. After the master device receives the forged response signal, the outstanding is released, shortening the cycle of the outstanding from application to release.

[0060] In an exemplary embodiment, such as Figure 2As shown, a method for processing requests of an interface is provided. The interface includes a master device and a slave device. The method is applied to the master device and includes:

[0061] Step 202, when there is an access request in the master device, query the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface.

[0062] Among them, the access request carries command data. It can be understood that the access request is used to access the destination end, and requests the destination end to process the command data. The processing methods include, for example, reading data or writing data, etc. Exemplarily, other hardware or functional modules connected to the interface send an access request, and the master device receives the access request and processes the request.

[0063] Among them, the master device is provided with a first counter and a second counter to monitor the amount of requests processed by the interface through the first counter and the second counter. The first counter is used to count the outstanding (uncompleted transactions) of the interface, and the first count value of the first counter is used to reflect the ability of the master device to send commands. The first count value can be understood as the number of remaining transactions that the master device can process; the second counter is used to count the credit (credit token) of the interface, and the second count value of the second counter is used to reflect the ability of the interface to process commands. The second count value can be understood as the number of remaining transactions that the interface can process. As the master device and the slave device interact continuously, the first count value and the second count value will change continuously. For the access request to be transmitted, the master device queries the current first count value and second count value.

[0064] Step 204, when it is determined that the conditions for sending the access request are met according to the first count value and the second count value, send a valid access request to the slave device; the valid access request carries the command data corresponding to the access request.

[0065] Among them, if the first count value and the second count value meet the first numerical condition, it indicates that the master device has the ability to send command data, and it is determined that the condition for sending an access request is met. The first numerical condition can be that the first count value is greater than a preset threshold and the second count value is greater than the preset threshold. The preset threshold can be the lower boundary value of the count value range. It can be understood that both the first counter and the second counter are set with an upper boundary value and a lower boundary value. The upper boundary value is used to represent the maximum number of transactions that the interface can handle, and the lower boundary value can be set to 0. It can be understood that if the maximum number of transactions that the interface can handle is 10, the count value range of the counter (the first counter or the second counter) can be set to [0, 10] (i.e., the lower boundary is 0), or it can be set to [m, m + 10] (i.e., the lower boundary is m), where m is any integer, and this embodiment does not limit this. The backpressure mechanism of the interface can be understood as that when the destination end connected to the interface cannot receive data or the interface has too many requests in the backlog and cannot send them out, it is necessary to pause the running state of the interface. Optionally, if both the first count value and the second count value are greater than the lower boundary value, it indicates that the master device has the ability to send commands and the interface has the ability to process commands. At this time, the master device sends a valid access request to the slave device.

[0066] In an alternative implementation, the master device parses the command data from the access request according to the parsing strategy of the access request, and packages the command data according to the sending logic of the valid access request to generate a valid access request and send it to the slave device to ensure normal communication between the master device, the request sender, and the slave device.

[0067] Step 206, in response to the indication signal sent by the slave device, subtract one from the count value of the first counter and the count value of the second counter respectively; where the indication signal is used to indicate that the slave device has received the valid access request.

[0068] Among them, after the master device issues a valid access request, if the slave device determines that it can receive the request, it returns an indication signal. Optionally, when the master device issues a valid access request, it raises the valid signal to indicate that the data sent by the master device is valid; if the slave device determines that it can receive the request, it returns an indication signal and raises the ready signal to indicate that the slave device is ready; when the data transmitted by the master device is valid and the slave device is ready, the command data will be taken away by the slave device, realizing the request handshake between the master device and the slave device. At this time, the command data is successfully transmitted to the slave device. After the handshake is successful, the master device decrements the count values of the first counter and the second counter respectively. Since the command data has not been sent to the destination, for the master device and the interface, the transaction of sending the command data this time is an unfinished transaction, and the subsequent need to continue to track this unfinished transaction; by decrementing the count values of the first counter and the second counter, the number of remaining processable transactions of the master device and the number of remaining processable transactions of the interface are updated, which helps to prevent deadlocks.

[0069] Step 208, in response to the forged response signal returned by the slave device, increment the count value of the first counter; wherein, the forged response signal is used to indicate that the slave device has stored the command data in the buffer unit of the slave device.

[0070] Among them, the slave device is provided with a buffer unit for storing the command data sent by the master device. After the slave device stores the command data in the buffer unit, it generates a forged response signal and returns it to the master device. The master device regards the forged response signal as the request response signal of the destination. In response to the forged response signal, the master device determines the transaction of sending the command data this time as a completed transaction, and increments the count value of the first counter to update the number of remaining processable transactions of the master device. At this time, the master device determines that the outstanding transaction is completed and releases resources. If there are still requests to be sent in the master device at this time, then the master device continues to determine whether it has the condition to send requests according to the first count value and the second count value. If it has the sending condition, it can continue to send requests.

[0071] Optionally, after the request handshake is successful between the master device and the slave device, the buffer unit receives a forged request carrying the command data, performs a handshake based on the forged request, caches the command data, and after the caching is successful, sends a forged response signal to the master device.

[0072] In the request processing method of the above-mentioned interface, the amount of requests processed by the interface is monitored by the first counter and the second counter to realize the back pressure mechanism of the interface; compared with the traditional back pressure mechanism in which the master device needs to wait for the slave device to send the command to the destination and return a response before releasing outstanding, in this method, the time taken from the master device sending a valid access request, the slave device sending an indication signal, to the master device receiving the forged response signal sent by the slave device is shorter, thereby reducing the delay of the master device in processing the request, improving the interface throughput, and thus improving the processing performance of the chip system; by setting a cache unit on the slave device, the master device can release the request processing capability after transmitting the command data to the slave device for caching, thereby improving the efficiency of the master device in processing requests, and thus improving the data transmission efficiency of the interface.

[0073] In an exemplary embodiment, the method further includes: in response to a true response signal returned from the device, adding one to the count value of the second counter; wherein the true response signal is used to indicate that the destination end of the access request has received the command data.

[0074] The slave device sends each command data stored in the cache unit to the corresponding destination. Optionally, the slave device initiates a request to the destination (host). When the destination successfully shakes hands with the slave device, the command data sent by the master device is actually written to the destination. At this time, the destination will initiate a response (i.e., a real response signal) to the slave device, and the slave device will transparently transmit the response to the master device. After receiving the real response signal, the master device confirms that the access request has been processed and adds one to the count value of the second counter to update the number of remaining processable transactions on the interface.

[0075] In an exemplary embodiment, the method further includes: if it is determined according to the first count value and the second count value that the condition for sending the access request is not satisfied, stopping sending the valid access request to the slave device.

[0076] Among them, the backpressure mechanism of the interface can be understood as that when the destination end connected to the interface cannot receive data or the interface has too many backlogged requests and cannot send them out, the running state of the interface needs to be paused. If the first count value and the second count value meet the second numerical condition, it indicates that the master device does not have the ability to send command data, and it is determined that the condition for sending an access request is not met. The second numerical condition can be that the first count value is not greater than a preset threshold or the second count value is not greater than a preset threshold, and the preset threshold can be the lower boundary value of the count value range. It can be understood that if the count value of the first counter is equal to the lower boundary value, it indicates that the master device does not have the ability to send commands, and at this time, the master device cannot send a valid access request to the slave device. If the count value of the second counter is equal to the lower boundary value, it indicates that the interface does not have the ability to process commands, and at this time, the master device cannot send a valid access request to the slave device.

[0077] Through the above method, the backpressure mechanism of the interface is implemented, which can avoid data loss and data backlog during the request processing, ensure the smooth transmission of data, and improve the stability of data transmission.

[0078] In an exemplary embodiment, the method further includes: receiving performance configuration information, and setting the initial count value of the first counter and the initial count value of the second counter according to the performance configuration information; wherein, the initial count values of the first counter and the second counter are the same.

[0079] Among them, the performance configuration information is used to configure the interface so that the interface meets the expected performance requirements. Optionally, the performance configuration information includes a performance metric of the number of operations that the interface can perform per second, for example, 1 Gops (Giga Operations Per Second). In an alternative implementation, the master device sets the initial count value of the first counter and the initial count value of the second counter based on the duration required for the command req to be sent to the rsp return of the command (that is, the duration required for the interface to process one command), and the number of operations that the interface can perform per second. Exemplarily, assume that the duration required for the command req to be sent to the rsp return of the command is 100 ns, and the performance configuration information is used to indicate that the interface performance needs to reach 1 Gops; the single command sending performance is: 1 / 100 ns = 10 M, and 1 Gops = 1000 Mops; the initial count values of the first counter and the second counter are set to: 1000 M / 10 M = 100.

[0080] In an exemplary embodiment, as Figure 3 shown, a method for processing requests of an interface is provided. The interface includes a master device and a slave device, and the method is applied to the slave device and includes:

[0081] Step 302, in response to a valid access request sent by the master device, when it is determined that the cache unit of the slave device has free storage space, receive the valid access request and send an indication signal to the master device, where the indication signal is used to indicate that the slave device has received the valid access request.

[0082] Among them, when there is an access request in the master device, query the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface; when it is determined that the conditions for sending the access request are met according to the first count value and the second count value, send a valid access request to the slave device; the valid access request carries the command data corresponding to the access request.

[0083] In response to the indication signal sent by the slave device, the master device decrements the count values of the first counter and the second counter by one respectively.

[0084] It can be understood that if the cache unit of the slave device has free storage space, that is, the cache unit is not full, the slave device determines that it can receive requests, generates an indication signal, and sends it to the master device. Optionally, the master device sends a valid access request to the slave device (i.e., req_vld = 1). If the cache unit is not full, the slave device returns an indication signal (i.e., req_rdy = 1), and the handshake is successful at this time; if the cache unit is full, the slave device sets req_rdy = 0, and the handshake fails at this time. The master device keeps req_vld = 1 until it receives req_rdy = 1. In this way, when the slave device receives command data when the cache is not full, data loss can be avoided, and the reliability of data transmission can be improved.

[0085] Step 304, store the command data carried in the valid access request into the free storage space of the cache unit.

[0086] Step 306, send a forged response signal to the master device, where the forged response signal is used to indicate that the slave device has stored the command data in the cache unit.

[0087] Optionally, after the request handshake between the slave device and the master device is successful, the cache unit receives a forged request carrying command data, performs a handshake based on the forged request, caches the command data, and after the caching is successful, the slave device sends a forged response signal to the master device. In response to the forged response signal returned by the slave device, the master device increments the count value of the first counter by one.

[0088] It can be understood that the descriptions of steps 302 - 306 can refer to the explanations of the aforementioned steps 202 - 208, and will not be elaborated here.

[0089] In the request processing method of the above interface, the master device monitors the amount of requests processed by the interface through the first counter and the second counter to realize the back pressure mechanism of the interface; compared with the traditional back pressure mechanism in which the master device needs to wait for the slave device to send the command to the destination and return the response before the outstanding of the interface is released, in this method, the master device sends a valid access request, the slave device sends an indication signal, and the slave device sends a forged response signal, then the outstanding of the interface is released and the next request can be sent. The time spent in this application is relatively short, which reduces the delay of the master device in processing requests, improves the interface throughput, and thus improves the processing performance of the chip system; by setting a cache unit in the slave device, the master device can release the request processing capability after transmitting the command data to the slave device for caching, which improves the efficiency of the master device in processing requests, and thus improves the data transmission efficiency of the interface.

[0090] In an exemplary embodiment, the method further includes: sending the command data stored in the cache unit to the destination end; in response to a true response signal returned by the destination end, sending the true response signal to the main device; wherein the true response signal is used to indicate that the destination end has received the command data.

[0091] Among them, the slave device initiates a request to the destination (host). When the destination and the slave device successfully shake hands, the command data sent by the master device is actually written to the destination. At this time, the destination will initiate a response (i.e., a real response signal) to the slave device, and the slave device will transparently transmit the response to the master device. The master device responds to the real response signal returned by the slave device and adds one to the count value of the second counter. It can be understood that after receiving the real response signal, the master device confirms that the access request has been processed and adds one to the count value of the second counter to update the number of remaining processable transactions on the interface.

[0092] In an exemplary embodiment, the method further includes: in response to a true response signal returned by the destination end, deleting corresponding command data from the cache unit.

[0093] Among them, if a true response signal returned by the destination is received, the slave device determines that the access request has been processed and deletes the command data corresponding to the access request in the cache unit, thereby releasing cache resources and providing storage space for other command data, thereby improving the data transmission efficiency of the interface.

[0094] In an exemplary embodiment, Figure 4 As shown, a request processing method for an interface is provided, the interface includes a master device and a slave device, and the method includes:

[0095] Step 402: When the master device has an access request to be transmitted, it queries the first count value of the first counter and the second count value of the second counter. The first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface.

[0096] Step 404: When the master device determines that the conditions for sending the access request are met based on the first count value and the second count value, it sends a valid access request to the slave device. The valid access request carries the command data corresponding to the access request.

[0097] Step 406: In response to the valid access request sent by the master device, when the slave device determines that there is free storage space in its cache unit, it receives the valid access request and sends an indication signal to the master device. The indication signal is used to indicate that the slave device has received the valid access request.

[0098] Step 408: In response to the indication signal sent by the slave device, the master device decrements the count values of the first counter and the second counter by one respectively.

[0099] Step 410: After storing the command data in the free storage space of the cache unit, the slave device sends a forged response signal to the master device. The forged response signal is used to indicate that the slave device has stored the command data in its cache unit.

[0100] Step 412: In response to the forged response signal returned by the slave device, the master device increments the count value of the first counter by one.

[0101] For the descriptions of steps 402 - 412, reference can be made to the explanations of the foregoing steps 202 - 208 and steps 302 - 306, which will not be elaborated here.

[0102] In an exemplary embodiment, the method further includes: the slave device sends the command data stored in the cache unit to the destination; in response to the real response signal returned by the destination, it sends the real response signal to the master device; the real response signal is used to indicate that the destination has received the command data;

[0103] In response to the real response signal returned by the slave device, the master device increments the count value of the second counter by one.

[0104] In an exemplary embodiment, the method further includes: when the master device determines that the conditions for sending the access request are not met based on the first count value and the second count value, it stops sending valid access requests to the slave device.

[0105] In an exemplary embodiment, the method further includes: the master device receives performance configuration information, and sets the initial count value of the first counter and the initial count value of the second counter according to the performance configuration information; wherein, the initial count value of the first counter is the same as the initial count value of the second counter.

[0106] In an exemplary embodiment, the method further includes: the slave device deletes the corresponding command data from the cache unit in response to the true response signal returned by the destination.

[0107] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0108] Based on the same inventive concept, an embodiment of the present application further provides an interface for implementing the request processing method of the interface involved above. The implementation solution for solving the problem provided by this interface is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more interface embodiments provided below can refer to the limitations on the request processing method of the interface in the above text, and will not be repeated here.

[0109] In an exemplary embodiment, as Figure 5 shown, an interface is provided, including: a master device 501 and a slave device 502. The master device 501 includes a first circuit logic module 5011, an unfinished transaction control module 5012, and a credit token control module 5013; the unfinished transaction control module 5012 maintains a first counter, and the credit token control module 5013 maintains a second counter; wherein:

[0110] The first circuit logic module 5011 is configured to, when there is an access request in the master device 501, initiate registration requests to the unfinished transaction control module 5012 and the credit token control module 5013 respectively.

[0111] The unfinished transaction control module 5012 is configured to query the first count value of the first counter according to the registration request, and return the first count value to the first circuit logic module 5011.

[0112] The credit token control module 5013 is configured to query the second count value of the second counter according to the registration request and return the second count value to the first circuit logic module 5011.

[0113] The first circuit logic module 5011 is further configured to, when it is determined that the conditions for sending an access request are met based on the first count value and the second count value, send a valid access request to the slave device 502; the valid access request carries the command data corresponding to the access request; in response to the indication signal sent by the slave device 502, initiate a first count adjustment request to the unfinished transaction control module 5012 and the credit token control module 5013 respectively; wherein, the indication signal is used to indicate that the slave device 502 has received the valid access request.

[0114] The unfinished transaction control module 5012 is further configured to decrement the count value of the first counter according to the first count adjustment request.

[0115] The credit token control module 5013 is further configured to decrement the count value of the second counter according to the first count adjustment request.

[0116] The first circuit logic module 5011 is further configured to initiate a second count adjustment request to the unfinished transaction control module 5012 in response to the forged response signal returned by the slave device 502; wherein, the forged response signal is used to indicate that the slave device 502 has stored the command data in the cache unit of the slave device.

[0117] The unfinished transaction control module 5012 is further configured to increment the count value of the first counter according to the second count adjustment request.

[0118] In an exemplary embodiment, the first circuit logic module 5011 is further configured to initiate a third count adjustment request to the credit token control module 5013 in response to the real response signal returned by the slave device 502; wherein, the real response signal is used to indicate that the destination of the access request has received the command data.

[0119] The credit token control module 5013 is further configured to increment the count value of the second counter according to the third count adjustment request.

[0120] In an exemplary embodiment, the slave device 502 includes a cache unit 5021 and a second circuit logic module 5022; wherein:

[0121] The second circuit logic module 5022 is configured to, in response to the valid access request sent by the master device 501, receive the valid access request and send an indication signal to the master device 501 when it is determined that the cache unit 5021 of the slave device 502 has free storage space.

[0122] The second circuit logic module 5022 is further used to store the command data carried in the valid access request into the free storage space of the cache unit 5021 and send a forged response signal to the master device 501 .

[0123] In an exemplary embodiment, the second circuit logic module 5022 is also used to send the command data stored in the cache unit 5021 to the destination end; in response to the real response signal returned by the destination end, send the real response signal to the main device 501.

[0124] In an exemplary embodiment, the first circuit logic module 5011 is further configured to stop sending a valid access request to the slave device 502 when the condition for sending the access request is determined according to the first count value and the second count value.

[0125] In an exemplary embodiment, the unfinished transaction control module 5012 is also used to receive performance configuration information and set the initial count value of the first counter according to the performance configuration information; the credit token control module 5013 is also used to receive performance configuration information and set the initial count value of the second counter according to the performance configuration information; wherein the initial count value of the first counter is consistent with the initial count value of the second counter.

[0126] In an exemplary embodiment, the second circuit logic module 5022 is further configured to delete corresponding command data from the cache unit 5021 in response to a true response signal returned by the destination end.

[0127] In an exemplary embodiment, referring to Figure 6 and Table 2, Figure 6 Table 2 shows the interaction between the interface and the host in an embodiment. Figure 6 The signals and their meanings. Figure 6 The interactive process shown involves three entities, namely the master, slave, and host, and includes the following steps:

[0128] 1) The master queries the current access request. If there is an access request, it initiates a registration request (login) to the outstanding cnt control module and the credit cnt control module through the logic module.

[0129] 2) The outstanding cnt control module and the credit cnt control module query whether there is any outstanding or credit that has not been exhausted. If neither of them has been exhausted, the master side sends a request req_vld to the slave side. If either the outstanding or the credit is exhausted, the master cannot send the request req_vld to the slave.

[0130] It can be understood that the outstanding cnt control module maintains the ost_cnt timer, and the credit cnt control module maintains the credit_cnt timer. If an external cnt+1 control signal is received, the counter is incremented by 1; if an external cnt-1 control signal is received, the counter is decremented by 1. When ost_cnt = 0, it is called that the outstanding is exhausted; if credit_cnt = 0, it is called that the credit is exhausted. If ost_cnt > 0, it is called that the outstanding is not exhausted; if credit_cnt > 0, it is called that the credit is not exhausted. Refer to Figure 6 When both the outstanding and the credit are not exhausted, the logic module registers the successful request signal and the credit_cnt >0 signal in the credit cnt control module to perform an AND operation through AND gate 3 to initiate a req_vld.

[0131] 3) When the buffer unit inside the slave is not full, that is, when it is determined that the slave can receive the current request, the slave sets req_rdy. When req_vld and req_rdy are both high, the req handshake is successful, and the buffer unit buffer receives the fake_req, performs the handshake, and stores the command data sent by the master into the slave internal buffer.

[0132] Among them, refer to Figure 7 , Figure 7 is the timing diagram of the interface in an embodiment, and clk represents the clock. After the master sends req_vld to the slave, it keeps req_vld = 1 (that is, Figure 7 the high level of req_vld shown); when the slave side sets req_rdy = 1 (that is, Figure 7When the req_rdy shown is at a high level), it is called a successful handshake, and the master side can initiate the next req_vld. In this embodiment, when the internal buffer of the slave is not full, req_rdy = 1 is set; when the internal buffer of the slave is full, req_rdy = 0 is set. Since the master actually accesses the destination host, the handshake signals of the buffers in the master and the slave are called fake_req and fake_rsp to distinguish them from the actual handshake with the host. It can be understood that when req_vld = 1 and req_rdy = 1, that is, when both req_vld and req_rdy are at a high level, the slave takes away the command data passed by the master (that is Figure 7 the req_data shown, including data0, data1, data2, and data3).

[0133] 4) After the req handshake initiated by the master side to the slave is successful, the master controls the ost_cnt timer to decrement by 1 and simultaneously controls the credit cnt counter to decrement by 1.

[0134] The outstanding cnt control module and the credit cnt control module are used to control the ability of the master to send commands to the slave. When the command is successfully sent to the slave, the ost_cnt timer and the credit cnt counter need to be updated. Refer to Figure 6 When the req handshake between the master and the slave is successful, that is, the logical AND of req_vld and req_rdy (AND gate 2) is 1. At this time, the ost_cnt maintained in the outstanding cnt control module decrements by 1, and the credit_cnt maintained in the credit cnt control module decrements by 1.

[0135] 5) After the slave side stores the command data in the buffer, it returns rsp_vld (that is, fake_rsp) to the master side. The master sets rsp_rdy. When the rsp handshake is successful, the master controls the ost_cnt timer to increment by 1.

[0136] When the rsp handshake between the master and the slave is successful, that is, the logical AND of rsp_vld and rsp_rdy (AND gate 1) is 1. At this time, the ost_cnt maintained in the outstanding cnt control module increments by 1, which is called the successful release of the outstanding at the master side.

[0137] Among them, referring to Figure 7 , after the slave sends rsp_vld to the master, it keeps rsp_vld = 1 (i.e., Figure 7 the high level of rsp_vld shown); when the master sets rsp_rdy = 1 (i.e., Figure 7 the high level of rsp_rdy shown), it is called that the rsp handshake is successful, and the slave can initiate the next req_vld. It can be understood that when rsp_vld = 1 and rsp_rdy = 1, that is, when both rsp_vld and rsp_rdy are at high level, the master takes away the response data transmitted by the slave (i.e., Figure 7 the rsp_data shown, including data0, data1, data2, and data3).

[0138] 6) When the slave sends the command data to the destination host, after the destination host receives the command data, it returns real_rsp. And it returns the credit_pop_pulse signal to the slave, and the slave returns this pulse to the maser end. This signal indicates that the command has been delivered to the host end. At this time, the master end controls the credit cnt timer to increment by 1.

[0139] When the number of commands in the buffer of the slave is non-zero, the logic module in the slave will initiate real_req to the host. After the real_req handshake between the slave and the host is successful, the command initiated by the master end is actually written to the destination end. At this time, the host will initiate real_rsp to the slave module, and the slave will transparently transmit the rsp to the credit cnt control module at the master end. This signal is called credit_pop_pluse and is used to control the credit cnt maintained by the credit cnt control module to increment by 1.

[0140] Table 2:

[0141]

[0142] In an exemplary embodiment, in order to illustrate the differences between the request processing method, master device, slave device, interface, and chip provided by the present application and the traditional backpressure mechanism, Figure 8 and Figure 9 the timing diagrams shown are provided. Figure 8 and Figure 9For example only, it is not used to limit this application. Among them, the clock clk is 1 GHz, the master sends 5 requests to the slaver continuously, and the upper boundary values of ost_cnt and credit_cnt are 5, and the lower boundary values are 0.

[0143] In the traditional backpressure mechanism, rsp_vld is initiated only after the host receives a request. From the moment when the req handshake between the master and the slave is successful (i.e., Figure 8 at moment a), to the moment when the host receives the request and initiates rsp_vld (i.e., Figure 8 at moment b), in the SOC design, this delay is about 100 cycles, that is, about 100 ns. From the perspective of the master and slave interfaces, it is equivalent to sending only one request in 100 ns.

[0144] In the embodiment of this application, after the slave stores the master's request in the cache unit, it returns rsp_vld (i.e., fake_rsp). From the moment when the req handshake between the master and the slave is successful (i.e., Figure 9 at moment a), to the moment when the slave initiates rsp_vld (i.e., Figure 9 at moment b), in the SOC design, this delay is about 10 cycles, that is, about 10 ns. From the moment when the req handshake between the master and the slave is successful (i.e., Figure 9 at moment c), to the moment when the host receives the request and returns credit_pop_pulse (i.e., Figure 9 at moment d), it takes about 100 ns. From the perspective of the master and slave interfaces, it is equivalent to sending one request in 10 ns. Thus, it can be seen that in the above example, the performance of the interface implemented by this application is about 10 times that of the interface using the traditional backpressure mechanism; when the number of requests continuously sent by the master is greater than 5, this performance gap will be even larger.

[0145] Each module in the above interface can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the chip in hardware form or be independent of it, or can be stored in the memory in the chip in software form so that the processor can call and execute the operations corresponding to the above modules.

[0146] In an exemplary embodiment, this application also provides a master device, including a first processor and a first memory storing program instructions, and the first processor is configured to execute the steps of the method applied to the master device provided in any one of the above embodiments when running the program instructions.

[0147] In an exemplary embodiment, the present application further provides a slave device, including a second processor and a second memory storing program instructions. The second processor is configured to execute the steps of the method applied to the slave device provided in any of the above embodiments when running the program instructions.

[0148] In an exemplary embodiment, the present application further provides an interface, which includes a master device and a slave device. The master device is configured to execute the steps of the method applied to the master device provided in any of the above embodiments; the slave device is configured to execute the steps of the method applied to the slave device provided in any of the above embodiments.

[0149] In an exemplary embodiment, a chip is provided, and the chip includes the interface provided in any of the embodiments of the present application.

[0150] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0151] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, the memories, databases, or other media mentioned in the various embodiments provided in the present application can all include at least one of non-volatile memories and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the various embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the various embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing units (Data Process Unit), artificial intelligence (AI) processors, etc., without limitation.

[0152] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in the present application.

[0153] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for processing requests of an interface, characterized in that, The interface includes a master device and a slave device, and the method is applied to the master device. The method includes: When there is an access request in the master device, query the first count value of the first counter and the second count value of the second counter. The first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface. When it is determined that the condition for sending the access request is met according to the first count value and the second count value, send a valid access request to the slave device. The valid access request carries the command data corresponding to the access request. In response to the indication signal sent by the slave device, decrement the count values of the first counter and the second counter by one respectively. The indication signal is used to indicate that the slave device has received the valid access request. In response to the forged response signal returned by the slave device, increment the count value of the first counter by one. The forged response signal is used to indicate that the slave device has stored the command data in the cache unit of the slave device.

2. The method according to claim 1, wherein The method further includes: In response to the real response signal returned by the slave device, increment the count value of the second counter by one. The real response signal is used to indicate that the destination of the access request has received the command data.

3. The method according to claim 1, characterized in that, The method further includes: When it is determined that the condition for sending the access request is not met according to the first count value and the second count value, stop sending the valid access request to the slave device.

4. The method according to any one of claims 1 to 3, characterized in that The method further includes: Receive performance configuration information, and set the initial count values of the first counter and the second counter according to the performance configuration information. The initial count values of the first counter and the second counter are the same.

5. A method for processing requests of an interface, characterized in that, The interface includes a master device and a slave device, and the method is applied to the slave device. The method includes: In response to the valid access request sent by the master device, when it is determined that the cache unit of the slave device has free storage space, receive the valid access request and send an indication signal to the master device. The indication signal is used to indicate that the slave device has received the valid access request. Store the command data carried in the valid access request in the free storage space of the cache unit. Send a forged response signal to the master device. The forged response signal is used to indicate that the slave device has stored the command data in the cache unit.

6. The method according to claim 5, characterized in that, The method further includes: Send the command data stored in the cache unit to the destination. In response to the real response signal returned by the destination, send the real response signal to the master device. The real response signal is used to indicate that the destination has received the command data.

7. The method according to claim 6, wherein The method further includes: In response to the real response signal returned by the destination, delete the corresponding command data from the cache unit.

8. A method for processing requests of an interface, characterized in that, The interface includes a master device and a slave device, and the method includes: When the master device has an access request to be transmitted, it queries the first count value of the first counter and the second count value of the second counter; the first counter is used to count the outstanding of the interface, and the second counter is used to count the credit of the interface; When the master device determines that the conditions for sending the access request are met based on the first count value and the second count value, it sends a valid access request to the slave device; the valid access request carries the command data corresponding to the access request; In response to the valid access request sent by the master device, when the slave device determines that there is free storage space in its cache unit, it receives the valid access request and sends an indication signal to the master device; the indication signal is used to indicate that the slave device has received the valid access request; In response to the indication signal sent by the slave device, the master device decrements the count values of the first counter and the second counter respectively; After storing the command data in the free storage space of the cache unit, the slave device sends a forged response signal to the master device; wherein, the forged response signal is used to indicate that the slave device has stored the command data in its cache unit; In response to the forged response signal returned by the slave device, the master device increments the count value of the first counter.

9. A master device, comprising a first processor and a first memory storing program instructions, characterized in that, The first processor is configured to execute the steps of the method according to any one of claims 1 to 4 when running the program instructions.

10. An accessory device, comprising a second processor and a second memory storing program instructions, characterized in that, The second processor is configured to execute the steps of the method according to any one of claims 5 to 7 when running the program instructions.

11. An interface, the interface comprising a master device and a slave device, characterized in that, The master device is used to execute the steps of the method according to any one of claims 1 to 4; The slave device is used to execute the steps of the method according to any one of claims 5 to 7.

12. A chip, characterized in that, The chip includes the interface according to claim 11.

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