Method for increasing MIPI CPHY transmission distance
Through the two-stage data processing method, the MIPI C-PHY signal is converted into a DP signal and restored to a C-PHY signal, which solves the problem of short transmission distance of MIPI C-PHY, achieves a longer transmission distance and higher test efficiency, reduces electromagnetic interference, and improves the testing reliability and flexibility of the equipment.
Patent Information
- Application Number
- CN202510408290.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-18
AI Technical Summary
MIPI C-PHY has short transmission distance, high design complexity and cost, sensitive electromagnetic interference, and low ecosystem maturity, resulting in problems such as testing limitations and low efficiency.
Using a two-stage data processing method, the first stage converts data into DP signal output through conversion module A and controller A, and the second stage restores the DP signal to C-PHY signal output through conversion module B and controller B, and uses the high bandwidth and anti-interference ability of the DP signal to increase the transmission distance.
The transmission distance is increased from 10-15cm to more than 3M, which solves the problem of short transmission distance, improves the flexibility and efficiency of testing, reduces electromagnetic interference, and enhances the stability and reliability of the signal.
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Figure CN120343108A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for improving the transmission distance, and particularly to a method for improving the transmission distance of MIPI CPHY. Background Art
[0002] With the explosive development of AI technology, head-mounted devices and wearable devices will enter a period of rapid development. Currently, the main driving protocols for mainstream head-mounted and wearable devices include: IIC, SPI, LVDS, MIPI (Mobile Industry Processor Interface), etc. Among them, MIPI (Mobile Industry Processor Interface) has the highest rate and includes multiple protocols; D-PHY is the most widely used and stable existing method, but C-PHY has a higher transmission rate and is the best choice to embrace the AI era.
[0003] MIPI (Mobile Industry Processor Interface) DSI C-PHY adopts a unique 3-Phase symbol encoding technology. Each symbol can transmit 2.28 bits of data. Compared with 1 bit / symbol of D-PHY, the three groups of signal lines of C-PHY can transmit multiple data streams simultaneously, thus achieving higher data throughput; the clock signal of C-PHY is embedded in the data and does not require a separate clock channel, which reduces the number of pins and wiring complexity, and also reduces electromagnetic interference (EMI); C-PHY supports a data rate of up to 4.5 Gbps and can meet the bandwidth requirements of high-resolution display applications; C-PHY is designed to support coexistence with D-PHY on the same pins, which provides greater flexibility for manufacturers when designing new devices and allows for convenient selection and upgrade.
[0004] Refer to the following process Figure 1 , the existing MIPI (Mobile Industry Processor Interface) C-PHY driving solution: the host computer sends image data through Ethernet, and the MIPI (Mobile Industry Processor Interface) C-PHY output controller receives, processes, converts, and outputs the data to drive the display screen.
[0005] Research finds that in industrial actual usage scenarios, MIPI (Mobile Industry Processor Interface) C-PHY has problems such as short transmission distance, high design complexity and cost, sensitivity to electromagnetic interference (EMI), and low ecosystem maturity.
[0006] The main disadvantages are as follows:
[0007] 1. Due to its extremely high transmission rate, the effective transmission distance of C-PHY generally remains within 10 - 15 cm, and it needs to rely on higher-quality wires or repeaters to extend the distance; it can meet the usage requirements at the client and application ends, but faces great testing challenges at the product testing end;
[0008] 2. Due to its complex design and high cost, C-PHY requires an even higher yield rate; however, the short-distance transmission undoubtedly increases the limitations and inefficiency of testing;
[0009] 3. C-PHY uses a unique 3-Phase symbol encoding technology instead of differential transmission similar to D-PHY, resulting in sensitivity to electromagnetic interference (EMI);
[0010] 4. C-PHY is currently mainly applied to mobile phones and will surely be widely used in future head-mounted displays and wearable devices, but the maturity of its display-related ecosystem in head-mounted displays and wearable devices is not high enough. Summary of the Invention
[0011] To solve the problems of short transmission distance, structural complexity, and high cost, the present invention provides a method for improving the transmission distance of MIPI CPHY.
[0012] The present invention provides the following technical solutions:
[0013] A method for improving the transmission distance of MIPI CPHY includes two-level data processing, namely the first-level data processing and the second-level data processing. The first-level data processing is carried out through the first-level data processing module, and the second-level data processing is carried out through the second-level data processing module;
[0014] The first-level data processing module includes a conversion module A and a controller A, and the conversion module A and the controller output a DP signal;
[0015] The second-level data processing module includes a conversion module B and a controller B, and the conversion module B and the controller B restore the DP signal to a C-PHY signal for output.
[0016] The steps of the two-level data processing are as follows:
[0017] The host computer sends data to the first-level data processing module through Ethernet. The first-level data processing module includes a conversion module A and a controller A. The conversion module A receives the data from the host computer, converts the received data through the data conversion of the conversion module A, and converts the data into a DP signal for output through the controller A;
[0018] The DP signal is sent to the second-stage data processing module. The conversion module B receives the DP signal data, converts the received DP signal data through the conversion module B, and restores the DP signal to a C-PHY signal through the controller B. The C-PHY signal output is used to drive the display screen.
[0019] Furthermore, through the encoding and decoding method, the C-PHY signal is converted back to drive the display screen.
[0020] Furthermore, the conversion module A uses the chip STM32H743 to receive data through Ethernet, stores the data in the memory EMMC. The controller A uses XC7K035 to communicate with the conversion module A through the FSMC bus, temporarily caches the data in the memory DDR, and through the internal GTX function of the controller A, uses the DP IP core to convert the data in the memory DDR into DP data and outputs it as a DP signal.
[0021] Furthermore, the DP signal output includes a four-channel linear transfer driver and a capacitor bank. The VCC1-VCC12 terminals of the four-channel linear transfer driver are connected to the capacitor bank. The four-channel linear transfer driver uses the SN65DP141 chip for receiving, processing, and outputting high-speed digital signals.
[0022] Furthermore, the conversion module B accesses a bridge chip. The DP receiving end is used as an input to receive the DP signal, performs decoding processing on it, and performs signal conversion through the bridge chip in the middle to convert it into a MIPI CPHY signal and output the MIPI CPHY signal to drive the display screen.
[0023] Furthermore, the DP receiving end includes an interface part J1, various resistors, and various connectors. The interface part J1 uses DP_Sink_Receptacle. The pins of the interface part J1 are connected to the resistor R1, resistor R7, and resistor R8. The pins of the interface part J1 are also connected to the connectors D1, D2, and D3.
[0024] Furthermore, the MIPI CPHY signal output includes the chip U3B, which has ports Port 0, Port 1, Port 2, and Port 3, and each port has multiple differential signal pairs.
[0025] Compared with the prior art, the beneficial effects of the present invention are:
[0026] Optimized for the factory-end test of the tiny display screen applied to future head-mounted displays and wearable devices.
[0027] (1) Through two - level data processing, namely the first - level data processing and the second - level data processing, the transmission distance of MIPI DSIC - PHY is improved. The transmission distance is increased from 10 - 15 cm to more than 3 m, solving the problem of short transmission distance and being beneficial to the test work at the factory production end;
[0028] (2) The first - level data processing module outputs the DP signal, and the second - level data processing module restores the DP signal to the C - PHY signal for output; The DP signal has the advantages of high bandwidth, long transmission distance and strong anti - interference ability. Based on the DP signal for the transfer method, it solves the test limitations and efficiency problems caused by short - distance transmission. Brief Description of the Drawings
[0029] Figure 1 It is the schematic diagram of the prior art of the present invention;
[0030] Figure 2 It is the schematic diagram of the present invention;
[0031] Figure 3 It is the schematic diagram of the configuration of conversion module A;
[0032] Figure 4 It is the schematic diagram of controller A - GTX;
[0033] Figure 5 It is the schematic diagram of DP signal output;
[0034] Figure 6 It is the schematic diagram of conversion module B and controller B;
[0035] Figure 7 It is the schematic diagram of the DP input connector;
[0036] Figure 8 It is the schematic diagram of DP input to the bridge chip;
[0037] Figure 9 It is the schematic diagram of MIPI CPHY output;
[0038] Figure 10 It is the C - PHY eye diagram test chart. Detailed Embodiment
[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0040] Figure 2As shown, a method for improving the transmission distance of MIPI CPHY includes two - stage data processing, namely the first - stage data processing and the second - stage data processing. The first - stage data processing is carried out by the first - stage data processing module, and the second - stage data processing is carried out by the second - stage data processing module;
[0041] The first - stage data processing module includes a conversion module A and a controller A, and the conversion module A and the controller A output the DP signal;
[0042] The second - stage data processing module includes a conversion module B and a controller B, and the conversion module B and the controller B restore the DP signal to a C - PHY signal for output.
[0043] The main function of the present invention is to improve the transmission distance of MIPI DSI C - PHY. Different from the existing C - PHY driving scheme, it performs two - stage data processing.
[0044] The steps are as follows:
[0045] The host computer sends data to the first - stage data processing module through Ethernet. The first - stage data processing module includes a conversion module A and a controller A. The conversion module A receives data from the host computer, converts the received data through the conversion module A, and converts the data into a DP signal for output through the controller A;
[0046] Compared with Figure 1 , the conversion module and the controller are designed to output a DP (DisplayPort) signal. The DP signal has the characteristics of high bandwidth, long transmission distance, strong anti - interference ability, high standardization and compatibility compared with the MIPI C - PHY signal; The relay method based on the DP signal perfectly solves the problem of short transmission distance currently faced by MIPI C - PHY;
[0047] The DP signal is sent to the second - stage data processing module. The conversion module B receives the DP signal data, converts the received DP signal data through the conversion module B, and restores the DP signal to a C - PHY signal through the controller B. The C - PHY signal output is used to drive the display screen.
[0048] The second - stage data processing module is the core of the invention. The conversion module B and the controller B are used to restore the DP signal to a C - PHY signal, and through the encoding and decoding method, convert the CPHY signal back to drive the display screen.
[0049] Figure 3 It is the schematic diagram of the conversion module A; Figure 4It is the schematic diagram of Controller A - GTX. The conversion module A uses the chip STM32H743 to receive data through Ethernet and store the data in the memory EMMC. The controller A uses XC7K035 of Xilinx to communicate with the conversion module A through the FSMC bus, temporarily cache the data in the memory DDR, and through the internal GTX function of the controller A, use the IP core of DP to perform DP data conversion on the data in the memory DDR and convert it into a DP signal for output.
[0050] Figure 5 It is the schematic diagram of DP signal output, including a four - channel linear transfer driver (SN65DP141 chip) and a capacitor bank. The VCC1 - VCC12 terminals of the four - channel linear transfer driver are connected to the capacitor bank. The main function of the capacitor bank is to filter out high - frequency noise in the power supply;
[0051] The SN65DP141 chip mainly realizes the functions of receiving, processing, and outputting high - speed digital signals. The input high - speed serial signal is processed by the SN65DP141 chip, and then a DP signal is output to drive a display device or communicate with other high - speed digital devices.
[0052] The working principle of conversion module B and controller B: Through a bridging chip, which is mainly used to receive DP signals, decode them, and convert them into MIPI CPHY signals for driving the display screen. The DP signal is converted into a CPHY signal by the conversion module B and the controller B; Since the DP protocol and DP lines are used as the intermediate transmission lines, the transmission distance can be greatly increased.
[0053] Figure 6 It is the schematic diagram of conversion module B and controller B, which involves signal reception, processing, and output. The input DP signal is collected, error - corrected and decoded to improve the reliability of signal transmission, then audio - video processing is performed, and the processed signal is converted and sent. The main function is to convert the DP signal into a MIPI CPHY signal as described above.
[0054] The reference schematic diagram of the conversion circuit part is as follows: The DP receiving end is used as the input ( Figure 7 ), and the signal is converted through a bridging chip in the middle ( Figure 8 ), and the MIPI CPHY signal is output ( Figure 9 ).
[0055] Figure 7 In it, the DP receiving end includes the interface part J1, various resistors, and various connectors. The interface part J1 uses DP_Sink_Receptacle. The pins of the interface part J1 are connected to the resistor R1, resistor R7, and resistor R8. The pins of the interface part J1 are also connected to the connectors D1, D2, and D3.
[0056] Power supply, signal transmission and other operations are carried out with external devices through these pins. At the same time, a resistor network is used to stabilize the pin levels to ensure reliable signal transmission, realizing the connection and communication functions between DP interface devices.
[0057] Figure 8 In [description], the bridging chip U1A is used to receive and process DP signals. The DP signals are differential data signals such as DP_RX_D0+ and DP_RX_D0-, and the DP_RX_HPD hot plug detection signal.
[0058] Figure 9 In [description], the MIPI CPHY signal output includes the chip U3B, which has ports Port 0, Port 1, Port 2, and Port 3. Each port has multiple differential signal pairs, as well as the pin connection relationships corresponding to each channel (lane0, lane1, lane2). In Port 0, lane0_A_0 is connected to the D14 and D15 pins and is connected to other components through LMTX0_D0N and LMTX0_D0P.
[0059] The pin "D14" corresponding to "lane0_A_0" is connected to "LMTX0_D0N" and "LMTX0_D0P", which is a set of differential signals. Differential signals are widely used in high-speed data transmission. By transmitting data through a pair of signals with opposite phases, electromagnetic interference (EMI) can be effectively reduced and signal integrity can be improved.
[0060] In the present invention, an oscilloscope is used to capture the CPHY signal quality after extending the transmission distance by 3M, and the eye diagram test results ( Figure 10 ) are observed and no obvious abnormalities or interferences are found.
[0061] The overall operation process is as follows: 1. Turn on the host computer; 2. Connect the power cord, Ethernet cable, DP (DisplayPort) cable, and C-PHY cable in sequence; 3. Import customized image data; 4. Send data and the device works; 5. The screen lights up.
[0062] The present invention can increase the transmission distance from 10 - 15 cm to more than 3M, greatly solving the testing difficulties at the factory production end;
[0063] In the present invention, DP (DisplayPort) signals are interspersed. Through the differential and stable characteristics of DP (DisplayPort), the transmission stability problem is greatly solved;
[0064] The present invention improves the test yield and test efficiency while increasing a little cost, and increases the flexibility and portability of testing.
[0065] Although embodiments of the present invention have been shown and described, those of ordinary skill in the art will appreciate that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A method for improving the transmission distance of MIPI CPHY, characterized in that: It includes two - level data processing, namely the first - level data processing and the second - level data processing. The first - level data processing is carried out through the first - level data processing module, and the second - level data processing is carried out through the second - level data processing module; The first - level data processing module includes a conversion module A and a controller A, and the conversion module A and the controller A carry out DP signal output; The second - level data processing module includes a conversion module B and a controller B, and the conversion module B and the controller B restore the DP signal to a C - PHY signal for output.
2. The method for improving the transmission distance of MIPI CPHY according to claim 1, wherein: The steps of the two - level data processing are as follows: The host computer sends data to the first - level data processing module through Ethernet. The first - level data processing module includes a conversion module A and a controller A. The conversion module A receives the data from the host computer, converts the received data through the data conversion of the conversion module A, and converts the data into a DP signal for output through the controller A; The DP signal is sent to the second - level data processing module. The conversion module B receives the DP signal data, converts the received DP signal data through the conversion module B, restores the DP signal to a C - PHY signal through the controller B, and the C - PHY signal output is used to drive the display screen.
3. The method for improving the transmission distance of MIPI CPHY according to claim 2, wherein: Through the encoding and decoding method, the C - PHY signal is converted back to drive the display screen.
4. A method for improving the transmission distance of MIPI CPHY according to claim 1, characterized in that: The conversion module A uses the chip STM32H743 to receive data through Ethernet and stores the data in the memory EMMC. The controller A uses XC7K035 to communicate with the conversion module A through the FSMC bus, temporarily caches the data in the memory DDR, and uses the internal GTX function of the controller A and the IP core of DP to convert the data in the memory DDR into DP data and output it as a DP signal.
5. A method for improving the transmission distance of MIPI CPHY according to claim 1, characterized in that: The DP signal output includes a four - channel linear transfer driver and a capacitor bank. The VCC1 - VCC12 terminals of the four - channel linear transfer driver are connected to the capacitor bank. The four - channel linear transfer driver uses the SN65DP141 chip and is used for the reception, processing, and output of high - speed digital signals.
6. The method for improving the transmission distance of MIPI CPHY according to claim 1, characterized in that: The conversion module B accesses a bridge chip. The DP receiving end is used as an input to receive the DP signal, performs decoding processing on it, and performs signal conversion through the bridge chip in the middle, converts it into a MIPI CPHY signal, and outputs the MIPI CPHY signal to drive the display screen.
7. The method for improving the transmission distance of MIPI CPHY according to claim 6, characterized in that: The DP receiving end includes an interface part J1, various resistors, and various connectors. The interface part J1 uses DP_Sink_Receptacle. The pins of the interface part J1 are connected to the resistor R1, resistor R7, and resistor R8. The pins of the interface part J1 are also connected to the connector D1, connector D2, and connector D3.
8. A method for increasing the transmission distance of MIPI CPHY according to claim 6, characterized in that: The bridge chip U1A is used to receive and process the DP signal. The DP signal is an equal - difference differential data signal and a hot - plug detection signal.
9. A method for increasing the transmission distance of MIPI CPHY according to claim 6, characterized in that: The MIPI CPHY signal output includes the chip U3B, which has ports Port 0, Port 1, Port 2, and Port 3, and each port has multiple differential signal pairs.