Nitride ferroelectric integrated memory and preparation method thereof

Abstract

The invention discloses a nitride ferroelectric integrated memory which mainly solves the problems that an existing ferroelectric memory device is poor in reliability, low in storage density, complex in manufacturing process and difficult to be compatible with a CMOS (complementary metal oxide semiconductor) process. The device comprises a substrate, a buffer layer and a channel layer from bottom to top, a drain electrode is arranged on one side of the channel layer, a ferroelectric material layer is arranged on the other side of the channel layer, and the ferroelectric material layer is tightly attached to the channel layer, so that the manufacturing process is simplified, and the integration level is improved; a dielectric layer and a gate electrode are sequentially arranged in the middle above the channel layer; the ferroelectric material layer is made of a single crystal nitride ferroelectric material, a source electrode is arranged above the ferroelectric material layer, and the ferroelectric material layer and the source electrode form ohmic contact. The single-crystal nitride ferroelectric material with low dielectric constant, high Curie temperature and high breakdown voltage is used for replacing an oxide ferroelectric material, the reliability of the ferroelectric memory can be improved, the size of a memory unit can be reduced through the in-situ grown ferroelectric material, the integration level of the memory is improved, the process complexity is reduced, seamless integration with a CMOS process is achieved, and the performance of the memory is improved. The method can be used for digital storage circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a nitride ferroelectric integrated memory which can be used for digital storage circuits. Background Art

[0002] Ferroelectric materials are a class of materials with special crystal structures and properties. The arrangement of positive and negative ions inside the material changes with the change of the external electric field. Under the action of the external electric field, they show reversible polarization and can maintain a stable polarization direction after the electric field is removed. Controllable polarization makes ferroelectric materials have important application value in non-volatile memory. Ferroelectric memory has the advantages of fast read and write speed, low power consumption, high density and long life, and has broad application prospects in embedded systems, mobile communications, intelligent security and other fields. Ideal ferroelectric materials must meet the characteristics of small dielectric constant, high Curie temperature, strong polarization retention ability, and easy integration into CMOS process. At present, ferroelectric memory mainly uses PZT and SBT as ferroelectric storage materials. Compared with single crystal nitride ferroelectric materials, PZT and SBT have weak ferroelectric polarization, low Curie temperature, poor polarization retention ability, and are difficult to integrate with Si CMOS process, which cannot meet the further development of high reliability and high integration ferroelectric memory.

[0003] Patent document with application number CN201980062904.8 discloses a ferroelectric semiconductor device and a method for manufacturing a memory cell, which includes a substrate, an epitaxial layer, a dielectric layer, a gate, a source and a drain from bottom to top, and a ferroelectric capacitor structure composed of an electrode, a ferroelectric material layer and an electrode is connected at the top of the source through an interconnection line. The structure places the capacitor in the active area, and connects the lower electrode of the capacitor to the source end of the MOS tube through a conductive layer, such as Figure 1 The manufacturing process of this device is relatively complicated and cannot achieve high-density and large-scale integration.

[0004] Patent document with application number CN201910911592.5 discloses a semiconductor device with ferroelectric material and a method for manufacturing the same, which realizes three-dimensional ferroelectric storage by grooving inside an electrode stack including an interlayer insulating layer and a gate electrode structure and arranging a gate dielectric layer including ferroelectric material along the surface of the groove sidewall. This structure realizes high-density storage through three-dimensional stacking, which not only has a complex manufacturing process and high process difficulty, but also has low device reliability. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to provide a nitride ferroelectric integrated memory and a preparation method thereof, so as to reduce the process difficulty of device manufacturing and improve device reliability and process integration.

[0006] The technical solution of the present invention is achieved in this way:

[0007] 1. A nitride ferroelectric integrated memory, comprising a substrate, a buffer layer, a channel layer, a ferroelectric material layer, a dielectric layer, a gate electrode, a drain electrode and a source electrode, characterized in that:

[0008] The ferroelectric material layer is located on one side above the channel layer, and the two are in close contact, so as to simplify the manufacturing process steps and improve the device integration;

[0009] The source electrode is located above the ferroelectric material layer, and an ohmic contact is formed therebetween, serving as an output terminal of the electrical signal.

[0010] Furthermore, the ferroelectric material layer is made of any one of nitride ferroelectric materials such as ScAlN, YAlN, and BAlN, and its thickness is 5 nm - 100 nm.

[0011] Furthermore, the buffer layer is located above the substrate; the channel layer is located above the buffer layer.

[0012] Furthermore, the dielectric layer and the gate electrode are located in the middle part of the channel layer, and the drain electrode is located on the other side above the channel layer.

[0013] Furthermore, the substrate is made of any one of GaN, SiC or Si materials; the buffer layer is made of GaN material, and its thickness is 50 nm - 10 μm.

[0014] Furthermore, the channel layer is made of n + GaN material, with a thickness of 10 nm - 1 μm and a doping concentration of 1×10 19 cm -3 ~5×10 20 cm -3 ; the dielectric layer is made of any one of Si3N4, HfO2 or Al2O3 materials, and its thickness is 5 nm - 50 nm.

[0015] 2. A manufacturing method of a nitride ferroelectric integrated memory, characterized by including the following steps:

[0016] 1) On the upper part of the substrate, deposit GaN with a thickness of 50 nm - 10 μm as the buffer layer by using metal organic chemical vapor deposition technology or molecular beam epitaxy technology;

[0017] 2) By using metal organic chemical vapor deposition technology or molecular beam epitaxy technology, deposit n 19 cm -3 ~5×10 20 cm -3 GaN with a thickness of 10 nm - 1 μm and a doping concentration of 1×10 + as the channel layer on the buffer layer;

[0018] 3) Using metal-organic chemical vapor deposition technology or molecular beam epitaxy technology, grow a nitride ferroelectric material with a thickness of 5 nm - 100 nm on the first contact layer as the ferroelectric material layer;

[0019] 4) Using photolithography technology, with photoresist as a mask on the ferroelectric material layer, use dry etching method to etch the ferroelectric material layer to the surface of the channel layer to form a mesa;

[0020] 5) Using photolithography technology to etch source and drain electrode patterns on the surface of the channel layer and the ferroelectric material layer, then use electron beam evaporation process to deposit Ti / Al / Ni / Au metal, and anneal in a nitrogen atmosphere to form source and drain electrodes;

[0021] 6) Using atomic layer deposition technology, grow 5 nm - 50 nm of Si3N4 or HfO2 or Al2O3 as a dielectric layer in the region between the drain electrode above the channel layer and the ferroelectric material layer;

[0022] 7) Using photolithography technology to etch the gate electrode pattern on the surface of the dielectric layer, then use electron beam evaporation technology to deposit Ni / Au metal combination on the dielectric layer to form a gate electrode, completing the device fabrication.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] First, since the ferroelectric material layer is directly disposed on one side above the channel layer and formed on the channel layer by in-situ growth in the present invention, the epitaxial-level integration of the memory logic unit and the ferroelectric storage capacitor is realized, the manufacturing process of the ferroelectric memory is simplified, the size of the storage unit is reduced, the integration degree of the ferroelectric memory is improved, and the storage density is increased.

[0025] Second, using single-crystal nitride ferroelectric semiconductor to replace the traditional oxide material as the ferroelectric storage layer, and utilizing the characteristics of single-crystal nitride ferroelectric semiconductor material with low dielectric constant, high Curie temperature, and high breakdown voltage, the stability and reliability of the device can be improved.

[0026] Third, the present invention uses nitride-based semiconductor materials, which can be seamlessly integrated with CMOS process. Compared with the existing ferroelectric memories, the manufacturing process is simplified, the process integration degree is improved, and at the same time, the loss and interference of the interconnection line to the signal are eliminated, and the reliability of the storage is improved. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of an existing ferroelectric memory;

[0028] Figure 2 is a schematic structural diagram of the nitride ferroelectric integrated memory of the present invention;

[0029] Figure 3It is a schematic diagram of the implementation process for fabricating a nitrogen-polar nitride ferroelectric memory according to the present invention. Detailed implementation manners

[0030] The following further describes the embodiments of the present invention in detail with reference to the accompanying drawings:

[0031] Refer to Figure 2 , the nitride ferroelectric integrated memory of the present invention includes a substrate 1, a buffer layer 2, a channel layer 3, a ferroelectric material layer 4, a dielectric layer 5, a gate electrode 6, a drain electrode 7, and a source electrode 8, wherein:

[0032] The substrate 1 is made of any one of GaN, SiC, or Si materials;

[0033] The buffer layer 2 is located above the substrate 1 and is made of GaN material with a thickness of 50 nm - 10 μm;

[0034] The channel layer 3 is located above the buffer layer 2 and is made of n-GaN material with a thickness of 10 nm - 1 μm and a doping concentration of 1×10 19 cm -3 ~5×10 20 cm -3 ; + GaN material;

[0035] The ferroelectric material layer 4 is located above one side of the channel layer 3 and is in close contact with it to simplify the manufacturing process steps and improve the device integration. It is made of any one of nitride ferroelectric materials such as ScAlN, YAlN, and BAlN, and its thickness is 5 nm - 100 nm;

[0036] The dielectric layer 5 is located above the middle part of the channel layer 3 and is made of any one of Si3N4, HfO2, or Al2O3 materials, and its thickness is 5 nm - 50 nm;

[0037] The gate electrode 6 is located above the dielectric layer 5;

[0038] The drain electrode 7 is located above the other side of the channel layer 3;

[0039] The source electrode 8 is located above the ferroelectric material layer 4, and an ohmic contact is formed between them, serving as the output terminal of the electrical signal.

[0040] Refer to Figure 3 , the present invention provides the following three embodiments for fabricating a nitride ferroelectric integrated memory.

[0041] Embodiment 1: Fabricate a YAlN material with a ferroelectric material layer thickness of 50 nm on a SiC substrate. The buffer layer material is GaN with a thickness of 5 μm, and the channel layer thickness is 500 nm, n +The doping concentration of GaN is 1×10 20 cm -3 , and a nitride ferroelectric integrated memory with a dielectric layer material of HfO2 and a thickness of 25 nm.

[0042] Step 1: Use molecular beam epitaxy technology to epitaxially grow a GaN buffer layer on a SiC substrate, as shown in Figure 3 (a).

[0043] Place the SiC substrate into the molecular beam epitaxy equipment, set the temperature to 750 °C, the nitrogen flow rate to 3.2 sccm, the equilibrium vapor pressure of the gallium beam current to 9.5×10 -7 Torr, and the power of the nitrogen radio frequency source to 380 W. Epitaxially grow GaN with a thickness of 5 μm on the SiC substrate 1 as the buffer layer 2.

[0044] Step 2: Use molecular beam epitaxy technology to epitaxially grow a channel layer, as shown in Figure 3 (b).

[0045] Set the temperature to 550 °C, the nitrogen flow rate to 0.6 sccm, the equilibrium vapor pressure of the gallium beam current to 3.2×10 -7 Torr, and the power of the nitrogen radio frequency source to 250 W. Epitaxially grow n 20 cm -3 -type GaN with a thickness of 500 nm and a doping concentration of 1×10 + as the channel layer 3.

[0046] Step 3: Use molecular beam epitaxy technology to epitaxially grow a ferroelectric material layer, as shown in Figure 3 (c).

[0047] Set the temperature to 600 °C, the nitrogen flow rate to 0.6 sccm, the equilibrium vapor pressure of the aluminum beam current to 0.6×10 -7 Torr, the equilibrium vapor pressure of the yttrium beam current to 1.8×10 -8 Torr, and the power of the nitrogen radio frequency source to 320 W. Epitaxially grow YAlN with a thickness of 50 nm as the ferroelectric material layer 4 on the first contact layer 3.

[0048] Step 4: Use dry etching technology to etch the ferroelectric material layer to the surface of the channel layer, as shown in Figure 3 (d).

[0049] Set the Cl2 flow rate to 12 sccm, the pressure in the reaction chamber to 11 mTorr, and the electrode power to 180 W. Etch the ferroelectric material layer 4 to the surface of the channel layer 3 to form a mesa.

[0050] Step 5: Use photolithography technology, electron beam evaporation technology, and rapid thermal annealing technology to fabricate source and drain electrodes, as shown in Figure 3 (e).

[0051] 5.1) Use photolithography to form source and drain electrode patterns on the surfaces of the channel layer 3 and the ferroelectric material layer 4.

[0052] 5.2) Set the vacuum degree to be less than 1.8×10 -3 Pa, the power to be 400 W, and the evaporation rate to be . Under these process conditions, use electron beam evaporation to deposit Ti / Al / Ni / Au metals with a thickness of 40 nm / 60 nm / 40 nm / 80 nm in the source and drain electrode pattern regions.

[0053] 5.3) Set the temperature to 800 °C and the process conditions to be a nitrogen atmosphere. Anneal the source and drain metals for 5 minutes to complete the fabrication of the source electrode and the drain electrode.

[0054] Step 6, use atomic layer deposition technology to fabricate a dielectric layer, such as Figure 3 (f).

[0055] Set the temperature to 280 °C, the flow rate of ethylmethylamino hafnium to be 1200 sccm, the flow rate of H2O to be 110 sccm, and the flow rate of N2 to be 1000 sccm. Deposit HfO2 with a thickness of 25 nm as the dielectric layer 5 in the region between the drain electrode 7 and the ferroelectric material layer 4 above the channel layer 3.

[0056] Step 7, use photolithography technology and electron beam evaporation technology to fabricate an electrode, such as Figure 3 (g).

[0057] 7.1) Use photolithography to form a gate electrode pattern on the surface of the dielectric layer 5.

[0058] 7.2) Set the vacuum degree to be less than 1.2×10 -3 Pa, the power to be 400 W, and the evaporation rate to be . Under these process conditions, deposit Ni / Au metals with a thickness of 150 nm / 350 nm on the surface of the dielectric layer 5 to form a gate electrode and complete the device fabrication.

[0059] Example 2, fabricate a nitride ferroelectric integrated memory on a GaN substrate with a ScAlN material having a ferroelectric material layer thickness of 5 nm, a buffer layer material of GaN with a thickness of 50 nm, a channel layer thickness of 10 nm, and an n + GaN doping concentration of 1×10 19 cm -3 , and a dielectric layer material of Si3N4 with a thickness of 5 nm.

[0060] Step 1, deposit a buffer layer, such as Figure 3 (a).

[0061] Place the GaN substrate into a metalorganic chemical vapor deposition (MOCVD) equipment, and deposit GaN with a thickness of 50 nm as the buffer layer 2 on the GaN substrate 1 using the MOCVD technology;

[0062] The deposition process conditions are as follows: the temperature is 1000 °C, the pressure is 40 Torr, the ammonia flow rate is 5000 sccm, the hydrogen flow rate is 3500 sccm, and the gallium source flow rate is 200 sccm.

[0063] Step 2: Deposit the channel layer, as shown in Figure 3 (b).

[0064] Deposit GaN with a thickness of 10 nm and a doping concentration of 1×10 19 cm -3 as the channel layer 3 on the buffer layer 2 using the MOCVD technology;

[0065] The deposition process conditions are as follows: the temperature is 1000 °C, the pressure is 200 Torr, the ammonia flow rate is 5000 sccm, the hydrogen flow rate is 3500 sccm, the gallium source flow rate is 50 sccm, and the silicon source flow rate is 20 sccm.

[0066] Step 3: Deposit the ferroelectric material layer, as shown in Figure 3 (c).

[0067] Deposit ScAlN with a thickness of 5 nm as the ferroelectric material layer 4 on the channel layer 3 using the MOCVD technology;

[0068] The deposition process conditions are as follows: the temperature is 1000 °C, the pressure is 200 Torr, the ammonia flow rate is 5000 sccm, the hydrogen flow rate is 3500 sccm, the aluminum source flow rate is 50 sccm, and the scandium source flow rate is 5000 sccm.

[0069] Step 4: Etch the ferroelectric material to form a mesa, as shown in Figure 3 (d).

[0070] Use photolithography technology to fabricate a mask on the ferroelectric material layer 4;

[0071] Use dry etching technology to etch the ferroelectric material layer 4 to the surface of the channel layer 3 to form a mesa;

[0072] The etching process conditions are as follows: the Cl2 flow rate is 18 sccm, the reaction chamber pressure is 15 mTorr, and the electrode power is 160 W.

[0073] Step 5: Fabricate the source and drain electrodes, as shown in Figure 3 (e).

[0074] Use photolithography to form source and drain electrode patterns on the surfaces of the channel layer 3 and the ferroelectric material layer 4;

[0075] Use electron beam evaporation to deposit Ti / Al / Ni / Au metals with thicknesses of 20nm / 40nm / 30nm / 75nm in the source and drain electrode pattern regions, and anneal in a nitrogen atmosphere at 800 °C to form the source electrode and the drain electrode;

[0076] The process conditions for electron beam evaporation: the vacuum degree is less than 1.2×10 -3 Pa, the power is 400W, and the evaporation rate is

[0077] The process conditions for annealing: nitrogen atmosphere, the temperature is 830 °C, and the annealing time is 5 min.

[0078] Step six, deposit a dielectric layer, such as Figure 3 (f).

[0079] Use atomic layer deposition to deposit 5nm-thick Si3N4 as the dielectric layer 5 in the region between the drain electrode 7 and the ferroelectric material layer 4 above the channel layer 3;

[0080] The process conditions for atomic layer deposition are: the temperature is 300 °C, the pressure is 2000 mTorr, the Si source flow rate is 850 sccm, and the N2 flow rate is 1000 sccm.

[0081] Step seven, fabricate the gate electrode, such as Figure 3 (g).

[0082] Use photolithography to form a gate electrode pattern on the surface of the dielectric layer 5, and use electron beam evaporation to deposit Ni / Au metals with thicknesses of 120nm / 300nm on the dielectric layer 5 to form the gate electrode, completing the device fabrication;

[0083] The process conditions for electron beam evaporation are: the vacuum degree is less than 1.2×10 -3 Pa, the power is 400W, and the evaporation rate is

[0084] Example three, fabricate a nitride ferroelectric integrated memory with a 100nm-thick BAlN material as the ferroelectric material layer on a Si substrate, a 10μm-thick GaN as the buffer layer material, a 1μm-thick channel layer, and an n + GaN doping concentration of 5×10 20 cm -3 , and a 50nm-thick Al2O3 as the dielectric layer material.

[0085] Step A, deposit the GaN buffer layer, such as Figure 3 (a).

[0086] Place the Si substrate into a metalorganic chemical vapor deposition equipment. Using the metalorganic chemical vapor deposition technique, deposit a 10-μm-thick nitrogen-polar GaN as the buffer layer 2 on the Si substrate 1 under the process conditions of a temperature of 1300 °C, a pressure of 60 Torr, an ammonia flow rate of 5000 sccm, a hydrogen flow rate of 3500 sccm, and a gallium source flow rate of 200 sccm.

[0087] Step B, deposit an n + GaN channel layer, as shown in Figure 3 (b).

[0088] Using the metalorganic chemical vapor deposition technique, deposit a 1-μm-thick GaN with a doping concentration of 5×10 20 cm -3 as the channel layer 3 on the GaN buffer layer 2 under the process conditions of a temperature of 1100 °C, a pressure of 180 Torr, an ammonia flow rate of 5000 sccm, a hydrogen flow rate of 3500 sccm, a gallium source flow rate of 100 sccm, and a silicon source flow rate of 100 sccm.

[0089] Step C, deposit a BAlN ferroelectric material layer, as shown in Figure 3 (c).

[0090] Using the metalorganic chemical vapor deposition technique, deposit a 100-nm-thick BAlN as the ferroelectric material layer 4 on the first contact layer 3 under the process conditions of a temperature of 1100 °C, a pressure of 180 Torr, an ammonia flow rate of 5000 sccm, a hydrogen flow rate of 3500 sccm, an aluminum source flow rate of 4 sccm, and a boron source flow rate of 4000 sccm.

[0091] Step D, etch the ferroelectric material layer to form a mesa, as shown in Figure 3 (d).

[0092] Using the dry etching technique, etch the ferroelectric material layer 4 to the surface of the channel layer 3 to form a mesa under the process conditions of a Cl2 flow rate of 12 sccm, a reaction chamber pressure of 11 mTorr, and an electrode power of 180 W.

[0093] Step E, fabricate source and drain electrodes, as shown in Figure 3 (e).

[0094] E1) Use the photolithography process to lithographically form source and drain electrode patterns on the surfaces of the channel layer 3 and the ferroelectric material layer 4;

[0095] E2) Use the electron beam evaporation process under a vacuum of less than 1.2×10 -3Pa, with a power of 300W and an evaporation rate of Under the process conditions of , deposit Ti / Al / Ni / Au metals with a thickness of 60nm / 50nm / 40nm / 130nm in the source-drain electrode pattern area;

[0096] E3) Use rapid annealing technology to anneal the source-drain metal for 30s at a temperature of 1200°C in a nitrogen atmosphere to form an ohmic contact and obtain the source-drain electrodes.

[0097] Step F, fabricate the dielectric layer, as Figure 3 (f).

[0098] Use atomic layer deposition technology to deposit Al2O3 with a thickness of 50nm as the dielectric layer 5 in the area between the drain electrode 7 and the ferroelectric material layer 4 above the channel layer 3 under the process conditions of a temperature of 280°C, an Al(CH3)3 flow rate of 850sccm, an H2O flow rate of 350sccm, and an N2 flow rate of 1000sccm.

[0099] Step G, fabricate the gate electrode, as Figure 3 (g).

[0100] G1) Use photolithography to form a gate pattern by electro-lithography on the surface of the dielectric layer 5;

[0101] G2) Use electron beam evaporation technology to deposit Ni / Au metals with a thickness of 150nm / 320nm under the process conditions of a vacuum degree less than 1.2×10 -3 Pa, with a power of 300W and an evaporation rate of to form the gate electrode and complete the device fabrication.

[0102] The above description is only three specific examples of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the materials used above for the ferroelectric material layer, other nitride ferroelectric materials can also be used; in addition to the materials used above for the dielectric layer, other high-k dielectric materials can also be used; for the source-drain electrode metal materials, in addition to the metals used above, any one or any combination of Ni, Ti, Al, Ta, W, Mo, Ta can also be used; for the gate electrode metal materials, in addition to the metals used above, any one or any combination of Ni, Pt, Pd, Au, W can also be used. However, these modifications and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A nitride ferroelectric integrated memory, comprising a substrate (1), a buffer layer (2), a channel layer (3), a ferroelectric material layer (4), a dielectric layer (5), a gate electrode (6), a drain electrode (7), and a source electrode (8), characterized in that: The ferroelectric material layer (4) is located on one side above the channel layer (3), and the two are in close contact, so as to simplify the manufacturing process steps and improve the device integration; The source electrode (8) is located above the ferroelectric material layer (4), and an ohmic contact is formed between the two, serving as the output end of the electrical signal.

2. The nitride ferroelectric integrated memory according to claim 1, wherein: The ferroelectric material layer (4) is made of any one of nitride ferroelectric materials such as ScAlN, YAlN, and BAlN, and its thickness is 5 nm - 100 nm.

3. The nitride ferroelectric integrated memory according to claim 1, characterized in that: The buffer layer (2) is located above the substrate (1); The channel layer (3) is located above the buffer layer (2).

4. The nitride ferroelectric integrated memory according to claim 1, characterized in that: The dielectric layer (5) and the gate electrode (6) are located in the middle part of the channel layer (3), The drain electrode (7) is located on the other side above the channel layer (3).

5. The nitride ferroelectric integrated memory according to claim 1, characterized in that: The substrate (1) is made of any one of GaN, SiC, or Si materials; The buffer layer (2) is made of GaN material, and its thickness is 50 nm - 10 μm.

6. The nitride ferroelectric integrated memory according to claim 1, characterized in that: The channel layer (3) is made of n + GaN material with a thickness of 10 nm - 1 μm and a doping concentration of 1×10 19 cm -3 ~5×10 20 cm -3 ; The dielectric layer (5) is made of any one of Si3N4, HfO2, or Al2O3 materials, and its thickness is 5 nm - 50 nm.

7. A method for fabricating a nitride ferroelectric integrated memory, characterized in that, It includes the following steps: 1) On the upper part of the substrate (1), use metal organic chemical vapor deposition technology or molecular beam epitaxy technology to deposit GaN with a thickness of 50 nm - 10 μm as the buffer layer (2); 2) Using metalorganic chemical vapor deposition technology or molecular beam epitaxy technology, deposit an n-GaN with a thickness of 10 nm - 1 μm and a doping concentration of 1×10 19 cm -3 ~5×10 20 cm -3 as the channel layer (3); + ​ 3) Use metal organic chemical vapor deposition technology or molecular beam epitaxy technology to grow a nitride ferroelectric material with a thickness of 5 nm - 100 nm on the first contact layer (3) as the ferroelectric material layer (4); 4) Use photolithography technology, use photoresist as a mask on the ferroelectric material layer (4), and use dry etching method to etch the ferroelectric material layer (4) to the surface of the channel layer (3) to form a mesa; 5) Use photolithography technology to etch the source and drain electrode patterns on the surface of the channel layer (3) and the ferroelectric material layer (4), then use electron beam evaporation process to deposit Ti / Al / Ni / Au metal, and anneal in a nitrogen atmosphere to form the source electrode and the drain electrode; 6) Use atomic layer deposition technology to grow 5 nm - 50 nm of Si3N4, HfO2, or Al2O3 between the drain electrode above the channel layer (3) and the ferroelectric material layer as the dielectric layer (5); 7) Use photolithography technology to etch the gate electrode pattern on the surface of the dielectric layer (5), and then use electron beam evaporation technology to deposit a Ni / Au metal combination on the dielectric layer (5) to form the gate electrode and complete the device manufacturing.

8. The method according to claim 7, wherein: For the metal organic chemical vapor deposition in steps 1) - 3), the process conditions are as follows: The temperature is 1000°C - 1300°C; the pressure is 40 Torr - 200 Torr; The flow rate of ammonia gas is 5000 sccm; the flow rate of hydrogen gas is 3500 sccm; The flow rate of aluminum source is 4 sccm - 50 sccm; the flow rate of gallium source is 50 sccm - 200 sccm; The flow rate of silicon source is 20 sccm - 100 sccm; the flow rate of scandium source is 2000 sccm - 5000 sccm; The flow rate of yttrium source is 1000 sccm - 3000 sccm; the flow rate of boron source is 1500 sccm - 4000 sccm.

9. The method according to claim 7, wherein: For the molecular beam epitaxy method in the steps 1) - 3), the process conditions are as follows: The temperature is 550°C - 750°C; the flow rate of nitrogen gas is 0.6 sccm - 3.2 sccm; The equilibrium vapor pressure of the gallium beam is 3.2×10 -7 Torr - 9.5×10 -7 Torr; The equilibrium vapor pressure of the aluminum beam current is 0.6×10 -7 Torr - 3.5×10 -7 Torr; The equilibrium vapor pressure of silicon beam is 0.8×10 -9 Torr - 5.4×10 -9 Torr; The equilibrium vapor pressure of the scandium beam is 0.9×10 -8 Torr - 2.8×10 -8 Torr; The equilibrium vapor pressure of the yttrium beam current is 0.6×10 -8 Torr - 1.8×10 -8 Torr; The equilibrium vapor pressure of the boron beam is 0.3×10 -8 Torr - 1.2×10 -8 Torr; The power of the nitrogen radio frequency source is 250 W - 380 W.

Images