Field effect transistor and manufacturing method thereof
By designing non-overlapping first and second source injection regions and gate injection regions structures in the field effect transistor, the gate leakage capacitance is reduced, and the problems of long time and high switching losses in the prior art are solved, device reliability is improved and application process is simplified.
Patent Information
- Application Number
- CN202510467844.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-18
AI Technical Summary
Existing vertical junction field effect transistor devices have problems such as large gate leakage capacitance, long Miller platform time, high switching losses, and the need for additional reverse diodes.
A field effect transistor structure is designed, including forming an epitaxial layer on the substrate, the first and second source injection regions on the upper part of the epitaxial layer do not overlap and are electrically connected, the gate injection region is located below the second source injection region, isolates by an insulating layer, reduces the gate leakage capacitance, and forms a drain injection region on the lower surface of the substrate.
Reduces Miller platform time, reduces device switching losses, improves device reliability, simplifies application processes, and avoids additional reverse diode settings.
Smart Images
Figure CN120343952A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to semiconductor technology, and particularly to a field effect transistor and a manufacturing method thereof. Background Art
[0002] Vertical junction field effect transistor devices have high input impedance, low noise, low power consumption, good thermal stability and radiation resistance, and are more suitable for use in portable devices and high-density integrated circuits. An existing vertical junction field effect transistor device is as shown in Figure 1 which forms a longitudinal channel by etching and implantation. Its bottom is the drain, the top is the n+ source, and the left and right sides are the gates, and a gate contact is formed at the bottom of the groove.
[0003] In the above existing solution, the gate-drain capacitance is large, which will affect the Miller plateau, resulting in an increase in the turn-on and turn-off time of the device, thereby increasing the switching loss. There is a large gate leakage when the device breaks down, and the vertical channel is not protected. This device needs to be additionally connected with a reverse diode in application, which increases the process complexity. Summary of the Invention
[0004] To solve one of the above technical defects, an embodiment of the present application provides a field effect transistor and a manufacturing method thereof.
[0005] According to the first aspect of the embodiments of the present application, a field effect transistor is provided, including:
[0006] A substrate;
[0007] An epitaxial layer formed on the substrate;
[0008] A first source injection region and a second source injection region formed on the upper part of the epitaxial layer; the first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region; the first source injection region and the second source injection region are electrically connected through a metal structure;
[0009] A gate injection region formed below the second source injection region, and the gate injection region is located on both sides of the region below the second source injection region;
[0010] A drain injection region formed on the lower surface of the substrate.
[0011] According to the second aspect of the embodiments of the present application, a manufacturing method of a field effect transistor is provided, including:
[0012] Forming an epitaxial layer on the upper surface of the substrate;
[0013] Digging a groove in a partial region on the upper surface of the epitaxial layer to form a groove portion, and the epitaxial layer beside the groove portion is a protruding portion;
[0014] A first source injection region is formed in the epitaxial layer below the groove portion;
[0015] An insulating layer is formed on the upper surface of the first source injection region;
[0016] Gate injection regions are formed on both sides of the protruding portion;
[0017] A second source injection region is formed on the upper portion of the protruding portion. The first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region;
[0018] A metal structure is formed above the first source injection region and the second source injection region, and the metal structure is electrically connected to the first source injection region and the second source injection region respectively;
[0019] A drain injection region is formed on the lower surface of the substrate.
[0020] In the technical solution provided by the embodiment of the present application, an epitaxial layer is formed on the substrate, and a first source injection region and a second source injection region are formed on the upper portion of the epitaxial layer; the first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region; the first source injection region and the second source injection region are electrically connected through a metal structure; a gate injection region is further formed below the second source injection region, and the gate injection region is located on both sides of the region below the second source injection region; the drain injection region is formed on the lower surface of the substrate, and the first source injection region is arranged below the gate injection region, which can reduce the gate-drain capacitance, thereby reducing the time of the Miller plateau and reducing the device switching loss. Description of the Drawings
[0021] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:
[0022] Figure 1 It is a schematic structural diagram of a vertical junction field effect transistor in the related art;
[0023] Figure 2 It is a schematic structural diagram of the field effect transistor provided by the embodiment of the present application;
[0024] Figure 3 It is a flowchart of the manufacturing method of the field effect transistor provided by the embodiment of the present application;
[0025] Figure 4 It is a schematic structural diagram of forming an epitaxial layer on the substrate in the manufacturing method of the field effect transistor provided by the embodiment of the present application;
[0026] Figure 5 Schematic diagram of the structure for grooving on the epitaxial layer in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0027] Figure 6 Schematic diagram of the structure for forming the first source injection region in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0028] Figure 7 Schematic diagram of the structure for forming the insulating layer in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0029] Figure 8 Schematic diagram of the structure for etching back the insulating layer to the surface of the first source injection region in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0030] Figure 9 Schematic diagram of the structure for forming the gate injection region in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0031] Figure 10 Schematic diagram of the structure for forming the second source injection region in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0032] Figure 11 Two-dimensional schematic diagram of the structure for forming the second source injection region in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0033] Figure 12 Schematic diagram of the structure for forming the gate silicide layer in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0034] Figure 13 Two-dimensional schematic diagram of the structure for forming the gate silicide layer in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0035] Figure 14 Schematic diagram of the structure for forming the first metal hole and the second metal hole in the field effect transistor manufacturing method provided by the embodiment of the present application;
[0036] Figure 15 Device doping diagram of the field effect transistor provided by the embodiment of the present application;
[0037] Figure 16 Breakdown voltage BV electric field distribution diagram of the field effect transistor provided by the embodiment of the present application;
[0038] Figure 17 Vgs-Ids curve graph of the field effect transistor provided by the embodiment of the present application;
[0039] Figure 18Simulation diagram of applying reverse Vds to the field effect transistor provided by the embodiment of the present application;
[0040] Figure 19 Curve graph of applying reverse Vds to the field effect transistor provided by the embodiment of the present application.
[0041] Reference numerals:
[0042] 1 - Substrate;
[0043] 2 - Epitaxial layer; 21 - Groove portion;
[0044] 3 - First source injection region;
[0045] 4 - Insulating layer;
[0046] 5 - Gate injection region;
[0047] 6 - Second source injection region;
[0048] 7 - Gate silicide layer;
[0049] 81 - First metal hole; 82 - Second metal hole;
[0050] 9 - Metal layer. Detailed implementation manners
[0051] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further details the exemplary embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0052] As Figure 2 shown, the field effect transistor provided in this embodiment includes: a substrate 1, an epitaxial layer 2, a first source injection region 3, a gate injection region 5, a second source injection region 6, and a drain injection region.
[0053] Among them, the substrate 1 can be a silicon substrate or a silicon carbide substrate, etc. The epitaxial layer 2 is formed on the upper surface of the substrate 1 by an epitaxial process.
[0054] The first source injection region 3 and the second source injection region 6 are formed on the upper part of the epitaxial layer 2, and there is no overlapping part between the first source injection region 3 and the second source injection region 6 in the thickness direction, and the top surface height of the first source injection region 3 is lower than the bottom surface of the second source injection region 6; the first source injection region 3 and the second source injection region 6 are electrically connected through a metal structure.
[0055] One implementation is as follows: A groove is dug downward in a partial area on the upper surface of the epitaxial layer 2 to form a groove portion, and the two side walls of the groove portion serve as protruding portions. The first source injection region 3 is formed in the epitaxial layer 2 below the bottom surface of the groove portion, and the second source injection region 6 is formed below the top surface of the protruding portion, so that the first source injection region 3 is lower than the second source injection region 6.
[0056] The gate injection region 5 is formed on both sides of the protruding portion and is located below the second source injection region 6.
[0057] The drain injection region is formed on the lower surface of the substrate 1 (not shown in the figure).
[0058] The field effect transistor obtained by the above solution belongs to a vertical junction field effect transistor. By arranging the first source injection region below the gate injection region, the gate-drain capacitance can be reduced, thereby reducing the time of the Miller plateau and reducing the switching loss of the device.
[0059] The technical solution provided in this embodiment forms an epitaxial layer on the substrate, and a first source injection region and a second source injection region formed on the upper part of the epitaxial layer; the first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region; the first source injection region and the second source injection region are electrically connected through a metal structure; a gate injection region is further formed below the second source injection region, and the gate injection region is located on both sides of the region below the second source injection region; the drain injection region is formed on the lower surface of the substrate. By arranging the first source injection region below the gate injection region, the gate-drain capacitance can be reduced, thereby reducing the time of the Miller plateau and reducing the switching loss of the device.
[0060] Moreover, by arranging the first source injection region below the gate injection region, the first source injection region can absorb part of the electric field, reduce the electric field in the channel, thereby reducing channel punch-through. There is no breakdown large current in the gate, which can prevent the device from being burned due to channel punch-through and improve the reliability of the device.
[0061] Further, an insulating layer 4 is provided on the upper surface of the first source injection region 3, which can isolate the first source injection region 3 from the upper regions.
[0062] Based on the above technical solution, for the electrical connection manner between the first source injection region 3 and the second source injection region 6, this embodiment provides an implementation: An insulating layer is formed on the first source injection region 3 and the second source injection region 6, and a first metal hole 81 and a second metal hole 82 are formed in the insulating layer. Among them, the first metal hole 81 is correspondingly in electrical contact with the first source injection region 3, and the second metal hole 82 is correspondingly in electrical contact with the second source injection region 6.
[0063] Then, a metal layer 9 is formed on the insulating layer, and the metal layer 9 is in electrical contact with the first metal hole 81 and the second metal hole 82 respectively. The first metal hole 81, the second metal hole 82, and the metal layer 9 serve as a metal structure to connect the first source injection region 3 and the second source injection region 6.
[0064] In actual operation, each first source injection region 3 is connected to the metal layer 9 through the first metal hole 81. In the attached drawings of this embodiment, only the first source injection region 3 on the right is shown to be connected to the metal layer 9 through the first metal hole 81, and the remaining first source injection regions 3 are not shown to be connected to the first metal hole 81 to simplify the drawings and clearly display.
[0065] On the basis of the above technical solution, a gate silicide layer 7 is further formed on the outer surface of the gate injection region 5 facing away from the other gate injection region 5. The top surface of the gate silicide layer 7 is lower than the bottom surface of the second source injection region 6, and insulation is maintained between the gate silicide layer 7 and the second source injection region 6. The gate silicide layer 7 can be formed by alloying metals such as nickel and titanium with silicon materials, has a high conductivity, can reduce the gate resistance, and improve the on and off capabilities of the field effect transistor, thereby achieving fast turn-on or conduction.
[0066] The distance between the gate silicide layer 7 and the second source injection region 6 is greater than 0.1 μm, which can keep good insulation between the two. The width of the gate silicide layer 7 (the dimension in the left-right direction in the figure) is 90 nm - 110 nm, for example, 100 nm, which can have better conductivity.
[0067] Furthermore, the conductivity type of the first source injection region 3 is P+, and the conductivity type of the epitaxial layer 2 is N-, so that the P+-type first source injection region 3 and the N-type epitaxial layer 2 form a PN junction, which can meet the requirement of reverse diode conduction. It is equivalent that the device has the function of a reverse diode, so the device no longer needs to be additionally provided with a reverse diode during application, which can simplify the application process.
[0068] The above-mentioned substrate 1 is an N+-type substrate, with a thickness of more than 10 μm and a doping concentration greater than 1e17 cm -3 。
[0069] The epitaxial layer 2 is N-type, with a thickness greater than 1 μm and a doping concentration less than 1e18 cm -3 , which can improve the breakdown voltage of the device to a certain extent.
[0070] The first source injection region 3 is P+-type, with a doping concentration greater than 1e18 cm -3 。
[0071] The insulating layer 4 is specifically an oxide layer, such as a silicon dioxide layer, with a thickness greater than 100 nm.
[0072] The gate injection region 5 is of P+ type, and the doping concentration is greater than 1e18 cm -3 .
[0073] The second source injection region 6 is of N+ type, and the doping concentration is greater than 1e18 cm -3 .
[0074] Based on the above technical solutions, this embodiment provides a manufacturing method of a field effect transistor for manufacturing the field effect transistor provided in any of the above contents. As Figure 3 shown, the manufacturing method of the field effect transistor provided in this embodiment includes:
[0075] Step 101: Form an epitaxial layer on the upper surface of the substrate.
[0076] Specifically, an N-type epitaxial layer 2 is formed on the upper surface of the N+ type substrate through an epitaxial process, as Figure 4 shown.
[0077] Step 102: Grooves are dug in a partial area on the upper surface of the epitaxial layer to form a groove portion, and the epitaxial layer beside the groove portion is a protruding portion.
[0078] Grooves are dug in a partial area on the upper surface of the epitaxial layer 2 through an etching process to form a groove portion 21, and the epitaxial layer 2 on both sides of the groove portion 21 serves as a protruding portion, as Figure 5 shown.
[0079] Step 103: A first source injection region is formed in the epitaxial layer below the groove portion.
[0080] A P+ type first source injection region 3 is formed by injection in the epitaxial layer 2 below the bottom surface of the groove portion 21, as Figure 6 shown.
[0081] Step 104: An insulating layer is formed on the upper surface of the first source injection region.
[0082] Specifically, an insulating layer 4 is formed on the surfaces of the first source injection region 3 and the remaining part of the epitaxial layer 2, as Figure 7 shown.
[0083] Then, a part of the insulating layer 4 is removed, and the back etching is performed until a part located on the upper surface of the first source injection region 3 is reserved, as Figure 8 shown.
[0084] Step 105: Gate injection regions are formed on both sides of the protruding portion.
[0085] Gate injection regions 5 are formed by injection on both sides of the protruding portion of the epitaxial layer 2. Specifically, an inclined injection process can be adopted, and the gate injection regions 5 are formed by injecting at an angle towards both sides of the protruding portion, as Figure 9 shown.
[0086] Step 106: A second source injection region is formed on the upper portion of the protruding portion. There is no overlapping portion between the first source injection region and the second source injection region in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region.
[0087] An N+-type second source injection region 6 is formed by injection on the upper portion of the protruding portion (i.e., below the upper edge of the protruding portion), as Figure 10 and Figure 11 shown. The second source injection region 6 is located above the gate injection region 5.
[0088] In one embodiment: After the second source injection region 6 is formed, a gate silicide layer 7 is formed on the outer surface of the gate injection region 5 facing away from the other gate injection region 5. The top surface of the gate silicide layer 7 is lower than the bottom surface of the second source injection region 6, as Figure 12 and Figure 13 shown.
[0089] Step 107: A metal structure is formed above the first source injection region and the second source injection region, and the metal structure is electrically connected to the first source injection region and the second source injection region respectively.
[0090] In one embodiment: First, an insulating layer is formed on the upper surfaces of the first source injection region 3 and the second source injection region 6. Then, a first metal hole 81 and a second metal hole 82 are etched and filled in the insulating layer. The first metal hole 81 is correspondingly in electrical contact with the first source injection region 3, and the second metal hole 82 is correspondingly in electrical contact with the second source injection region 6, as Figure 14 shown.
[0091] After that, a metal layer 9 is formed on the upper surface of the insulating layer. The metal layer 9 is electrically connected to the first metal hole 81 and the second metal hole 82 respectively. The first metal hole 81, the second metal hole 82, and the metal layer 9 serve as a metal structure to connect the first source injection region 3 and the second source injection region 6, as Figure 2 shown.
[0092] Step 108: A drain injection region is formed on the lower surface of the substrate.
[0093] Subsequently, a metal lead-out layer is further included to lead out the electrical signals of the source, drain, and gate.
[0094] In the above technical solution, a lower first source injection region 3 and a higher second source injection region 6 are formed in the epitaxial layer 2. The two are electrically connected through a metal structure; and a gate injection region 5 is formed below the second source injection region 6. The first source injection region 3 is isolated from the gate injection region 5 through the insulating layer 4 on its surface, which can reduce the gate-drain capacitance, thereby reducing the time of the Miller plateau and reducing the switching loss of the device.
[0095] Moreover, a first source injection region is provided below the gate injection region. The first source injection region can absorb part of the electric field, reducing the electric field in the channel, thereby reducing channel punch-through. Without gate breakdown large current, it can prevent the device from burning out due to channel punch-through and improve device reliability.
[0096] Figure 15 This is the device doping diagram of the field effect transistor provided in this embodiment. In the figure, the red region is N-type doping and the blue region is P-type doping.
[0097] Figure 16 This is the breakdown voltage BV electric field distribution diagram of the field effect transistor provided in the embodiment of the present application. As Figure 16 shown, the drain is located at the bottom of the device, and the gate is located at the top of the device. The first source injection region is used to absorb part of the electric field, thereby reducing the channel electric field between the source and the drain and improving device reliability.
[0098] The field effect transistor device provided in this embodiment is simulated and tested, and the obtained data and curves are as follows in the table and Figure 17 .
[0099] In the device provided in this embodiment, the gate-source capacitance Cgs has a significant decrease compared with the prior art, thereby being able to improve the on and off speeds of the device. The Miller capacitance (also known as: reverse isolation capacitance) Crss is much lower than the prior art, reducing the time of the Miller plateau and reducing the device switching loss, with a relatively prominent effect.
[0100] The threshold voltage Vth is reduced to half of the prior art. After testing, the device provided in this embodiment can conduct when the gate-source voltage Vgs is -3.3V, which can effectively reduce the switching loss of the device.
[0101] Cgs (pF) Crss (pF) Coss (pF) Vth (V) BV (V) Rsp (mΩ*cm2) This embodiment 850 3 100 -3.3 1400 0.7 Existing SiC JFET technology 1008 95 100 -6.6 1400 0.7
[0102] In addition, as Figure 18 and Figure 19 shown, when a reverse voltage Vds is applied between the drain and the source of the device provided in this embodiment, the drain-source current Ids gradually increases. The P+-type first source injection region 3 and the N--type epitaxial layer 2 form a PN junction, which can meet the requirements of reverse diode conduction, equivalent to that the device has the function of a reverse diode. When a reverse drain-source current is applied, the reverse diode conducts, and the device no longer needs to be additionally provided with a reverse diode during application, which can simplify the application process. Figure 18 The red region in is the large current region, and the arrow indicates the current flow direction during reverse conduction.
[0103] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.
[0104] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.
[0105] In the present application, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0106] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.
[0107] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.
Claims
1. A field effect transistor, characterized in that, Comprising: A substrate; An epitaxial layer formed on the substrate; A first source injection region and a second source injection region formed on the upper part of the epitaxial layer; the first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region; the first source injection region and the second source injection region are electrically connected through a metal structure; A gate injection region formed below the second source injection region, and the gate injection region is located on both sides of the region below the second source injection region; A drain injection region formed on the lower surface of the substrate.
2. The field effect transistor according to claim 1, wherein A groove portion is formed by downward depression of the upper surface of the epitaxial layer, and the two side walls of the groove portion are protruding portions; the first source injection region is located below the bottom surface of the groove portion, and the second source injection region is located below the top surface of the protruding portion; The gate injection region is located on both sides of the protruding portion.
3. The field effect transistor according to claim 1, wherein Further comprising: An insulating layer formed on the first source injection region and the second source injection region, and the insulating layer is provided with a first metal hole and a second metal hole; The first metal hole corresponds to make electrical contact with the first source injection region, and the second metal hole corresponds to make electrical contact with the second source injection region; A metal layer formed on the insulating layer and electrically contacting the first metal hole and the second metal hole respectively; the first metal hole, the second metal hole and the metal layer serve as the metal structure to connect the first source injection region and the second source injection region.
4. The field effect transistor according to any one of claims 1-3, characterized in that Further comprising: A gate silicide layer formed on the outer side surface of the gate injection region facing away from the other gate injection region; the top surface of the gate silicide layer is lower than the bottom surface of the second source injection region.
5. The field effect transistor according to claim 1, characterized in that, The conductivity type of the first source injection region is P+, and the conductivity type of the epitaxial layer is N-.
6. The field effect transistor according to claim 5, characterized in that, The thickness of the epitaxial layer is greater than 1 μm.
7. The field effect transistor according to claim 4, wherein The width of the gate silicide is 90 nm - 110 nm.
8. A method for manufacturing a field effect transistor, characterized in that, Comprising: Forming an epitaxial layer on the upper surface of the substrate; Digging a groove in a partial region of the upper surface of the epitaxial layer to form a groove portion, and the epitaxial layer beside the groove portion is a protruding portion; Forming a first source injection region in the epitaxial layer below the groove portion; Forming an insulating layer on the upper surface of the first source injection region; Forming gate injection regions on both sides of the protruding portion; Forming a second source injection region on the upper part of the protruding portion, the first source injection region and the second source injection region do not overlap in the thickness direction, and the top surface height of the first source injection region is lower than the bottom surface of the second source injection region; Forming a metal structure on the first source injection region and the second source injection region, and the metal structure is electrically connected to the first source injection region and the second source injection region respectively; Forming a drain injection region on the lower surface of the substrate.
9. The manufacturing method according to claim 8, wherein, Forming a metal structure on the first source injection region and the second source injection region, comprising: Forming an insulating layer on the upper surfaces of the first source injection region and the second source injection region; Providing a first metal hole and a second metal hole in the insulating layer; the first metal hole corresponds to make electrical contact with the first source injection region, and the second metal hole corresponds to make electrical contact with the second source injection region; Forming a metal layer on the upper surface of the insulating layer, and the metal layer is electrically contacted with the first metal hole and the second metal hole respectively; the first metal hole, the second metal hole and the metal layer serve as the metal structure to connect the first source injection region and the second source injection region.
10. The manufacturing method according to claim 8 or 9, characterized in that, After forming the second source injection region, further comprising: A gate silicide layer is formed on an outer surface of the gate injection region facing away from the other gate injection region, and a top surface of the gate silicide layer is lower than a bottom surface of the second source injection region.