Groove type MOS transistor power device and preparation method thereof

Abstract

The invention provides a groove type MOS (Metal Oxide Semiconductor) transistor power device and a preparation method thereof. The device includes a substrate, an epitaxial layer, a first trench, a second trench, a gate insulating layer, and a gate material. The first trench and the second trench are distributed on the epitaxial layer and are physically isolated through the gate insulating layer. And the gate insulating layer of the first groove is thicker, so that the voltage resistance is enhanced. The preparation method comprises the steps of groove forming, gate insulation layer and gate material filling, graphical etching, well region and source region forming through ion implantation, metal wiring forming and the like. The device has the advantages of high voltage resistance, low electric leakage and low power consumption, is suitable for power electronic application, improves the reliability and efficiency, and meets the development requirements of high-performance power devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to a trench MOS transistor power device and a preparation method thereof. Background Art

[0002] With the continuous progress of microelectronics technology, power MOS transistor devices have gradually replaced bipolar devices and become the mainstream of power device development due to their advantages such as high input impedance, low loss, fast switching characteristics, no risk of secondary breakdown, wide safe operating area, excellent dynamic performance, and easy coupling with the front-stage circuit to achieve large current and high conversion efficiency. Currently, the power devices on the market mainly include planar diffused MOS transistors and trench MOS transistors. To solve the problem that the channel occupies a large area during integration in planar diffused MOS transistors, trench MOS transistors have been developed. The gate structure of this transistor is built vertically in the channel perpendicular to the substrate surface, thus reducing the space occupied by the channel. Trench MOS transistors have the same working principle as planar diffused MOS transistors, but due to the adoption of a vertical channel design, their sidewalls can be used to fabricate the gate, so the occupied area is smaller. This not only improves the integration degree of the device but also effectively reduces the on-resistance and driving voltage. Therefore, trench MOS transistors have become an ideal choice for pursuing ultra-low on-state drain-source resistance performance.

[0003] However, with the further reduction of the size of trench MOS devices, the breakdown voltage problem of polysilicon gates has become increasingly prominent, especially at the trench positions at the edges of the devices, which has led to increased leakage current and power consumption. Some existing patent documents have proposed some solutions to these problems. For example, the depletion-type MOS transistor provided in patent publication No. CN102694012B includes a source electrode, a drain electrode, a lightly doped region, a gate electrode, a first conductive channel, and a second conductive channel, which is not easily broken down and the reliability is improved to some extent. However, there is still room for improvement in reducing leakage current and power consumption.

[0004] Therefore, the present invention proposes a novel trench MOS transistor power device, aiming to improve the leakage problem of polysilicon gates and reduce power consumption, thereby enhancing the comprehensive performance of MOS transistor devices. The device of the present invention has higher reliability and efficiency in power electronics applications, meeting the requirements of modern power electronics devices for high-performance power devices. Summary of the Invention

[0005] The object of the present invention is to provide a trench MOS transistor power device and its manufacturing method. Through innovative trench design and optimization of the gate insulating layer thickness, the breakdown voltage performance and electrical performance of the device are significantly improved, while leakage and power consumption are reduced. This enables the trench MOS transistor power device to have higher reliability and efficiency in power electronics applications, meeting the development requirements of high-performance power devices.

[0006] The technical solution adopted by the present invention to solve its technical problems is as follows: The trench MOS transistor power device adopts a unique trench structure design, dividing the trench into a first trench and a second trench. The first trench is mainly distributed around the periphery of the chip, and the second trench is distributed inside the first trench, which helps to improve the breakdown voltage performance of the device, reduce leakage, and lower power consumption.

[0007] For claim 1, the MOS transistor power device includes the following components: a substrate; an epitaxial layer located on the substrate; at least two trenches, namely the first trench and the second trench, where the first trench is mainly distributed around the periphery of the chip, and the second trench is located inside the first trench; a gate insulating layer and a gate material, which are respectively filled in the first trench and the second trench, and physical isolation is achieved through the gate insulating layer; wherein, the gate insulating layer far from the inner side of the second trench in the first trench is thicker than the gate insulating layer closer to the inner side of the second trench. The manufacturing method of the trench MOS transistor power device includes the following steps: forming the first trench and the second trench on the substrate silicon with an epitaxial layer; filling the gate material and the gate insulating layer material in the first trench and the second trench respectively; achieving physical isolation of the gate material in the first trench and the second trench through the gate insulating layer; further, ensuring that the gate insulating layer far from the inner side of the second trench in the first trench is thicker than the gate insulating layer closer to the inner side of the second trench to enhance the breakdown voltage performance outside the chip, reduce leakage, and effectively reduce the energy consumption of the device.

[0008] Preferably, for claim 2, the first trench and the second trench are formed on the epitaxial layer through semiconductor processes. The first trench is mainly located around the periphery of the chip, and the second trench is located inside the first trench, optimizing the layout and performance of the device. The gate insulating layer and the gate material are filled in the first trench and the second trench respectively. The gate insulating layer is used to isolate the gate material, prevent current leakage, and improve the breakdown voltage performance of the device.

[0009] Further, the gate material is used to control the conduction and cutoff of the channel. The well region and the source region are respectively formed in the epitaxial layer through the ion implantation process. Ion implantation is a commonly used doping technology that changes the electrical properties of semiconductor materials by implanting specific types of ions into them. In the present invention, the conduction types of the well region and the source region are different, and the conduction type of the source region is the same as that of the epitaxial layer, which helps to form an effective PN junction, improve the switching performance of the device, enable the trench MOS transistor power device to improve the breakdown voltage performance while maintaining a small device size, reduce leakage current, lower power consumption, and optimize the electrical performance.

[0010] Regarding claim 3, the first trench and the second trench have the same width, as well as the same depth and vertical angle, which facilitates more precise control during the manufacturing process and ensures the consistency of the device performance between different regions. The first trench is located at the edge of the chip, forming two continuous trench structures. The edge layout can improve the breakdown voltage performance of the device, especially in the edge region of the chip, which is a part prone to leakage current and breakdown in traditional designs. The edge layout of the first trench reduces the risk of leakage current and breakdown. The second trench is located in the central region of the chip and consists of multiple trenches arranged side by side. The multi-trenches in the central region can optimize the current distribution inside the device, improve the conduction ability and overall performance of the device.

[0011] Regarding claim 4, the gate insulating layers used to fill the first trench and the second trench are both composed of silicon dioxide (SiO2) material, and silicon dioxide, as an insulating layer, has excellent electrical properties, including high breakdown voltage, good thermal stability, and chemical stability.

[0012] Further, the gate insulating layer of the first trench is composed of a combination of two silicon dioxide layers: one is the silicon dioxide layer formed through the high-temperature thermal oxidation process, and the other is the silicon dioxide layer formed through the plasma-enhanced chemical vapor deposition (PECVD) method. The double-layer structure can provide better insulation performance and mechanical support, and may also help to improve the filling quality of the trench and reduce stress.

[0013] Even further, the gate insulating layer of the second trench is only composed of the silicon dioxide layer formed through high-temperature thermal oxidation, which simplifies the manufacturing process while still providing sufficient insulation performance. The thickness and formation conditions of the gate insulating layer of the second trench are the same as those of the high-temperature thermal oxidation layer in the first trench, ensuring that the insulating layers of the two trenches have similar electrical properties, thereby achieving a more uniform electric field distribution and more stable performance throughout the device.

[0014] For claim 5, both the first trench and the second trench are initially filled with two layers of silicon dioxide. The first layer is a silicon dioxide layer formed by a high-temperature thermal oxidation process, and the second layer is a silicon dioxide layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. This initial filling provides a basic insulating layer for the trenches.

[0015] Furthermore, a patterning process is employed. After the initial filling is completed, the silicon dioxide layer in the trenches is processed through the patterning process. This step can use wet or dry etching techniques to precisely remove the silicon dioxide layer in the second trench and on one side of the first trench. The selective removal is to retain the silicon dioxide film layer on the other side of the first trench, thereby forming gate insulating layers with different thicknesses. After the patterning process, the first trench and the second trench are subjected to a high-temperature thermal oxidation process again. The purpose of this step is to form the final gate insulating layer, further improving the insulation performance and breakdown voltage capability of the device by increasing the thickness of the insulating layer or improving its quality.

[0016] For claim 6, an ion implantation process is implemented in the epitaxial layer to form a well region and a source region. Ion implantation is a commonly used doping technique in semiconductor manufacturing. By implanting specific types of ions into the semiconductor material, its electrical properties are changed. During this process, the ions implanted into the well region and the source region have different conduction types. This different conduction type is to form different functional regions in the device, such as the well region and the source region, which play different roles in the operating principle of the device.

[0017] Furthermore, through the ion implantation process, precise control of the doping concentration and type can be achieved, thereby optimizing the performance of the device. By ensuring that the conduction type of the source region is the same as that of the epitaxial layer, an effective PN junction can be formed, improving the switching speed of the device, reducing the on-resistance, and enhancing the overall efficiency.

[0018] For claim 7, a manufacturing method of a trench MOS transistor power device includes the following steps: providing a silicon substrate with an epitaxial layer, forming at least one trench on the epitaxial layer, respectively forming a first gate insulating layer and a second gate insulating layer in the trench, performing patterning etching on the first and second gate insulating layers, further forming a third gate insulating layer in the trench, performing gate filling, respectively forming a well region and a source region on the front surface of the epitaxial layer through an ion implantation process, forming an isolation layer on the front surface of the epitaxial layer, and patterning to form a metal layer for the well region and the source region, and forming metal wirings to electrically connect the metal layers of the well region and the source region.

[0019] Preferably, for claim 8, the device adopts a vertical channel structure design, which is different from the traditional planar diffused MOS transistor. In the structure, the channel is perpendicular to the substrate surface, and its sidewalls are used as the gate. Due to the adoption of the vertical channel design, compared with the planar diffused MOS transistor, this structure significantly reduces the area occupied by the device, improves the integration of the device, and enables more devices to be accommodated in a limited space.

[0020] Furthermore, the vertical channel structure helps to effectively reduce the on-resistance and drive voltage of the device. The gate directly controls the vertical channel, thereby improving the control efficiency of the gate over the channel. The trench MOS transistor becomes the preferred structure for achieving ultra-low on-state drain-source resistance performance and is suitable for application scenarios with extremely high electrical performance requirements.

[0021] For claim 9, the device improves the breakdown voltage performance of the device by filling different thicknesses of gate insulating layer materials in the first trench and the second trench respectively, where the thickness of the gate insulating layer in the first trench is greater than that in the second trench, so as to enhance the breakdown voltage capacity of the peripheral position of the device, reduce leakage and lower power consumption. Increasing the thickness of the gate insulating layer in the first trench helps to reduce the power consumption of the device. The thicker insulating layer can more effectively prevent current leakage, thereby reducing power consumption.

[0022] Preferably, for claim 10, the device further includes one or more drain regions, which are located in the epitaxial layer and on the side physically far from the source region. The drain region is controlled by the gate material to achieve the functions of conduction and cutoff. This is part of the basic working principle of the MOS transistor, where the gate controls the current flow between the drain and the source.

[0023] Furthermore, the drain region and the source region are electrically connected through metal wiring to ensure the external electrical connection of the device. Metal wiring is used to achieve the complete circuit function of the device.

[0024] The above technical solutions can achieve the following beneficial effects: Compared with the prior art, the present invention has the following advantages and positive effects: (1) The present invention provides a novel trench MOS transistor power device. By adopting a unique trench structure design and optimizing the thickness of the gate insulating layer, it can significantly improve the breakdown voltage performance and electrical performance of the device, thereby achieving more efficient power conversion and lower power consumption; (2) The trench MOS transistor power device provided by the present invention effectively reduces the leakage phenomenon and power consumption by filling different thicknesses of gate insulating layer materials in the first trench and the second trench respectively, and improves the reliability and stability of the device; (3) The vertical channel structure design adopted in the present invention not only reduces the area occupied by the device, but also improves the integration degree of the device, making it possible to accommodate more devices in a limited space and being suitable for the application requirements of high-density integration.

[0025] (4) The well region and source region are formed by the ion implantation process adopted in the present invention. By precisely controlling the doping concentration and type, the performance of the device is optimized, the switching speed is increased, the on-resistance is reduced, thereby improving the overall efficiency.

[0026] (5) The present invention realizes the electrical connection between the drain region and the source region through metal wiring, ensuring the reliability of the external electrical connection of the device, making the trench MOS transistor power device more suitable for actual power electronics applications and meeting the requirements of modern power electronics equipment for high-performance power devices.

[0027] In summary, the trench MOS transistor power device and its manufacturing method of the present invention have advantages in improving the breakdown voltage performance, reducing leakage, lowering power consumption, optimizing electrical performance and enhancing reliability, and can meet the requirements of modern power electronics equipment for high-performance power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below.

[0029] Figure 1 It is a structural illustration of the trench MOS transistor power device provided by the present invention.

[0030] Figure 2 It is an illustration of the formation of trenches in the epitaxial layer of the trench MOS transistor provided by the present invention.

[0031] Figure 3 It is an illustration of two patterning etching steps of the gate insulating layer of the present invention.

[0032] Figure 4 It is an illustration of the steps of forming the third gate insulating layer and filling the gate of the present invention.

[0033] Figure 5 It is an illustration of the steps of forming the well region, source region by the ion implantation process and realizing electrical connection by forming metal wiring of the present invention.

[0034] Figure 6 It is a flow chart of the manufacturing method adopted by the present invention.

[0035] In the figure: (101) heavily doped n-type region in the substrate, (102) n-type epitaxial layer, (103) p-type diffusion region, (104) heavily doped n-type region, (105) gate oxide layer, (106) gate formed of polysilicon, (107) gate electrode, (108) metal wiring, (109) SiO2 or other insulating medium, (110) source, (201) first trench, (202) second trench. Detailed implementation manners

[0036] The present invention will be further explained and illustrated below with reference to the accompanying drawings and specific embodiments.

[0037] The implementation manner of the present invention relates to a trench-type MOS transistor power device and a preparation method thereof, aiming to significantly improve the breakdown voltage performance and electrical performance of the device through innovative trench design and optimization of the gate insulating layer thickness, while reducing leakage and power consumption.

[0038] The following are the detailed implementation manners of the present invention. As Figure 1 shown, the trench-type MOS transistor power device of the present invention includes: a substrate (101), which is a heavily doped n-type region and provides the basic structure of the device; an epitaxial layer (102), located on the substrate and used to form the active region of the device; a first trench (201) and a second trench (202), distributed on the epitaxial layer, wherein the first trench is mainly located at the peripheral position of the chip, and the second trench is located inside the first trench; a gate insulating layer, filled in the first trench and the second trench, and physical isolation is achieved through the gate insulating layer; a gate material, filled in the first trench and the second trench, and used to control the on and off of the channel; a gate electrode (107), electrically connected to the gate material and used to apply a control signal; a source (110), located on one side of the epitaxial layer and opposite to the gate material; a drain region, located on the side of the epitaxial layer far from the source region, and the on and off are controlled through the gate material; a metal wiring (108), used to electrically connect the source and the drain region to achieve the external electrical connection of the device.

[0039] Figure 2 provides a visual illustration of the key trench formation process for the trench-type MOS transistor power device of the present invention. Through the design and formation of the trench, the device can improve the breakdown voltage performance, reduce leakage, lower power consumption, and optimize the electrical performance while maintaining a small device size. Combined with Figure 2The following is an explanation. In the figure, the substrate (101) and the epitaxial layer (102) constitute the basic structure of the trench MOS transistor. The epitaxial layer (102) is located on the substrate (101) and is used to form the active region of the device. At least two trenches are formed on the epitaxial layer (102), namely the first trench (201) and the second trench (202). The first trench (201) is mainly distributed around the periphery of the chip, while the second trench (202) is located inside the first trench (201), which helps to improve the breakdown voltage performance of the device, reduce leakage current, and lower power consumption.

[0040] Furthermore, Figure 2 shows the process of filling the gate insulating layer in the trenches. The first trench (201) and the second trench (202) are filled with the gate insulating layer and the gate material respectively. The gate insulating layer is composed of silicon dioxide (SiO2) material. The gate insulating layer of the first trench (201) is composed of a combination of a silicon dioxide layer formed by high-temperature thermal oxidation and a silicon dioxide layer formed by the PECVD method, while the gate insulating layer of the second trench is only composed of a silicon dioxide layer formed by high-temperature thermal oxidation.

[0041] As Figure 3 shows the patterned etching of the gate insulating layer in the trench MOS transistor power device of the present invention. The steps involve using wet or dry etching techniques to precisely remove the silicon dioxide layer on one side of the second trench (202) and the first trench (201) to retain the silicon dioxide film layer on the other side of the first trench (201). Gate insulating layers with different thicknesses are formed to optimize the breakdown voltage performance of the device and reduce leakage current.

[0042] Furthermore, wet etching can provide better selectivity and anisotropy, which helps to precisely control the etching shape and depth. Dry etching includes plasma etching, which can provide better control accuracy and repeatability and is suitable for the processing of fine patterns. First, the epitaxial layer is pretreated to ensure the uniformity of the etching process. A layer of photoresist is coated on top of the trench, and the required patterned mask is formed through the photolithography process. The mask will serve as a protective layer during the etching process to ensure that only the exposed areas are etched. Using wet or dry etching techniques, the exposed silicon dioxide layer is selectively etched. During this process, the silicon dioxide layer on one side of the second trench (202) and the first trench (201) is precisely removed, while the silicon dioxide film layer on the other side of the first trench (201) is retained.

[0043] Furthermore, as Figure 4As shown, the process of forming the third gate insulating layer and filling the gate (106) in the trench-type MOS transistor power device. This step is carried out after patterning etching, aiming to form an additional insulating layer in the trench to enhance the insulation performance and breakdown voltage capability of the device. Gate filling (106) involves filling the gate material into the trench to form a gate structure for controlling the on and off states of the channel.

[0044] Furthermore, in the preparation of the trench-type MOS transistor power device, the present invention can precisely control the formation of the gate insulating layer and gate filling to optimize the device performance. Through the precise control of the process steps, not only the electrical performance of the device is improved, but also its stability and reliability under high voltage and high current conditions are enhanced.

[0045] As Figure 5 shown, the process of forming the well region and source region respectively by ion implantation in the epitaxial layer (102) is demonstrated. The ions implanted into the well region and source region have different conduction types, and the conduction type of the source region is consistent with that of the epitaxial layer, forming an effective PN junction to improve the switching performance of the device. The process of forming the source metal wiring (108) and gate electrode (107) on the front surface of the substrate, and forming the metal wiring (108) to electrically connect the metal layers of the well region and source region is crucial for realizing the external electrical connection of the device, ensuring that the device can be integrated into a larger circuit system.

[0046] Furthermore, as Figure 5 shown, a vertical channel structure is adopted, where the sidewalls of the channel form the gate (106), reducing the area occupied by the device, and effectively reducing the on-resistance and drive voltage, thereby optimizing the electrical performance of the device. It can improve the breakdown voltage performance, reduce leakage, and lower power consumption while maintaining a small device size.

[0047] As Figure 6 shown, a method for fabricating a trench-type MOS transistor power device. The method for fabricating the trench-type MOS transistor power device of the present invention includes the following steps: providing a silicon substrate with an epitaxial layer; forming at least one trench on the epitaxial layer, including a first trench (201) and a second trench (202); forming a first gate insulating layer and a second gate insulating layer in the trenches respectively; performing patterning etching on the first and second gate insulating layers; further forming a third gate insulating layer in the trenches and performing gate filling; forming a well region and a source region respectively on the front surface of the epitaxial layer by ion implantation; forming an isolation layer on the front surface of the epitaxial layer and patterning to form the metal layers of the well region and source region; forming metal wiring to electrically connect the metal layers of the well region and source region.

[0048] Through the above embodiments, the trench MOS transistor power device of the present invention and its manufacturing method can achieve more efficient power conversion and lower power consumption, while improving the reliability and stability of the device, meeting the requirements of modern power electronic devices for high-performance power devices.

[0049] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. The present invention provides a trench MOS transistor power device and a manufacturing method thereof. The MOS transistor power device includes a substrate, an epitaxial layer, a first trench, a second trench, a gate insulating layer, and a gate insulating layer. The MOS transistor divides the trench of the MOS transistor into two parts on the silicon substrate with an epitaxial layer, forming a first trench and a second trench. The first trench is mainly distributed at the peripheral position of the chip, and the second trench is distributed inside the first trench. The first trench and the second trench are respectively filled with gate material and gate insulating layer material, and physical isolation is achieved through the gate insulating layer. Among them, the gate insulating layer of the first trench far from the inner side of the second trench is thicker than that closer to the inner side of the second trench.

2. The trench MOS transistor power device and its manufacturing method according to claim 1, characterized in that, The first trench and the second trench are formed on the epitaxial layer through semiconductor processes. The gate insulating layer and the gate material are respectively filled in the first trench and the second trench. Well regions and source regions are respectively formed in the epitaxial layer through ion implantation processes. Source region metal and gate metal are formed on the front surface of the substrate, wherein the gate metal is electrically connected to the gate material.

3. A trench MOS transistor power device and a manufacturing method thereof as claimed in claim 1, wherein, The widths of the first trench and the second trench are the same, and the depths and vertical angles of the trenches are also the same. The first trench is located at the edge of the chip, forming two continuous trench structures; the second trench is located in the central region of the chip and is composed of multiple side-by-side trenches.

4. The MOS transistor power device according to claim 1, characterized in that, The gate insulating layer for filling the first trench and the second trench is composed of silicon dioxide (SiO2) material. The gate insulating layer of the first trench is composed of a combination of a silicon dioxide layer formed by high-temperature thermal oxidation and a silicon dioxide layer formed by plasma-enhanced chemical vapor deposition (PECVD) method. The gate insulating layer of the second trench is only composed of a silicon dioxide layer formed by high-temperature thermal oxidation, and its thickness is the same as that of the high-temperature thermal oxidation layer in the first trench and the formation conditions are the same.

5. The MOS transistor power device according to claim 4, characterized in that, Both the first trench and the second trench are first filled with a layer of silicon dioxide layer formed by high-temperature thermal oxidation and a layer of silicon dioxide layer formed by PECVD method. Subsequently, through a patterning process, wet or dry etching technology is used to remove the silicon dioxide layer in the second trench and on one side of the first trench to retain the silicon dioxide film layer on the other side of the first trench. Finally, the first trench and the second trench are subjected to a high-temperature thermal oxidation treatment again to form the final gate insulating layer.

6. The manufacturing method of the trench MOS transistor power device according to claim 2, wherein, Including the following steps: Implement an ion implantation process in the epitaxial layer to form well regions and source regions. During this process, the ions implanted into the well regions and the source regions have different conduction types, and the conduction type of the source region is the same as that of the epitaxial layer.

7. A manufacturing method of a trench MOS transistor power device, characterized in that, Including the following steps: providing a silicon substrate with an epitaxial layer, forming at least one trench on the epitaxial layer, respectively forming a first gate insulating layer and a second gate insulating layer in the trench, performing patterning etching on the first and second gate insulating layers, further forming a third gate insulating layer in the trench, performing gate filling, respectively forming well regions and source regions in the epitaxial layer through ion implantation processes on the front surface of the epitaxial layer, forming an isolation layer on the front surface of the epitaxial layer, and patterning to form the metal layers of the well regions and the source regions, and forming metal wirings to electrically connect the metal layers of the well regions and the source regions.

8. A trench MOS transistor power device and a manufacturing method thereof, characterized in that, This device utilizes a vertical channel structure, where the sidewalls of the channel form the gate. Compared with planar diffused MOS transistors, this structure can reduce the area occupied by the device and effectively lower the on-resistance and drive voltage, thereby optimizing the electrical performance of the device and making the trench MOS transistor the preferred structure for achieving ultra-low on-state drain-source resistance performance.

9. The trench MOS transistor power device according to claim 1, characterized in that This device improves the breakdown voltage performance of the device by filling gate insulating layer materials with different thicknesses in the first trench and the second trench respectively, where the thickness of the gate insulating layer in the first trench is greater than that in the second trench, to enhance the breakdown voltage capacity at the peripheral position of the device, reduce leakage current and lower power consumption.

10. The trench MOS transistor power device according to any one of claims 1 to 9, characterized in that, This device further includes one or more drain regions located on the side of the epitaxial layer away from the source region; the conduction and cutoff of the drain region are controlled by the gate material; the layout design of the drain region and the source region optimizes the current flow path of the device to reduce the on-resistance of the device and improve the overall performance of the device; the drain region and the source region are electrically connected through metal wiring to achieve the external electrical connection of the device.

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