LED chip and manufacturing method thereof
By using a layered N-type layer in the LED chip and using Al atom substitution to bending the dislocation, the problem of insufficient antistatic ability of GaN-based LED chips is solved, and the antistatic ability and reliability are improved.
Patent Information
- Application Number
- CN202510531461.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-07-18
AI Technical Summary
How to improve the antistatic ability of GaN-based LED chips to improve product prices and yields and increase economic benefits.
During the production process of LED chips, an N-type layer with a laminate structure is used, including an N-type doped GaN layer, an undoped AlGaN layer and an undoped AlGaN layer, and a superlattice layer composed of an N-type doped GaN layer, which uses lattice mismatch caused by Al atom substitution to bending the dislocation, thereby reducing or annihilated defects and improving the growth quality of the N-type layer.
By optimizing the crystal quality of the epitaxial layer, the antistatic ability and reliability of the LED chip are improved, the life span is extended, and the stability is enhanced.
Smart Images
Figure CN120344054A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to an LED chip and a manufacturing method thereof. Background Art
[0002] As a kind of high-efficiency, safe, environmentally friendly, and green new solid-state lighting source, the light-emitting diode (LED chip) based on GaN material has the advantages of safety, reliability, long life, and low energy consumption, and is being rapidly and widely applied to fields such as urban landscape lighting, traffic signal lights, mobile phone backlights, outdoor displays, automotive headlights, tunnel lights, and plant lighting. Therefore, the improvement of all aspects of the performance of LED chips has been the focus of attention in the industry. Among them, the anti-static ability is an important parameter of LED chip products. With strong anti-static ability, the product has a high price, a high yield rate, and significant economic benefits. Therefore, how to improve the anti-static ability of LED chips has become a research hotspot for those skilled in the art. Summary of the Invention
[0003] In view of the above problems, this application provides an LED chip and a manufacturing method thereof to achieve the purpose of improving the anti-static ability of the LED chip. The specific solutions are as follows:
[0004] A manufacturing method of an LED chip includes:
[0005] Forming an N-type layer on one side of a substrate, where the N-type layer includes a stacked first component layer, second component layer, and third component layer. Among them, the first component layer is an N-type doped GaN layer, the second component layer is an undoped AlGaN layer, and the third component layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer;
[0006] Forming a quantum well active layer on the side of the N-type layer away from the substrate;
[0007] Forming a P-type layer on the side of the quantum well active layer away from the N-type layer.
[0008] Optionally, forming an N-type layer on one side of a substrate, where the N-type layer includes a stacked first component layer, second component layer, and third component layer, including:
[0009] Forming a first component layer on one side of the substrate;
[0010] Forming a second component layer on the side of the first component layer away from the substrate;
[0011] Forming a third component layer on the side of the second component layer away from the first component layer;
[0012] Among them, the gallium source during the growth of the first composition layer is TEGa. Forming the first composition layer on one side of the substrate includes: using TEGa as the Ga source to grow an N-type doped GaN layer on one side of the substrate.
[0013] Optionally, the growth temperature of the first composition layer ranges from 1100 °C to 1200 °C, including the endpoint values; the thickness of the first composition layer ranges from 200 nm to 400 nm, including the endpoint values; the thickness of the second composition layer ranges from 50 nm to 800 nm, including the endpoint values; the growth temperature of the second composition layer ranges from 950 °C to 1050 °C, including the endpoint values.
[0014] Optionally, forming the second composition layer on the side of the first composition layer away from the substrate includes:
[0015] Using TMGa as the Ga source to form a grown AlxGa1-xN layer on the side of the first composition layer away from the substrate; wherein, the value range of x is from 0% to 50%, including the right endpoint value and not including the left endpoint value.
[0016] Optionally, forming the third composition layer on the side of the second composition layer away from the first composition layer includes:
[0017] Using TMGa as the Ga source to grow a K-group superlattice layer on the side of the second composition layer away from the first composition layer. Each group of superlattice layers includes periodically spaced grown undoped Al y Ga 1-y N layer and N-type doped GaN layer, and K is a positive integer.
[0018] Optionally, K is 2. In the first group of superlattice layers, the number of periods of the undoped Al y Ga 1-y N layer and N-type doped GaN layer ranges from 30 to 50, including the endpoint values; in the first group of superlattice layers, the thickness ratio of the undoped Al y Ga 1-y N layer and N-type doped GaN layer is 7.5 / 10;
[0019] In the second group of superlattice layers, the number of periods of the undoped Al y Ga 1-y N layer and N-type doped GaN layer ranges from 15 to 25, including the endpoint values; in the second group of superlattice layers, the thickness ratio of the undoped Al y Ga 1-y N layer and N-type doped GaN layer is 5 / 10;
[0020] The value of y in the second group of superlattice layers is less than the value of y in the first group of superlattice layers.
[0021] Optionally, the value range of y in the first group of superlattice layers is 10% to 30%, including the endpoint values; the value range of y in the second group of superlattice layers is 0% to 20%, including the right endpoint value and excluding the left endpoint value.
[0022] Optionally, forming a third composition layer on the side of the second composition layer away from the first composition layer further includes:
[0023] Growing a stress release layer between the first group of superlattice layers and the second group of superlattice layers.
[0024] An LED chip includes:
[0025] A substrate;
[0026] An N-type layer on one side of the substrate, the N-type layer includes a stacked first composition layer, a second composition layer and a third composition layer, wherein the first composition layer is an N-type doped GaN layer, the second composition layer is an undoped AlGaN layer, and the third composition layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer;
[0027] A quantum well active layer on the side of the N-type layer away from the substrate;
[0028] A P-type layer on the side of the quantum well active layer away from the N-type layer.
[0029] Optionally, the gallium source during the growth of the first composition layer is TEGa, the growth temperature value range of the first composition layer is 1100°C to 1200°C, including the endpoint values; the growth temperature value range of the GaN layer in the third composition layer is 1000°C to 1100°C, including the endpoint values.
[0030] Optionally, the second composition layer is an undoped AlxGa1-xN layer, the thickness value range is 50 nm - 800 nm, including the endpoint values, the growth temperature value range is 950 - 1050°C, including the endpoint values, the value range of x is 0% to 50%, including the right endpoint value and excluding the left endpoint value, and the gallium source during the growth of the second composition layer is TMGa;
[0031] The third composition layer includes at least two groups of superlattice layers, and each group of superlattice layers is composed of periodically arranged undoped Al y Ga 1-y N layer and N-type doped GaN layer; wherein,
[0032] The number of periods of the undoped AlGaN layer and the N-type doped GaN layer in the first group of superlattice layers is in the range of 30 - 50, including the endpoint values, and the undoped Al y Ga1-y The thickness ratio of the N-layer and the N-type doped GaN layer is 7.5 / 10;
[0033] In the second group of superlattice layers, undoped Al y Ga 1-y The number of periods of the N-layer and the N-type doped GaN layer ranges from 15 to 25, including the end values. The undoped Al y Ga 1-y The thickness ratio of the N-layer and the N-type doped GaN layer is 5 / 10;
[0034] In the second group of superlattice layers, the value of y is less than the value of y in the first group of superlattice layers.
[0035] Optionally, the value range of y in the first group of superlattice layers is 10% to 30%, including the end values. The value range of y in the second group of superlattice layers is 0% to 20%, including the right end value but not including the left end value.
[0036] Optionally, it further includes: a stress relief layer located between the first group of superlattice layers and the second group of superlattice layers.
[0037] In the method for manufacturing an LED chip provided by the embodiments of the present application, the N-type layer includes a stacked first component layer, a second component layer, and a third component layer. Among them, the first component layer is an N-type doped GaN layer, the second component layer is an undoped AlGaN layer, and the third component layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer. Thus, in the second component layer, the lattice mismatch caused by the substitution of Al atoms can cause dislocations to bend, so that the defects in the N-type layer are reduced or annihilated at this interface, thereby achieving the effect of shielding dislocations, further improving the growth quality of the N-type layer, improving the antistatic ability of the N-type layer, and ultimately improving the antistatic ability and reliability of the LED chip. Description of the Drawings
[0038] Combined with the drawings and referring to the following specific embodiments, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more obvious. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.
[0039] Figure 1 It is a flowchart of a method for manufacturing an LED chip provided by the present application;
[0040] Figure 2 It is a schematic structural diagram of an LED chip provided by the present application. Detailed Embodiments
[0041] The embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.
[0042] Without departing from the spirit or scope of the present application, various modifications and variations can be made in the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.
[0043] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0044] As described in the background art section, how to improve the electrostatic resistance of LED chips has become a research hotspot for those skilled in the art.
[0045] The inventor's research found that the improvement of the electrostatic resistance of LED chips is related to the optimization of the crystal quality of the epitaxial layer. Specifically, when the crystal quality of the epitaxial layer is improved, the performance of the LED chip can be improved, and the lifespan, anti-aging ability, electrostatic resistance, and stability of the LED chip will be improved with the improvement of the crystal quality of the epitaxial layer.
[0046] In view of this, the embodiments of the present application provide a method for manufacturing an LED chip. It should be noted that in the embodiments of the present application, the manufacturing of the LED chip mainly uses the metal organic chemical vapor deposition (MOCVD, Metal-organic Chemical Vapor Deposition) process, but the present application does not limit this. In other embodiments of the present application, the manufacturing of the LED chip can also use other processes, depending on the specific situation.
[0047] The following describes the method for manufacturing an LED chip provided in the embodiments of the present application by taking the MOCVD process as an example of the manufacturing process of the LED chip.
[0048] Optionally, in the process of manufacturing the LED chip provided in the embodiments of the present application, trimethylgallium (TMGa) or triethylgallium (TEGa) is used as the Ga source, ammonia (NH3) is used as the N source, trimethylindium (TMIn) is used as the In source, trimethylaluminum (TMAl) is used as the Al source, H2 and N2 are used as carrier gases, the N-type and P-type doping sources are silane (SiH4) and bis(cyclopentadienyl)magnesium (CP2Mg) respectively, and a graphite disk is used as the substrate carrier disk.
[0049] Specifically, as Figure 1 shown, the manufacturing method of the LED chip provided in the embodiments of the present application includes:
[0050] S1: Form an N-type layer on one side of the substrate. The N-type layer includes a stacked first composition layer, second composition layer, and third composition layer. Among them, the first composition layer is an N-type doped GaN layer, the second composition layer is an undoped AlGaN layer, and the third composition layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer.
[0051] Optionally, in an embodiment of the present application, before forming the N-type layer on one side of the substrate, it further includes: sequentially forming a buffer layer, a three-dimensional nucleation layer, and a two-dimensional coalescence layer on the substrate along a first direction, and the first direction is perpendicular to the plane where the substrate is located. The substrate includes, but is not limited to, a sapphire substrate.
[0052] Optionally, in an embodiment of the present application, sequentially forming a buffer layer, a three-dimensional nucleation layer, and a two-dimensional coalescence layer on the substrate along the first direction includes:
[0053] Form a buffer layer on one side of the substrate. Optionally, the buffer layer is an AlN buffer layer;
[0054] Form a three-dimensional nucleation layer on the side of the buffer layer away from the substrate;
[0055] Form a two-dimensional coalescence layer on the side of the three-dimensional nucleation layer away from the buffer layer.
[0056] Specifically, in an embodiment of the present application, forming a buffer layer on one side of the substrate includes: introducing a first process gas into the deposition chamber within a temperature range of 900°C to 1150°C, including the end point values. The first process gas includes TMAl, SiH4, NH3, H2, and N2, and grow an AlN buffer layer on one side of the substrate. Optionally, in an embodiment of the present application, the thickness of the buffer layer ranges from 5 nm to 50 nm, including the end point values, and the molar ratio of Si to Al in the first process gas ranges from 0.05 to 0.5, including the end point values, but the present application does not limit this, and it depends on the specific situation.
[0057] Based on any of the above embodiments, in an embodiment of the present application, forming a three-dimensional nucleation layer on the side of the buffer layer away from the substrate includes:
[0058] Introduce a second process gas into the deposition chamber. The second process gas includes NH3, H2, and N2. In the temperature range of 800°C to 1000°C, including the endpoint values, using the lattice mismatch between GaN and AlN as the driving force, form a three-dimensional nucleation layer on the side of the buffer layer away from the substrate. Among them, the proportion range of the NH3 component in the second process gas is 30% to 80%, including the endpoint values. Thus, using the lattice mismatch between GaN and AlN as the driving force, in a small ammonia atmosphere, realize three-dimensional island growth mode by deposition decomposition to form a three-dimensional nucleation layer.
[0059] Optionally, in an embodiment of the present application, the introduction time of the second process gas ranges from 0.5 min to 3 min, including the endpoint values, that is, the formation time of the three-dimensional nucleation layer ranges from 0.5 min to 3 min, including the endpoint values; the thickness of the three-dimensional nucleation layer ranges from 1800 nm to 2200 nm, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0060] Based on any of the above embodiments, in an embodiment of the present application, forming a two-dimensional merging layer on the side of the three-dimensional nucleation layer away from the buffer layer includes:
[0061] Introduce a third process gas into the deposition chamber. The third process gas includes NH3, H2, and N2. In the temperature range of 900°C to 1200°C, including the endpoint values, use diffusion to realize the lateral growth mode, and merge the three-dimensional islands into a GaN plane to form a two-dimensional merging layer on the side of the three-dimensional nucleation layer away from the buffer layer; among them, the proportion range of the NH3 component in the third process gas is 70% to 100%, including the endpoint values. Thus, in a high-temperature and high-ammonia atmosphere, use diffusion to realize the lateral growth mode, and merge the three-dimensional islands into a GaN plane to reduce the dislocation density. It should be noted that in this embodiment, the two-dimensional merging layer is an unintentionally doped layer, that is, the third process gas does not include SiH4, that is, during the formation of the two-dimensional merging layer, SiH4 is not introduced into the deposition chamber.
[0062] Optionally, in an embodiment of the present application, the introduction time of the third process gas ranges from 0.5 min to 3 min, including the endpoint values, and the thickness of the two-dimensional merging layer ranges from 1300 nm to 1700 nm, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0063] Based on any of the above embodiments, in an embodiment of the present application, before forming a buffer layer on one side of the substrate, the method further includes: performing hydrogenation treatment on the substrate to remove impurities, scratches, particles, etc. on the substrate surface. Optionally, the time for performing hydrogenation treatment on the substrate is 5 min, and the temperature range for performing hydrogenation treatment on the substrate is 900°C to 1150°C, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0064] Based on any of the above embodiments, in an embodiment of the present application, an N-type layer is formed on one side of the substrate, and the N-type layer includes a stacked first composition layer, a second composition layer, and a third composition layer, including:
[0065] Form a first composition layer on one side of the substrate;
[0066] Form a second composition layer on the side of the first composition layer away from the substrate;
[0067] Form a third composition layer on the side of the second composition layer away from the first composition layer;
[0068] In the above embodiment, in an embodiment of the present application, forming a second composition layer on the side of the first composition layer away from the substrate includes:
[0069] Grow an Al x Ga 1-x N layer on the side of the first composition layer away from the substrate; where the value range of x is 0% to 50%, including the right endpoint value and not including the left endpoint value, so as to utilize the lattice mismatch caused by the substitution effect of Al atoms to cause dislocations to bend, thereby reducing or annihilating defects at this interface, achieving the effect of shielding dislocations, improving the quality of the second composition layer, ultimately improving the quality of the N-type layer, and improving the antistatic ability and reliability of the LED chip.
[0070] Optionally, in an embodiment of the present application, the thickness value range of the second composition layer is 50 nm to 800 nm, including the endpoint values, and the growth temperature value range of the second composition layer is 950°C to 1050°C, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0071] Specifically, in an embodiment of the present application, forming a second composition layer on the side of the first composition layer away from the substrate includes: using TMGa as the Ga source, and NH3, H2, and N2 as the N source and carrier gas respectively, and growing an Al x Ga 1-x N layer on the side of the first composition layer away from the substrate. It should be noted that in this embodiment, the Al x Ga 1-xThe N layer is an unintentionally doped layer, and SiH4 is not introduced during its growth process, that is, the Al x Ga 1-x in the N layer is not doped with Si.
[0072] It can be seen that in the method for manufacturing an LED chip provided by the embodiment of the present application, the N-type layer includes a stacked first component layer, a second component layer, and a third component layer. Among them, the first component layer is an N-type doped GaN layer, the second component layer is an undoped AlGaN layer, and the third component layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer. Thus, in the second component layer, the lattice mismatch caused by the substitution of Al atoms can cause dislocations to bend, so that the defects in the N-type layer are reduced or annihilated at this interface, thereby achieving the effect of shielding dislocations, further improving the growth quality of the N-type layer, improving the antistatic ability of the N-type layer, and ultimately improving the antistatic ability and reliability of the LED chip.
[0073] It should be noted that in the mass production preparation process of the epitaxial layer of traditional GaN-based LED chips, in order to obtain a high V / III ratio, high growth rate, and low cost, TMGa is usually used as the Ga source when growing the N-type layer in the epitaxial layer of the LED chip. However, TMGa is prone to introducing defects such as carbon impurities during high-temperature decomposition, resulting in a decrease in the crystal quality of the epitaxial layer and the formation of leakage channels, thus affecting the antistatic performance of the N-type layer and further affecting the antistatic performance of the LED chip.
[0074] The inventors have found through research that the β-hydride of TEGa has a lower activation energy than TMGa and is more likely to undergo an elimination reaction. Among them, the β-hydride elimination reaction is specifically as follows: a hydrogen atom at the β position in the ethyl group transfers to Ga, thereby decomposing a molecule containing a metal-hydrogen bond and a stable olefin containing a double bond. It should be noted that the β-hydride elimination reaction of TEGa occurs both in the gas phase and on the GaN surface, which is beneficial to reducing carbon pollution caused by insufficient decomposition of the MO source.
[0075] Therefore, in an optional embodiment of the present application, the gallium source during the growth process of the first component layer is TEGa. Forming the first component layer on one side of the substrate includes: using TEGa as the Ga source and growing an N-type doped GaN layer on one side of the substrate.
[0076] In the method for manufacturing an LED chip provided by an embodiment of the present application, during the growth process of the first composition layer, TEGa is selected as the Ga source instead of TMGa as the Ga source, which is beneficial to improving the surface flatness and cleanliness, reducing the formation of defects during the growth process, thereby being beneficial to reducing the introduction of carbon impurities to provide higher material quality, improving the growth quality of the first composition layer, further improving the growth quality of the N-type layer, improving the antistatic ability of the N-type layer, and ultimately improving the antistatic ability and reliability of the LED chip.
[0077] Optionally, in an embodiment of the present application, the growth temperature of the first composition layer ranges from 1100°C to 1200°C, including the endpoint values, to increase the cracking rate of TEGa, but the present application does not limit this, and it depends on the specific situation.
[0078] Specifically, in an embodiment of the present application, forming the first composition layer on one side of the substrate includes: using TEGa as the Ga source, SiH4, NH3, H2, and N2 as the Si doping source, N source, and carrier gas respectively, and growing an N-type doped GaN layer within the temperature range of 1100°C to 1200°C, including the endpoint values. Optionally, the concentration of SiH4 is 2E18 / cm 3 , but the present application does not limit this, and it depends on the specific situation.
[0079] Optionally, in an embodiment of the present application, the thickness of the first composition layer ranges from 200 nm to 400 nm, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0080] Based on any of the above embodiments, in an embodiment of the present application, forming the third composition layer on the side of the second composition layer away from the first composition layer includes: using TMGa as the Ga source and growing a K-group superlattice layer on the side of the second composition layer away from the first composition layer. Each group of superlattice layers includes periodically and alternately grown undoped Al y Ga 1-y N layer and N-type doped GaN layer, where K is a positive integer.
[0081] It should be noted that in the alternating stacked structure of the undoped Al y Ga 1-y N layer and the N-type doped GaN layer in the third composition layer, the improvement in the electron mobility of the undoped single layer (i.e., the undoped Al y Ga 1-y N layer) is higher than the decrease in the effective average electron concentration within a single period after the electron concentration diffusion of the N-type doped single layer (i.e., the N-type doped GaN layer), so that the third composition layer has higher conductivity, and further the N-type layer has higher conductivity.
[0082] Moreover, the modulation doping of the undoped single layer and the N-type doped single layer can cause the stress state in the third component layer to change periodically, providing stress buffering for the subsequent growth of the quantum well active layer.
[0083] In addition, an superlattice layer structure composed of alternately grown undoped Al y Ga 1-y N layers and N-type doped GaN layers is adopted in the third component layer, which can further bend and close the dislocations in the N-type layer, reduce the number of threading dislocations, improve the crystal quality, and thus improve the antistatic ability and reliability of the LED chip.
[0084] Specifically, in an embodiment of the present application, forming a third component layer on the side of the second component layer away from the first component layer includes: using TMGa as the Ga source, and SiH4, NH3, H2, and N2 as the Si doping source, N source, and carrier gas respectively, and periodically and alternately growing two sets of superlattice layers composed of undoped Al y Ga 1-y N layers and GaN layers on the side of the second component layer away from the first component layer. It should be noted that in this embodiment, in the first set of superlattice layers, the Al y Ga 1-y N layer is not doped with Si, and the GaN layer is doped with Si; in the second set of superlattice layers, the Al y Ga 1-y N layer is not doped with Si, and the GaN layer is doped with Si. Optionally, in an embodiment of the present application, the doping concentration of the GaN layer in the first superlattice layer is 4E18 / cm 3 , and the doping concentration of the GaN layer in the second superlattice layer is 8E18 / cm 3 , but the present application does not limit this, and it depends on the specific situation.
[0085] Optionally, in an embodiment of the present application, K = 2. In the first set of superlattice layers, the number of periods of the undoped Al y Ga 1-y N layer and the N-type doped GaN layer ranges from 30 to 50, including the end values, and the thickness ratio of the undoped Al y Ga 1-y N layer and the N-type doped GaN layer is 7.5 / 10; in the second set of superlattice layers, the number of periods of the undoped Al y Ga 1-y N layer and the N-type doped GaN layer ranges from 15 to 25, including the end values, and the thickness ratio of the undoped Al y Ga 1-yThe thickness ratio of the N-layer to the N-type doped GaN layer is 5 / 10; wherein, the value of y in the second group of superlattice layers is less than the value of y in the first group of superlattice layers. Specifically, in an embodiment of the present application, the value range of y in the first group of superlattice layers is 10% to 30%, including the endpoint values, and the value range of y in the second group of superlattice layers is 0% to 20%, including the right endpoint value and excluding the left endpoint value, but the present application does not make any limitation on this, and it depends on the specific situation.
[0086] Based on any of the above embodiments, in an embodiment of the present application, the method further includes: growing a stress release layer between the first group of superlattice layers and the second group of superlattice layers to reduce the stress generated during the growth of the third component layer.
[0087] Optionally, in an embodiment of the present application, the stress release layer is a GaN layer, and the thickness value range is 30 nm - 80 nm, including the endpoint values, but the present application does not make any limitation on this, and it depends on the specific situation.
[0088] Optionally, in an embodiment of the present application, the growth temperature value range of the third component layer is 1000 °C to 1100 °C, including the endpoint values, but the present application does not make any limitation on this, and it depends on the specific situation.
[0089] S2: Form a quantum well active layer on the side of the N-type layer away from the substrate.
[0090] Optionally, in an embodiment of the present application, before forming the quantum well active layer on the side of the N-type layer away from the substrate, the method further includes: forming a stress buffer layer on the side of the N-type layer away from the substrate. Specifically, in an embodiment of the present application, forming a stress buffer layer on the side of the N-type layer away from the substrate includes: introducing TEGa, TMIn, NH3, H2, N2, and growing a superlattice layer composed of an InGaN layer and a GaN layer, wherein the number of periods of the InGaN layer and the GaN layer has a value range of 5 to 10, including the endpoint values, the total thickness value range of the superlattice layer composed of the InGaN layer and the GaN layer is 60 nm to 120 nm, including the endpoint values, the growth temperature value range of the InGaN layer is 700 °C to 850 °C, including the endpoint values, and the growth temperature value range of the GaN layer is 800 °C to 1000 °C, including the endpoint values, but the present application does not make any limitation on this, and it depends on the specific situation.
[0091] Specifically, in an embodiment of the present application, the thickness of the InGaN layer in the stress buffer layer is 10 nm, and the thickness of the GaN layer is 2 nm, but the present application does not make any limitation on this, and it depends on the specific situation.
[0092] Optionally, in an embodiment of the present application, the LED chip has a V-pit. In this embodiment, before forming the stress buffer layer on the side of the N-type layer away from the substrate, the method further includes: forming a low-temperature gallium nitride layer on the side of the N-type layer away from the substrate. The specific method includes: introducing TMGa, NH3, and N2, and growing a low-temperature gallium nitride layer with a thickness of 150 nm to 250 nm, including the end values, within the temperature range of 600 °C to 800 °C, including the end values, to convert the dislocation density to form a V-pit. Wherein, the V-pit penetrates through the quantum well active layer and the stress buffer layer and extends into the low-temperature gallium nitride layer.
[0093] Based on any of the above embodiments, in an embodiment of the present application, forming a quantum well active layer on the side of the N-type layer away from the substrate includes: alternately growing a quantum well layer and a quantum barrier layer on the side of the N-type layer away from the substrate. Optionally, during the growth of the quantum well layer, the process gases include TEGa, TMIn, and NH3, and the growth temperature ranges from 700 °C to 850 °C, including the end values; during the growth of the quantum barrier layer, the process gases include TEGa, TMIn, SiH4, NH3, H2, and N2, and the growth temperature ranges from 800 °C to 1000 °C, including the end values, but the present application does not limit this, and it depends on the specific situation.
[0094] Optionally, in an embodiment of the present application, the total thickness of the quantum well active layer ranges from 10 nm to 16 nm, including the end values, the number of periods of the quantum well and the quantum barrier ranges from 8 to 12, including the end values, the thickness of the quantum well is 3 nm, and the thickness of the quantum barrier is 11 nm, but the present application does not limit this, and it depends on the specific situation.
[0095] S3: Form a P-type layer on the side of the quantum well active layer away from the N-type layer.
[0096] Optionally, in an embodiment of the present application, the P-type layer includes a stacked P-type doped Al x Ga 1-x N layer and a P-type doped GaN layer. In this embodiment, forming a P-type layer on the side of the quantum well active layer away from the N-type layer includes:
[0097] First, introduce TMAl, TMGa, CP2Mg, NH3, and H2, and grow a P-type doped Al x Ga 1-x N layer under an N2 atmosphere at a growth pressure of 100 torr within the temperature range of 850 °C to 1050 °C, including the end values;
[0098] Then, TMGa, CP2Mg, NH3, H2, and N2 are introduced, and a P-type doped GaN layer is grown within the temperature range of 800°C to 1200°C, including the endpoint values.
[0099] Optionally, in an embodiment of the present application, P-type doped Al x Ga 1-x The thickness of the N layer ranges from 150 nm to 250 nm, including the endpoint values; during the growth process of the P-type doped Al x Ga 1-x The growth rate of the N layer is 20 Å / s, the doping concentration of Mg is 5E19 / cm 3 , and the value range of the Al component x is from 0% to 50%, including the right endpoint value and excluding the left endpoint value, but the present application does not limit this, and it depends on the specific situation.
[0100] Optionally, in an embodiment of the present application, the thickness of the P-type doped GaN layer ranges from 200 nm to 600 nm, including the endpoint values, and the concentration value range of Mg during the growth process of the P-type doped GaN layer is 1E19 / cm 3 ~4E20 / cm 3 , including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0101] Based on any of the above embodiments, the method further includes: S5: Cooling and annealing the formed LED chip to end the growth of the LED chip.
[0102] Optionally, in an embodiment of the present application, the method further includes testing the LED chip and fabricating the chip, and performing optoelectronic parameter testing through EL. However, the present application does not limit this, and it depends on the specific situation.
[0103] Next, a specific embodiment is used to describe the method for fabricating an LED chip provided by the embodiments of the present application.
[0104] Specifically, in this embodiment, the method for fabricating the LED chip includes:
[0105] Step 1: Introduce H2 into the deposition chamber at a high temperature of 1050°C to perform a 5-minute hydrogenation treatment on the sapphire substrate to remove impurities, scratches, particles, etc. on the substrate surface.
[0106] Step 2: At a temperature of 1000°C, introduce TMAl, SiH4, NH3, H2, and N2 into the deposition chamber to grow an AlN buffer layer, the thickness of the buffer layer is 25 nm, and the molar ratio of Si to Al is 0.2.
[0107] Step 3: Introduce NH3, H2, and N2 into the deposition chamber. At a temperature of 900 °C, using the lattice mismatch between GaN and AlN as the driving force, in a small ammonia atmosphere, utilize deposition decomposition to achieve three-dimensional island growth mode for 1 min to form a three-dimensional nucleation layer. Among them, the proportion of the NH3 component is 20%, and the thickness of the three-dimensional nucleation layer is 2000 nm.
[0108] Step 4: Introduce NH3, H2, and N2 into the deposition chamber. At a temperature of 1100 °C, and in a high-temperature large ammonia atmosphere, utilize diffusion to achieve lateral growth mode for 2 min to merge the three-dimensional islands into a GaN plane to form a two-dimensional merging layer. Among them, the proportion of the NH3 component is 80%, and the thickness of the two-dimensional merging layer is 1500 nm. It should be noted that in this embodiment, the two-dimensional merging layer is an unintentionally doped layer, and SiH4 is not introduced during its growth process.
[0109] Step 5: Use TEGa as the Ga source, and SiH4, NH3, H2, and N2 as the Si doping source, N source, and carrier gas respectively. Grow an N-type doped GaN layer at a high temperature of 1150 °C. The thickness of the N-type doped GaN layer is 300 nm, and the concentration of SiH4 is 2E18 / cm 3 。
[0110] Step 6: Use TMGa as the Ga source, and NH3, H2, and N2 as the N source and carrier gas respectively. Grow an Al x Ga 1-x N layer at a temperature of 1000 °C. The thickness of the Al x Ga 1-x N layer is 100 nm, it is not doped with Si, and the Al component x is 30%.
[0111] Step 7: Use TMGa as the Ga source, and SiH4, NH3, H2, and N2 as the Si doping source, N source, and carrier gas respectively. At a temperature of 1050 °C, grow the first group of superlattice layers, stress release layers, and the second group of superlattice layers composed of undoped Al y Ga 1-y N layers and N-type doped GaN layers in sequence; among them, the number of periods in the first group of superlattice layers is 40, the thickness of the Al y Ga 1-y N layer is 7.5 nm, the thickness of the GaN layer is 10 nm, the Al component y is 20%, and the Al y Ga 1-y N layer is not doped with Si, and the doping concentration of the GaN layer is 4E18 / cm y Ga 1-y ; the number of periods in the second group of superlattice layers is 20, and the Al 3 ;y Ga 1-y The thickness of the N layer is 5 nm, the thickness of the GaN layer is 10 nm, the Al composition y is 10%, and Al z Ga 1-z There is no Si doping in the N layer, and the doping concentration of the GaN layer is 8E18 / cm 3 ; The stress release layer is a 50-nm GaN layer.
[0112] Step 8: Introduce TMGa, NH3, and N2, and grow a 200-nm low-temperature gallium nitride layer at a temperature of 650 °C to transform the dislocation density into V-shaped pits.
[0113] Step 9: Introduce TEGa, TMIn, NH3, H2, and N2, and grow 6 periods of InGaN layer / GaN layer superlattice layers as a stress buffer layer; among them, the thickness of the InGaN layer is 10 nm, and the growth temperature is 800 °C; the thickness of the GaN layer is 2 nm, and the growth temperature is 880 °C. The total thickness of the stress buffer layer is 72 nm.
[0114] Step 10: Introduce TEGa, TMIn, SiH4, NH3, H2, and N2, and alternately grow 10 periods of quantum well layers and quantum barrier layers to form a quantum well active layer; among them, the thickness of the quantum well active layer is 14 nm; the thickness of the quantum well layer is 3 nm, and H2 is not introduced when growing the quantum well layer, and the growth temperature is 780 °C; the thickness of the quantum barrier layer is 11 nm, the quantum barrier layer is doped with Si, and the growth temperature is 900 °C
[0115] Step 11: Introduce TMAl, TMGa, CP2Mg, NH3, H2, and grow a P-type doped Al x Ga 1-x N layer under a growth pressure of 100 torr and a temperature of 900 °C in an N2 atmosphere at a growth rate of 20 A / s x Ga 1-x The thickness of the N layer is 200 nm, the doping concentration of Mg is 5E19 / cm 3 , and the Al composition x is 20%.
[0116] Step 12: Introduce TMGa, CP2Mg, NH3, H2, and N2, and grow a P-type doped GaN layer at a temperature of 1050, where the thickness of the P-type doped GaN layer is 400 nm and the concentration of Mg is 1E20 / cm 3 .
[0117] Step 13: Perform a cooling annealing treatment on the above LED chip structure to end the growth of the LED chip.
[0118] Step 14: Test the epitaxial wafer and fabricate the chip, and perform optoelectronic parameter tests through EL.
[0119] In the method for fabricating an LED chip provided by an embodiment of the present application, the N-type layer includes a stacked first constituent layer, second constituent layer, and third constituent layer. Among them, the first constituent layer is an N-type doped GaN layer, the second constituent layer is an undoped AlGaN layer, and the third constituent layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer. Thus, in the second constituent layer, the lattice mismatch caused by the substitution of Al atoms can cause dislocations to bend, so that the defects in the N-type layer are reduced or annihilated at this interface, thereby achieving the effect of shielding dislocations, further improving the growth quality of the N-type layer, improving the antistatic ability of the N-type layer, and ultimately improving the antistatic ability and reliability of the LED chip.
[0120] Correspondingly, an embodiment of the present application further provides an LED chip, as Figure 2 shown, including:
[0121] A substrate 10;
[0122] An N-type layer 50 located on one side of the substrate 10. The N-type layer 50 includes a stacked first constituent layer 51, second constituent layer 52, and third constituent layer 53. Among them, the first constituent layer 51 is an N-type doped GaN layer, the second constituent layer 52 is an undoped AlGaN layer, and the third constituent layer 53 includes a superlattice layer composed of an undoped AlGaN layer 531 and an N-type doped GaN layer 532;
[0123] A quantum well active layer 60 located on the side of the N-type layer 50 away from the substrate 10;
[0124] A P-type layer 90 located on the side of the quantum well active layer 60 away from the N-type layer 50.
[0125] Optionally, in an embodiment of the present application, the LED chip further includes: a buffer layer 20, a three-dimensional nucleation layer 30, and a two-dimensional merging layer 40 that are stacked between the substrate 10 and the N-type layer 50 along a first direction, and the first direction is perpendicular to the plane where the substrate is located.
[0126] Optionally, in an embodiment of the present application, the buffer layer 20 is an AlN buffer layer, the thickness of the buffer layer 20 ranges from 5 nm to 50 nm, including the endpoint values; the thickness of the three-dimensional nucleation layer 30 ranges from 1800 nm to 2200 nm, including the endpoint values, and the thickness of the two-dimensional merging layer 40 ranges from 1300 nm to 1700 nm, including the endpoint values. However, the present application does not limit this, and it depends on the specific situation.
[0127] Optionally, in an embodiment of the present application, the second component layer 52 is undoped Al x Ga 1-x N layer, where the value range of x is 0% to 50%, including the right endpoint value and excluding the left endpoint value. Thus, the lattice mismatch caused by the substitution effect of Al atoms causes dislocations to bend, and then defects are reduced or annihilated at this interface, achieving the effect of shielding dislocations, improving the quality of the second component layer 52, ultimately improving the quality of the N-type layer 50, and enhancing the electrostatic discharge resistance and reliability of the LED chip.
[0128] Optionally, in an embodiment of the present application, the thickness of the second component layer 52 ranges from 50 nm to 800 nm, including the endpoint values, and the growth temperature of the second component layer 52 ranges from 950 °C to 1050 °C, including the endpoint values. However, the present application does not limit this, and it depends on the specific situation.
[0129] In the LED chip provided by the embodiment of the present application, the N-type layer includes a stacked first component layer 51, a second component layer 52, and a third component layer 53. Among them, the first component layer 51 is an N-type doped GaN layer, the second component layer 52 is an undoped AlGaN layer, and the third component layer 53 includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer. Thus, in the second component layer 52, the lattice mismatch caused by the substitution effect of Al atoms causes dislocations to bend, so that defects in the N-type layer 50 are reduced or annihilated at this interface, thereby achieving the effect of shielding dislocations, further improving the growth quality of the N-type layer 50, enhancing the electrostatic discharge resistance of the N-type layer 50, and ultimately improving the electrostatic discharge resistance and reliability of the LED chip.
[0130] Optionally, in an embodiment of the present application, the gallium source during the growth of the first component layer 51 is TEGa, that is, during the growth of the first component layer 51, TEGa is selected as the Ga source instead of TMGa. This is beneficial to improving the surface flatness and cleanliness, reducing the formation of defects during the growth process, thereby facilitating the reduction of the introduction of carbon impurities to provide higher material quality, improving the growth quality of the first component layer 51, further improving the growth quality of the N-type layer 50, enhancing the electrostatic discharge resistance of the N-type layer 50, and ultimately improving the electrostatic discharge resistance and reliability of the LED chip.
[0131] Optionally, in an embodiment of the present application, the growth temperature of the first component layer 51 ranges from 1100 °C to 1200 °C, including the endpoint values, to increase the cracking rate of TEGa. However, the present application does not limit this, and it depends on the specific situation.
[0132] Optionally, in an embodiment of the present application, the thickness of the first component layer 51 ranges from 200 nm to 400 nm, including the endpoint values, but the present application does not limit this, and it depends on the specific situation.
[0133] Based on any of the above embodiments, in an embodiment of the present application, the third component layer 53 includes at least two groups of superlattice layers, and each group of superlattice layers is composed of periodically arranged undoped Al y Ga 1-y N layers 531 and N-type doped GaN layers 532; Optionally, in an embodiment of the present application, the third component layer 53 includes two groups of superlattice layers, and each group of superlattice layers is composed of periodically arranged undoped Al y Ga 1-y N layers 531 and N-type doped GaN layers 532; wherein, the number of periods of the undoped AlGaN layer 531 and the N-type doped GaN layer 532 in the first group of superlattice layers ranges from 30 to 50, including the endpoint values, and the thickness ratio of the undoped Al y Ga 1-y N layer 531 and the N-type doped GaN layer 532 is 7.5 / 10; in the second group of superlattice layers, the number of periods of the undoped Al y Ga 1-y N layer 531 and the N-type doped GaN layer 532 ranges from 15 to 25, including the endpoint values, and the thickness ratio of the undoped Al y Ga 1-y N layer 531 and the N-type doped GaN layer 532 is 5 / 10; and the value of y in the second group of superlattice layers is less than the value of y in the first group of superlattice layers. Specifically, in an embodiment of the present application, the value of y in the first group of superlattice layers ranges from 10% to 30%, including the endpoint values, and the value of y in the second group of superlattice layers ranges from 0% to 20%, including the right endpoint value and not including the left endpoint value, but the present application does not limit this, and it depends on the specific situation.
[0134] In an embodiment of the present application, in the superlattice layer composed of periodically arranged undoped Al y Ga 1-y N layers and N-type doped GaN layers, the undoped single layer (i.e., the undoped Al y Ga 1-yThe improvement of the electron mobility in the third constituent layer (i.e., the N-layer) is higher than the decrease in the effective average electron concentration within a single period after the diffusion of the electron concentration in the N-type doped single layer (i.e., the N-type doped GaN layer), so that the third constituent layer has a higher conductivity, and further the N-type layer has a higher conductivity. Moreover, the modulation doping of the undoped single layer and the N-type doped single layer can cause the stress state in the third constituent layer to change periodically, providing stress buffering for the subsequent growth of the quantum well active layer.
[0135] In addition, in the third constituent layer 53, a superlattice layer structure composed of alternately grown undoped Al y Ga 1-y N layers and N-type doped GaN layers can further bend and close the dislocations in the N-type layer, reduce the number of threading dislocations, improve the crystal quality, and thus improve the electrostatic resistance and reliability of the LED chip.
[0136] It should be noted that in this embodiment, in the first group of superlattice layers, the Al y Ga 1-y N layer is not doped with Si, and the GaN layer is doped with Si; in the second group of superlattice layers, the Al y Ga 1-y N layer is not doped with Si, and the GaN layer is doped with Si. Optionally, in an embodiment of the present application, the doping concentration of the GaN layer in the first superlattice layer is 4E18 / cm 3 , and the doping concentration of the GaN layer in the second superlattice layer is 8E18 / cm 3 , but the present application does not limit this, and it depends on the specific situation.
[0137] Based on any of the above embodiments, in an embodiment of the present application, the LED chip further includes: a stress release layer located between the first group of superlattice layers and the second group of superlattice layers to reduce the stress generated during the growth of the third constituent layer. Optionally, in an embodiment of the present application, the stress release layer is a GaN layer, and the thickness ranges from 30 nm to 80 nm, including the end values, but the present application does not limit this, and it depends on the specific situation.
[0138] Based on any of the above embodiments, in an embodiment of the present application, the LED chip further includes: a stress buffer layer 70 located between the N-type layer 50 and the quantum well active layer 60. Optionally, in an embodiment of the present application, the stress buffer layer 70 is a superlattice layer composed of periodically arranged InGaN layers and GaN layers. Among them, the number of periods of the InGaN layer and the GaN layer ranges from 5 to 10, including the end values. The total thickness of the superlattice layer composed of the InGaN layer and the GaN layer ranges from 60 nm to 120 nm, including the end values. The growth temperature of the InGaN layer ranges from 700 °C to 850 °C, including the end values. The growth temperature of the GaN layer ranges from 800 °C to 1000 °C, including the end values. However, the present application does not limit this, and it depends on the specific situation.
[0139] Specifically, in an embodiment of the present application, the thickness of the InGaN layer in the stress buffer layer 70 is 10 nm, and the thickness of the GaN layer is 2 nm. However, the present application does not limit this, and it depends on the specific situation.
[0140] Optionally, in an embodiment of the present application, the LED chip has a V pit. In this embodiment, the LED chip further includes: a low-temperature gallium nitride layer 80 located between the N-type layer 50 and the stress buffer layer 70 to convert the dislocation density to form a V-shaped pit. Among them, the V pit penetrates through the quantum well active layer 60 and the stress buffer layer 70 and extends into the low-temperature gallium nitride layer 80. Among them, the growth temperature of the low-temperature gallium nitride layer 80 ranges from 600 °C to 800 °C, including the end values, and the thickness ranges from 150 nm to 250 nm, including the end values. However, the present application does not limit this, and it depends on the specific situation.
[0141] Based on any of the above embodiments, in an embodiment of the present application, the quantum well active layer 80 includes a superlattice layer composed of periodically arranged quantum well layers and quantum barrier layers. Optionally, the growth temperature of the quantum well layer ranges from 700 °C to 850 °C, including the end values; the growth temperature of the quantum barrier layer ranges from 800 °C to 1000 °C, including the end values. However, the present application does not limit this, and it depends on the specific situation.
[0142] Optionally, in an embodiment of the present application, the total thickness of the quantum well active layer 80 ranges from 10 nm to 16 nm, including the end values. The number of periods of the quantum well and the quantum barrier ranges from 8 to 12, including the end values; the thickness of the quantum well is 3 nm, and the thickness of the quantum barrier is 11 nm. However, the present application does not limit this, and it depends on the specific situation.
[0143] Based on any of the above embodiments, in an embodiment of the present application, the P-type layer 90 includes a stacked P-type doped Al x Ga 1-x N layer 91 and a P-type doped GaN layer 92. Optionally, in an embodiment of the present application, the P-type doped Al x Ga 1-x The thickness of the N layer 91 ranges from 150 nm to 250 nm, including the end values. The value range of the Al component x is from 0% to 50%, including the right end value and excluding the left end value; the thickness of the P-type doped GAN layer 92 ranges from 200 nm to 600 nm, including the end values, but the present application does not limit this, and it depends on the specific situation.
[0144] In summary, in the LED chip provided by the embodiment of the present application, the N-type layer includes a stacked first composition layer, a second composition layer, and a third composition layer. Among them, during the growth process of the first composition layer, TEGa is selected as the Ga source instead of TMGa as the Ga source, which is beneficial to improving the surface flatness and cleanliness, reducing the formation of defects during the growth process, thereby being beneficial to reducing the introduction of carbon impurities, providing higher material quality, improving the growth quality of the first composition layer, further improving the growth quality of the N-type layer, improving the antistatic ability of the N-type layer, and ultimately improving the antistatic ability and reliability of the LED chip.
[0145] In the LED chip provided by the embodiment of the present application, the second composition layer is an undoped Al x Ga 1-x N layer, and the value range of x is from 0% to 50%, including the right end value and excluding the left end value. Thus, the lattice mismatch caused by the substitution effect of Al atoms causes the dislocations to bend, and then the defects are reduced or annihilated at this interface, achieving the effect of shielding dislocations, improving the quality of the second composition layer, ultimately improving the quality of the N-type layer, and improving the antistatic ability and reliability of the LED chip.
[0146] In the LED chip provided by the embodiment of the present application, the third composition layer includes at least two groups of superlattice layers, and each group of superlattice layers is composed of periodically arranged undoped Al y Ga 1-y N layer and an N-type doped GaN layer. And in the superlattice layer composed of periodically arranged undoped Al y Ga 1-y N layer and an N-type doped GaN layer, the undoped single layer (i.e., the undoped Al y Ga 1-yThe improvement of the electron mobility in the third constituent layer (i.e., the N-layer) is higher than the decrease in the effective average electron concentration within a single period after the diffusion of the electron concentration in the N-type doped single layer (i.e., the N-type doped GaN layer), so that the third constituent layer has a higher conductivity, and further the N-type layer has a higher conductivity. Moreover, the modulation doping of the undoped single layer and the N-type doped single layer can cause the stress state in the third constituent layer to change periodically, providing stress buffering for the subsequent growth of the quantum well active layer.
[0147] In addition, in the third constituent layer, a superlattice layer structure composed of alternately grown undoped Al y Ga 1-y N layers and N-type doped GaN layers can further bend and close the dislocations in the N-type layer, reduce the number of threading dislocations, improve the crystal quality, and thus improve the antistatic ability and reliability of the LED chip.
[0148] The various embodiments in this specification are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.
[0149] It should be noted that in the description of this application, it should be understood that the descriptions of the drawings and embodiments are illustrative rather than restrictive. It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the article or device including the above element.
[0150] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for fabricating an LED chip, characterized in that, Comprising: Forming an N-type layer on one side of a substrate, the N-type layer including a stacked first constituent layer, second constituent layer, and third constituent layer, wherein the first constituent layer is an N-type doped GaN layer, the second constituent layer is an undoped AlGaN layer, and the third constituent layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer; Forming a quantum well active layer on the side of the N-type layer away from the substrate; Forming a P-type layer on the side of the quantum well active layer away from the N-type layer.
2. The manufacturing method of the LED chip according to claim 1, wherein, Forming an N-type layer on one side of a substrate, the N-type layer including a stacked first constituent layer, second constituent layer, and third constituent layer including: Forming a first constituent layer on one side of a substrate; Forming a second constituent layer on the side of the first constituent layer away from the substrate; Forming a third constituent layer on the side of the second constituent layer away from the first constituent layer; Wherein, the gallium source during the growth of the first constituent layer is TEGa, and forming the first constituent layer on one side of the substrate includes: using TEGa as the Ga source to grow an N-type doped GaN layer on one side of the substrate.
3. The manufacturing method of the LED chip according to claim 2, characterized in that, The growth temperature of the first constituent layer ranges from 1100 °C to 1200 °C, including the end values; the thickness of the first constituent layer ranges from 200 nm to 400 nm, including the end values; the thickness of the second constituent layer ranges from 50 nm to 800 nm, including the end values; the growth temperature of the second constituent layer ranges from 950 °C to 1050 °C, including the end values.
4. The manufacturing method of the LED chip according to claim 2, wherein Forming a second constituent layer on the side of the first constituent layer away from the substrate includes: Using TMGa as the Ga source to form a growth AlxGa1-xN layer on the side of the first constituent layer away from the substrate; wherein, the value range of x is from 0% to 50%, including the right endpoint value and not including the left endpoint value.
5. The manufacturing method of the LED chip according to claim 2, characterized in that, Forming a third constituent layer on the side of the second constituent layer away from the first constituent layer includes: Using TMGa as the Ga source, grow K groups of superlattice layers on the side of the second composition layer away from the first composition layer. Each group of superlattice layers includes periodically spaced undoped Al y Ga 1-y N layers and N-type doped GaN layers, where K is a positive integer.
6. The manufacturing method of the LED chip according to claim 5, wherein, K is 2. In the first group of superlattice layers, undoped Al y Ga 1-y The number of periods of the N layer and the N-type doped GaN layer ranges from 30 to 50, including the end values; in the first group of superlattice layers, undoped Al y Ga 1-y The thickness ratio of the N layer and the N-type doped GaN layer is 7.5 / 10; In the second group of superlattice layers, undoped Al y Ga 1-y The number of periods of the N layer and the N-type doped GaN layer ranges from 15 to 25, including the end values; in the second group of superlattice layers, undoped Al y Ga 1-y The thickness ratio of the N layer and the N-type doped GaN layer is 5 / 10; The value of y in the second group of superlattice layers is less than the value of y in the first group of superlattice layers.
7. The manufacturing method according to claim 6, characterized in that, The value range of y in the first group of superlattice layers is from 10% to 30%, including the end values; the value range of y in the second group of superlattice layers is from 0% to 20%, including the right endpoint value and not including the left endpoint value.
8. The manufacturing method of the LED chip according to claim 7, characterized in that, Forming a third constituent layer on the side of the second constituent layer away from the first constituent layer further includes: Growing a stress release layer between the first group of superlattice layers and the second group of superlattice layers.
9. An LED chip, characterized in that, Comprising: A substrate; An N-type layer located on one side of the substrate, the N-type layer including a stacked first constituent layer, second constituent layer, and third constituent layer, wherein the first constituent layer is an N-type doped GaN layer, the second constituent layer is an undoped AlGaN layer, and the third constituent layer includes a superlattice layer composed of an undoped AlGaN layer and an N-type doped GaN layer; A quantum well active layer located on the side of the N-type layer away from the substrate; A P-type layer located on the side of the quantum well active layer away from the N-type layer.
10. The LED chip according to claim 9, wherein, During the growth of the first composition layer, the gallium source is TEGa, and the growth temperature of the first composition layer ranges from 1100°C to 1200°C, including the end values; the growth temperature of the GaN layer in the third composition layer ranges from 1000°C to 1100°C, including the end values.
11. The LED chip according to claim 9, wherein The second composition layer is an undoped AlxGa1-xN layer, with a thickness ranging from 50 nm to 800 nm, including the end values, a growth temperature ranging from 950 to 1050°C, including the end values, and the value of x ranging from 0% to 50%, including the right end value but not the left end value. The gallium source during the growth of the second composition layer is TMGa; The third composition layer includes at least two groups of superlattice layers, and each group of superlattice layers is composed of periodically arranged undoped Al y Ga 1-y N layers and N-type doped GaN layers; among them, The number of periods of the undoped AlGaN layer and the N-type doped GaN layer in the first group of superlattice layers ranges from 30 to 50, including the end values. The undoped Al y Ga 1-y N layer and the N-type doped GaN layer have a thickness ratio of 7.5 / 10; In the second group of superlattice layers, undoped Al y Ga 1-y The number of periods of the N layer and the N-type doped GaN layer ranges from 15 to 25, including the end values. The undoped Al y Ga 1-y The thickness ratio of the N layer and the N-type doped GaN layer is 5 / 10; The value of y in the second superlattice layer is less than the value of y in the first superlattice layer.
12. The LED chip according to claim 11, wherein, The value of y in the first superlattice layer ranges from 10% to 30%, including the end values, and the value of y in the second superlattice layer ranges from 0% to 20%, including the right end value but not the left end value.
13. The LED chip according to claim 11, wherein, Further comprising: A stress relaxation layer located between the first superlattice layer and the second superlattice layer.