Novel-characteristic double-channel transistor and preparation method thereof

Abstract

The invention discloses a new-characteristic double-channel transistor and a preparation method, the transistor comprises a grid electrode, a dielectric layer, an organosilane layer, a blending layer and an organic semiconductor SII layer which are stacked in sequence from bottom to top, a source electrode and a drain electrode are evaporated on the organic semiconductor SII layer, a doping layer is further evaporated on the upper layer of the organic semiconductor SII layer, and the doping layer is arranged on the lower layer of the organic semiconductor SII layer. The blending layer comprises an organic semiconductor SI layer and an insulating polymer layer, the energy levels and mobility of the organic semiconductor SI layer and the organic semiconductor SII layer are different, the organic semiconductor SI layer and the organic semiconductor SII layer jointly serve as channel layers to be used for charge transfer, and the insulating polymer and the organic semiconductor SI are blended to prepare the ultrathin organic semiconductor SI layer through vertical phase separation. The insulating polymer is simultaneously used as a charge storage layer to regulate and control device characteristics, the organosilane layer is used for surface modification of the dielectric layer and induction of vertical phase separation of the insulating polymer and the organic semiconductor SI, and the doping layer is used for filling a trap state of a channel material and changing a charge transfer energy level.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor electronic devices, and specifically relates to a dual-channel transistor with novel characteristics and a preparation method thereof. Background Art

[0002] Field-effect transistors are the cornerstone of contemporary microelectronics and power electronics technologies, and their applications involve multiple fields such as logic circuits, sensing, storage, display, signal modulation, etc. The function of a field-effect transistor depends on its charge transport characteristics. For traditional field-effect transistors, their source-drain current is proportional to the gate voltage V G 、V G 2 respectively in the linear region and the saturation region. So far, a series of field-effect transistors with unconventional characteristics have been developed, including source-gate transistors, negative-capacitance transistors, multi-gate devices, negative-transconductance transistors, etc. According to the unconventional characteristics of these devices, the applications of field-effect transistors in signal processing, low-power and high-speed electronics, and high-processing-capability chips have been expanded.

[0003] The accumulation and distribution of charges in the direction perpendicular to the plane of the active layer thin film are the key factors affecting the characteristics of transistors. By preparing devices with a vertically phase-separated structure or a multi-layer structure to obtain vertically distributed components in the thin film, it has been proven that various special device characteristics can be achieved. For example, non-volatile field-effect transistors with vertically resolved components are developed using vertical phase separation. Transistors with special charge accumulation methods are obtained by blending isotactic / atactic P3HT to construct transistors with special charge accumulation methods, resulting in device characteristics deviating from conventional devices. In multi-layer structure field-effect transistors, p and n dual channels are constructed to achieve separate transport of holes and electrons, and the device exhibits bipolar transport or specific optoelectronic characteristics. Transistors are constructed using a heterostacked dual-channel structure, and the device exhibits cascaded switching behavior. Although many functions have been achieved by modulating the accumulation and distribution of charges in the vertical direction, in the prior art, most of the dual-channel transistors prepared using the same type of semiconductor exhibit traditional device characteristics and are difficult to meet the requirements of integrated circuits and artificial intelligence for multifunctional electronic devices. At the same time, there is also a lack of devices that combine special characteristics and non-volatility, which is of great significance for expanding reconfigurable applications. Therefore, it is necessary to propose a dual-channel transistor with novel characteristics and its preparation method to solve the above problems. Summary of the Invention

[0004] The purpose of this application is to solve the problems of the prior art, and provides a dual-channel transistor with novel characteristics and a preparation method thereof.

[0005] To solve the technical problems, the technical solution of this application is: a dual-channel transistor with novel characteristics, including a gate, a dielectric layer, an organosilane layer, a blend layer, and an organic semiconductor SII layer stacked in sequence from bottom to top, and a source electrode and a drain electrode are evaporated above the organic semiconductor SII layer; The blend layer is prepared by blending an insulating polymer and an organic semiconductor SI through vertical phase separation, forming a vertically phase-separated organic semiconductor SI layer and an insulating polymer layer. The organic semiconductor SI layer is close to the organic semiconductor SII layer, and the insulating polymer layer is close to the organosilane layer; The mobility of the organic semiconductor SII layer is higher than that of the organic semiconductor SI layer, and the highest occupied molecular orbital energy level of the organic semiconductor SII layer is lower than that of the organic semiconductor SI layer; The materials of both the organic semiconductor SI layer and the organic semiconductor SII layer are p-type semiconductors; The material of the organosilane layer and the material of the insulating polymer layer have the same group, and the same group is selected from one of benzene ring, methoxy group, ethoxy group or halogen atom.

[0006] Preferably, the material of the organosilane layer is selected from one of phenyltrichlorosilane, octadecyltrichlorosilane, trimethoxysilane or triethoxysilane; the material of the organic semiconductor SI layer is selected from PDVT-10 or PM6; the material of the insulating polymer layer is selected from one of PS, PVN, PMMA or PαMS; the material of the organic semiconductor SII layer is selected from organic small molecule C8-BTBT or C12-BTBT.

[0007] Preferably, a doping layer is further evaporated on the upper layer of the organic semiconductor SII layer, and the doping material of the doping layer is selected from one of F4-TCNQ, F6-TCNNQ or F2-HCNQ, and the lowest unoccupied molecular orbital energy level of the doping layer is lower than the defect energy level of the organic semiconductor SII layer.

[0008] Preferably, the thickness of the doping layer is 3 - 8 nm.

[0009] Preferably, the mobility range of the material of the organic semiconductor SI layer is 0.01 cm –2 V –1 s –1 ~1 cm –2 V –1 s –1 , and the mobility range of the material of the organic semiconductor SII layer is 2.5 cm –2 V –1 s –1 ~20 cm –2 V –1 s –1 。

[0010] Preferably, the thickness of the organic semiconductor SII layer is 40 - 100 nm, the thickness of the blend layer is 40 - 100 nm, and the thickness of the organic semiconductor SI layer is 2 - 8 nm.

[0011] Preferably, a method for manufacturing a new - characteristic double - channel transistor includes the following steps: Step 1: Purchase a dielectric layer with a gate, perform plasma etching on the cleaned dielectric layer, and use organosilane for surface modification to obtain an organosilane layer; Step 2: Spin - coat a blend solution of an insulating polymer and organic semiconductor SI on the organosilane layer modified in Step 1. The mass ratio of the insulating polymer to organic semiconductor SI is 4:1 to 19:1. The solvent of the blend solution is ortho - dichlorobenzene, and the concentration of organic semiconductor SI is 5 - 8 mg / mL –1 , the spin - coating speed ranges from 1000 rpm to 3000 rpm, and then anneal at 120 - 180 °C for 30 min to obtain a blend layer, forming a vertically phase - separated organic semiconductor SI layer and insulating polymer layer; Step 3: Then, prepare an organic semiconductor SII layer by evaporation deposition method, with an evaporation rate of 0.1 - 0.4 Å / s –1 , and the thickness is 40 - 100 nm; Step 4: Prepare the source and drain by evaporation deposition method. The evaporation material is gold, with an evaporation rate of 0.5 - 0.8 Å / s –1 , and the thickness is 40 - 60 nm; Use a mask to control the channel length to be 1 - 300 μm and the channel width to be 3 - 5 mm; Step 5: Prepare a doping layer on the organic semiconductor SII layer by evaporation deposition method, with an evaporation rate of 0.1 - 0.4 Å / s –1 , and the thickness is 3 - 8 nm, obtaining a new - characteristic double - channel transistor; The output characteristic curve of the new - characteristic double - channel transistor has an extended linear region, and the curves under different gate voltages V G conditions overlap within the linear region; On the transfer characteristic curve, when the source - drain voltage V D <V G –V T , I D does not change with V G ; When V D ≥V G –V T , I D has a linear relationship with V G , I D is the source - drain current, and V T is the threshold voltage.

[0012] Preferably, step 1 is specifically as follows: The dielectric layer is successively ultrasonically treated with water, acetone, and isopropyl alcohol for 10 - 15 min. The cleaned dielectric layer is subjected to plasma etching, which is carried out under a gas pressure < 20 Pa for 5 - 10 min. The etched dielectric layer is modified with a toluene solution of organosilane, the solution concentration is 5‰, the modification temperature is 80 - 90 °C, and the duration is 1.5 - 3 h.

[0013] Compared with the prior art, the advantages of this application are as follows: (1) This application discloses an organic double-channel transistor for preparing the same type of semiconductor. An organosilane layer and a blend layer are designed. The insulating polymer in the organosilane layer and the blend layer has the same groups, resulting in a layered structure of the blend layer. Among them, the insulating polymer is distributed in the bottom layer as an electret, making the device non-volatile. The organic semiconductor SI layer is distributed in the top layer as one of the channels. The organic semiconductor SI layer formed in this way has a very thin thickness, ensuring that charges can be transmitted simultaneously in both the organic semiconductor SI layer and the organic semiconductor SII layer, that is, the formation of a double channel; (2) This application proposes the selection principle for the materials of the organic semiconductor SI layer and the organic semiconductor SII layer: The organic semiconductor SI layer is a polymer semiconductor, the organic semiconductor SII layer is a small molecule semiconductor, and the mobility of the organic semiconductor SII layer is higher than that of the organic semiconductor SI layer; the HOMO energy level of the organic semiconductor SI layer should be slightly higher than that of the organic semiconductor SII layer, so as to ensure that charges can accumulate simultaneously in the two semiconductor layers to form a double channel; (3) This application discloses the new characteristics of the double-channel transistor. These new characteristics are different from those of the double-channel transistors in the existing patents: The output characteristic curve has an extended linear region, and the curves under different gate voltages V G conditions coincide; on the transfer characteristic curve, when the source-drain voltage V D < V G – V T , I D does not change with V G ; when V D ≥ V G – V T , I D has a linear relationship with V G , I D is the source-drain current, and V T is the threshold voltage; in addition, the device also exhibits non-volatility, which makes such devices have great potential application value in fields such as reconfigurable signal modulation. Description of the Drawings

[0014] Figure 1It is a schematic structural diagram of a new feature dual-channel transistor of this application; Figure 2 It is a comparison diagram of the structures and characteristic curves of the dual-channel transistor and the conventional transistor of this application; Figure 3 It is a comparison diagram of the energy bands of the organic semiconductors involved in this application; Figure 4 It is the ultraviolet-visible absorption spectrum of the PM6@PS blend film in Example 1 of this application using plasma etching for different times; Figure 5 It is the ultraviolet-visible absorption spectrum of the control component variable film in Example 1 of this application; Figure 6 For the PM6@PS / C12-BTBT / F4-TCNQ dual-channel transistor in Example 1 of this application, (a) output curve and (b–c) transfer characteristic curves; Figure 7 For the PDVT-10@PS / C12-BTBT / F4-TCNQ dual-channel transistor in Example 2 of this application, (a) output curve and (b–c) transfer characteristic curves; Figure 8 For the PDVT-10@PS / C12-BTBT / F4-TCNQ dual-channel transistor in Example 2 of this application, (a) programming state charge accumulation schematic diagram and (b) non-volatility research diagram; Figure 9 For the transfer characteristic diagram of the PM6@PS / C12-BTBT dual-channel transistor in Example 3 of this application; Figure 10 For the PM6 / C12-BTBT transistor in Comparative Example 1 of this application, (a) device structure, (b) output curve and (c) transfer characteristic curves; Figure 11 For the PBTTT@PS / C12-BTBT transistor in Comparative Example 2 of this application, (a) output curve and (b–c) transfer characteristic curves; Figure 12 For the PCDTPT@PS / C12-BTBT transistor in Comparative Example 3 of this application, (a) output curve and (b–c) transfer characteristic curves.

[0015] Explanation of reference numerals: 1. Gate, 2. Dielectric layer, 3. Organosilane layer, 4. Blend layer, 5. Organic semiconductor SII layer, 6. Source electrode, 7. Drain electrode, 8. Doped layer; 41. Organic semiconductor SI layer, 42. Insulating polymer layer. Detailed implementation manners

[0016] The present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but the present application is not limited to these embodiments. The present application covers any alternatives, modifications, equivalent methods, and solutions made within the spirit and scope of the present application. In order to enable the public to have a thorough understanding of the present application, specific details are described in detail in the following embodiments of the present application, and those skilled in the art can fully understand the present application without the description of these details.

[0017] As Figure 1 shown, the present application discloses a novel feature double-channel transistor, which includes a gate 1, a dielectric layer 2, an organosilane layer 3, a blend layer 4, and an organic semiconductor SII layer 5 stacked in sequence from bottom to top. An anode 6 and a drain 7 are evaporated above the organic semiconductor SII layer 5; The blend layer 4 is prepared by blending an insulating polymer and an organic semiconductor SI through vertical phase separation, forming a vertically phase-separated organic semiconductor SI layer 41 and an insulating polymer layer 42. The organic semiconductor SI layer 41 is close to the organic semiconductor SII layer 5, and the insulating polymer layer 42 is close to the organosilane layer 3; The mobility of the organic semiconductor SII layer 5 is higher than that of the organic semiconductor SI layer 41, and the highest occupied molecular orbital energy level of the organic semiconductor SII layer 5 is lower than that of the organic semiconductor SI layer 41; The materials of both the organic semiconductor SI layer 41 and the organic semiconductor SII layer 5 are p-type semiconductors; The material of the organosilane layer 3 and the material of the insulating polymer layer 42 have the same group, and the same group is selected from one of benzene ring, methoxy group, ethoxy group, or halogen atom.

[0018] Preferably, the material of the organosilane layer 3 is selected from one of phenyltrichlorosilane, octadecyltrichlorosilane, trimethoxysilane, or triethoxysilane; the material of the organic semiconductor SI layer 41 is selected from PDVT-10 or PM6; the material of the insulating polymer layer 42 is selected from one of PS, PVN, PMMA, or PαMS; the material of the organic semiconductor SII layer 5 is selected from organic small molecule C8-BTBT or C12-BTBT.

[0019] Preferably, a doping layer 8 is further evaporated above the organic semiconductor SII layer 5. The doping material of the doping layer 8 is selected from one of F4-TCNQ, F6-TCNNQ, or F2-HCNQ, and the lowest unoccupied molecular orbital energy level of the doping layer 8 is lower than the defect energy level of the organic semiconductor SII layer 5.

[0020] The organic semiconductor SI layer 41 and the organic semiconductor SII layer 5 are used as channel layers for charge transport. The insulating polymer and the organic semiconductor SI are blended to prepare the ultra-thin organic semiconductor SI layer 41 through vertical phase separation. The insulating polymer also serves as a charge storage layer to regulate the device characteristics. The organosilane layer 3 is used to induce vertical phase separation. The doping layer 8 is used to fill the trap states of the channel material and change the charge transport energy levels.

[0021] The organosilane layer 3 has a chemical structure similar to that of the insulating polymer or can significantly change the surface characteristics of the dielectric layer, thereby inducing the vertical phase separation of the organic semiconductor SI and the insulating polymer, with the insulating polymer distributed below and the organic semiconductor SI above.

[0022] Preferably, the thickness of the doping layer 8 is 3 - 8 nm.

[0023] Preferably, the mobility range of the material of the organic semiconductor SI layer 41 is 0.01 cm –2 V –1 s –1 ~1 cm –2 V –1 s –1 and the mobility range of the material of the organic semiconductor SII layer 5 is 2.5 cm –2 V –1 s –1 ~20 cm –2 V –1 s –1 。

[0024] The highest occupied molecular orbital (HOMO) energy level of the organic semiconductor SII is lower than that of the organic semiconductor SI. The doping level of the doping layer meets the requirements of the doped semiconductor, that is, the lowest unoccupied molecular orbital (LUMO) energy level of the dopant is lower than the defect energy level of the organic semiconductor SII.

[0025] Preferably, the thickness of the organic semiconductor SII layer 5 is 40 - 100 nm, the thickness of the blend layer 4 is 40 - 100 nm, and the thickness of the organic semiconductor SI layer 41 is 2 - 8 nm.

[0026] Preferably, a preparation method of a novel characteristic double-channel transistor includes the following steps: Step 1: Purchase the dielectric layer 2 with the gate 1, perform plasma etching on the cleaned dielectric layer 2, and use organosilane for surface modification to obtain the organosilane layer 3; Step 2: Spin-coat the blend solution of the insulating polymer and the organic semiconductor SI on the organosilane layer 3 modified in Step 1. The mass ratio of the insulating polymer to the organic semiconductor SI is 4:1 - 19:1. The solvent of the blend solution is o-dichlorobenzene, and the concentration of the organic semiconductor SI is 5 - 8 mg mL–1 The spin coating speed ranges from 1000 rpm to 3000 rpm, and then annealing is carried out at 120 - 180 °C for 30 min to obtain the blend layer 4, forming the vertically phase - separated organic semiconductor SI layer 41 and the insulating polymer layer 42; Step 3, then prepare the organic semiconductor SII layer 5 by evaporation, and the evaporation rate is 0.1 - 0.4 Å / s –1 with a thickness of 40 - 100 nm; Step 4, prepare the source electrode 6 and the drain electrode 7 by evaporation, the evaporation material is gold, and the evaporation rate is 0.5 - 0.8 Å / s –1 with a thickness of 40 - 60 nm; use a mask to control the channel length to be 1 - 300 μm and the channel width to be 3 - 5 mm; Step 5, prepare the doping layer 8 on the organic semiconductor SII layer 5 by evaporation, and the evaporation rate is 0.1 - 0.4 Å / s –1 with a thickness of 3 - 8 nm, obtaining a new - characteristic double - channel transistor; The output characteristic curve of the new - characteristic double - channel transistor has an extended linear region, and the curves under different gate voltages V G conditions coincide; on the transfer characteristic curve, when the source - drain voltage V D < V G –V T , I D does not change with V G ; when V D ≥V G –V T , I D has a linear relationship with V G , I D is the source - drain current, and V T is the threshold voltage.

[0027] This application uses this method to construct two charge - transport channels, namely the organic semiconductor SI layer 41 and the organic semiconductor SII layer 5, in the transistor. The transistor exhibits unconventional characteristics. In addition, the insulating polymer acts as an electret and can be used for charge storage, so the device exhibits non - volatility.

[0028] Preferably, step 1 is specifically: ultrasonically treat the dielectric layer 2 with water, acetone, and isopropanol in sequence for 10 - 15 min, perform plasma etching on the cleaned dielectric layer 2, the plasma etching is carried out under a gas pressure < 20 Pa, the treatment time is 5 - 10 min, modify the etched dielectric layer 2 with a toluene solution of organosilane, the solution concentration is 5‰, the modification temperature is 80 - 90 °C, and the duration is 1.5 - 3 h.

[0029] The novel feature double-channel transistor involved in the following embodiments includes a gate 1, a dielectric layer 2, an organosilane layer 3, a blend layer 4, and an organic semiconductor SII layer 5. An active source 6 and a drain 7 are evaporated above the organic semiconductor SII layer 5; doped Si is used as the gate, SiO2 is used as the dielectric layer, and the formed substrate is Si / SiO2, and the source / drain is Au. The organic semiconductor SII material of the organic semiconductor SII layer is selected from organic small molecules C8-BTBT or C12-BTBT; the organic semiconductor SI material of the organic semiconductor SI layer is selected from PDVT-10 or PM6; the material of the insulating polymer layer 42 is selected from one of PS, PVN, PMMA, or PαMS, and the material of the organosilane layer 3 is selected from one of phenyltrichlorosilane, octadecyltrichlorosilane, trimethoxysilane, or triethoxysilane, and the dopant material of the doped layer 8 is selected from one of F4-TCNQ, F6-TCNNQ, or F2-HCNQ, as follows:

[0030] The organic semiconductor SI layer material in the comparative example is selected from:

[0031] As Figure 2 shown, a comparison diagram of the structures and characteristic curves of the double-channel transistor of the present application and a conventional transistor is disclosed. In the figure, (a) is the structure diagram of the conventional transistor, and the conventional transistor includes a dielectric layer and a semiconductor layer, as well as a source, a drain, and a gate. (b), (c), and (d) are the characteristic curves of the conventional transistor, (e) is the structure diagram of the double-channel transistor of the present application, and (f), (g), and (h) are the characteristic curves of the double-channel transistor of the present application; Figure 3 shows the energy band structure of the organic semiconductor involved in the present application.

[0032] Example 1 This embodiment provides a preparation method for a novel feature double-channel transistor, which is specifically as follows: Step 1: Use doped silicon / silicon dioxide (Si / SiO2) as the substrate. Doped silicon is used as the gate of the novel feature double-channel transistor described in the present application, and SiO2 is used as the dielectric layer with a thickness of 300 nm. The substrate is ultrasonically treated with water, acetone, and isopropyl alcohol in sequence, and the time is 10 min for each. The cleaned Si / SiO2 substrate is subjected to plasma etching treatment, and the plasma etching is carried out under the condition of a gas pressure < 20 Pa, and the treatment time is 5 min. The etched Si / SiO2 is modified with a toluene solution of phenyltrichlorosilane, the solution concentration is 5‰, the modification temperature is 80 °C, and the duration is 2 h.

[0033] Step 2: Spin-coat a blend solution of PM6 and PS on the substrate modified in Step 1. The mass ratio of PS in the blend solution is 95%, the solvent is o-DCB, the concentration of PM6 is 5 mg / mL –1 , and the concentration of PS is 10 mg / mL –1 . Spin at a speed of 2000 rpm. Place the spin-coated film on a hot plate and anneal at 150 °C for 30 min.

[0034] Step 3: Evaporate and deposit an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2 using an evaporation coater. The evaporation rate is 0.2 Å / s –1 , and the thickness is 40 nm.

[0035] Step 4: Prepare the source and drain electrodes on the organic semiconductor SII layer by thermal evaporation. The evaporated material is Au, the thickness is 40 nm, and the evaporation rate is 0.5 Å / s –1 . Use a mask to control the channel length to 300 μm and the channel width to 3 mm.

[0036] Step 5: Prepare an F4-TCNQ doping layer on the topmost layer of the device by thermal evaporation. The evaporation rate is 0.2 Å / s –1 , and the thickness is 5 nm.

[0037] Name the transistor using the materials of each layer. In this embodiment, the device is named PM6@PS / C12-BTBT / F4-TCNQ double-channel transistor.

[0038] As Figure 4 shown, use plasma etching technology and absorption spectroscopy to characterize the structure of the device. After plasma etching for 10 s, the absorption peak of PM6 (625 nm) disappears rapidly, indicating that PM6 aggregates on the top of the PM6@PS film to form the front channel layer.

[0039] As Figure 5 shown, PS / F4-TCNQ, PS / C12-BTBT / F4-TCNQ, PS / C12-BTBT / F4-TCNQ, and PM6@PS / C12-BTBT / F4-TCNQ films were prepared using the above method. Both the PM6@PS / C12-BTBT / F4-TCNQ film and the PS / C12-BTBT / F4-TCNQ film exhibit F4-TCNQ – peaks. While PM6@PS / F4-TCNQ only shows the F4-TCNQ peak and no F4-TCNQ –Peaks. Therefore, F4-TCNQ doped C12-BTBT, but did not dope PM6. The role of doping is to pre-fill the traps of C12-BTBT, enabling field-induced charges to fill both C12-BTBT and PM6 simultaneously, thereby facilitating charge transport in both channels.

[0040] As Figure 6 shown, the transistor was electrically tested using an Agilent Keysight B2902A precision source / measurement unit to obtain the output characteristics and transfer characteristics of the device, as Figure 6 shown in (a) below. The output curve exhibits an extended linear region, and in the low V D region, the curves corresponding to different gate voltages overlap. Specifically, as Figure 6 shown in (b) below, according to the transfer characteristics at V D =-5V, after the transistor is turned on, as V G increases, I D remains almost unchanged (I D ∝V G 0 ). As Figure 6 shown in (c) below, in the saturation region of the output curve, the source-drain current changes at equal intervals with V G . In terms of the transfer characteristics, when V D =-60V, there is a linear relationship between I D and V G (I D ∝V G 1 ).

[0041] Example 2 This example provides a method for fabricating a new-feature double-channel transistor, which is as follows: Step 1: Use doped silicon / silicon dioxide (Si / SiO2) as the substrate. The doped silicon serves as the gate of the new-feature double-channel transistor described in this application, and SiO2 serves as the dielectric layer with a thickness of 300 nm. The substrate was ultrasonically treated with water, acetone, and isopropanol in sequence, each for 10 minutes. The cleaned Si / SiO2 substrate was subjected to plasma etching, which was carried out under a gas pressure <20 Pa for 5 minutes. The etched Si / SiO2 was modified using a toluene solution of phenyltrichlorosilane, with a solution concentration of 5‰, a modification temperature of 90 °C, and a duration of 1.5 h.

[0042] Step 2: Spin-coat a blend solution of PDVT-10 and PS on the substrate modified in Step 1. The mass ratio of PS in the blend solution is 95%, the solvent is o-DCB, the concentration of PDVT-10 is 5 mg mL –1 , and the concentration of PS is 10 mg mL–1 , the spin coating speed is 3000 rpm. Place the spin-coated film on a hot plate and anneal it at 150 °C for 30 min.

[0043] Step 3, use an evaporation instrument to deposit an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2, with an evaporation rate of 0.2 Å / s –1 , and the thickness is 40 nm.

[0044] Step 4, fabricate the source and drain on the organic semiconductor SII layer by thermal evaporation. The deposited material is Au, with a thickness of 40 nm and an evaporation rate of 0.5 Å / s –1 , use a mask to control the channel length to be 300 μm and the channel width to be 3 mm.

[0045] Step 5, fabricate an F4-TCNQ doping layer on the topmost layer of the device by thermal evaporation, with an evaporation rate of 0.2 Å / s –1 , and the thickness is 5 nm.

[0046] Name the transistor using the materials of each layer. In this embodiment, the device is named PDVT-10@PS / C12-BTBT / F4-TCNQ double-channel transistor.

[0047] As Figure 7 shown, use an Agilent Keysight B2902A precision source / measurement unit to perform electrical tests on the transistor, and obtain the output characteristics and transfer characteristics of the device. As Figure 7 shown in (a), the output curve shows an extended linear region, and in the low V D region, the curves corresponding to different gate voltages overlap. Specifically, as Figure 7 shown in (b), according to the transfer characteristics at V D =-10 V, after the transistor is turned on, as V G increases, I D is almost unchanged (I D ∝V G 0 ). As Figure 7 shown in (c), the source-drain current in the saturation region of the output curve changes at equal intervals with V G . In terms of the transfer characteristics, when V D =-60 V, there is a linear relationship between I D and V G (I D ∝V G 1 ).

[0048] In addition, when programming the transistor, the threshold voltage of the device undergoes a reversible shift. This is because charges are stored in the insulating polymer layer PS, so the device exhibits non-volatility. Specifically, as Figure 8 shown, (a) is a schematic diagram of charge accumulation in the programming state and (b) is a diagram of non-volatile research of a double-channel transistor. Using a positive gate voltage / UV light pulse can shift the threshold voltage of the device in the positive voltage direction, and applying a negative gate voltage can restore the state. Using a negative gate voltage can shift the threshold voltage of the device in the negative voltage direction, and then applying UV light can erase the programmed state of the device. And during the programming process, the unconventional characteristics of the I D -V G of the device can be maintained.

[0049] Example 3 This example provides a method for fabricating a double-channel transistor with new characteristics, specifically as follows: Step 1, Use doped silicon / silicon dioxide (Si / SiO2) as the substrate, doped silicon as the gate of the double-channel transistor with new characteristics described in this application, and SiO2 as the dielectric layer with a thickness of 300 nm. The substrate is ultrasonically treated with water, acetone, and isopropanol in sequence, each for 10 min. The cleaned Si / SiO2 substrate is subjected to plasma etching treatment, which is carried out under a gas pressure of <0 Pa for 5 min. The etched Si / SiO2 is modified with a toluene solution of phenyltrichlorosilane, the solution concentration is 5‰, the modification temperature is 80 °C, and the duration is 2 h.

[0050] Step 2, Spin-coat a blend solution of PM6 and PS on the substrate modified in Step 1. The mass ratio of PS in the blend solution is 95%, the solvent is o-DCB, the concentration of PM6 is 5 mg mL –1 , and the concentration of PS is 10 mg mL –1 , and the spin-coating speed is 2000 rpm. The spin-coated film is placed on a hot stage and annealed at 150 °C for 30 min.

[0051] Step 3, Use an evaporation coater to deposit an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2, with an evaporation rate of 0.2 As –1 , and a thickness of 40 nm.

[0052] Step 4, Fabricate the source and drain on the organic semiconductor SII layer by thermal evaporation. The evaporated material is Au, with a thickness of 40 nm and an evaporation rate of 0.5 As –1 , and use a mask to control the channel length to be 300 μm and the channel width to be 3 mm.

[0053] In this example, no F4-TCNQ doping layer is deposited.

[0054] The transistor is named using the materials of each layer. In this embodiment, the device is named PM6@PS / C12-BTBT dual-channel transistor.

[0055] As Figure 9 shown, an Agilent Keysight B2902A precision source / measurement unit is used to perform electrical tests on the transistor. The transfer characteristics of the device at V D = -60V show that in the low V G region (region I), the transistor exhibits conventional characteristics, where I D ∝V G 2 . In the high V G region (region II), the transistor exhibits unconventional characteristics, i.e., I D ∝V G 1 . This is because in this embodiment, F4-TCNQ is not used to pre-fill the traps in C12-BTBT. Therefore, field-induced charges preferentially accumulate in C12-BTBT in the low gate voltage region, and only C12-BTBT serves as the charge transport channel, resulting in the conventional characteristics of the curve in the region I stage. This indicates that trap pre-filling caused by doping is crucial for achieving dual-channel transport.

[0056] Example 4 This embodiment provides a method for fabricating a new characteristic dual-channel transistor, which is as follows: Step 1: Purchase a dielectric layer 2 with a gate 1. The cleaned dielectric layer 2 is subjected to plasma etching and surface modification using organosilane to obtain an organosilane layer 3. Step 2: Spin-coat a blend solution of an insulating polymer and an organic semiconductor SI (PDVT-10 or PM6) on the organosilane layer 3 modified in Step 1. The mass ratio of the insulating polymer to the organic semiconductor SI is 4:1 to 19:1. The solvent of the blend solution is o-dichlorobenzene, and the concentration of the organic semiconductor SI is 5 to 8 mg mL –1 , and the spin-coating speed ranges from 1000 rpm to 3000 rpm. Then, anneal at 120 to 180 °C for 30 min to obtain a blend layer 4, forming a vertically phase-separated organic semiconductor SI layer 41 and an insulating polymer layer 42. Step 3: Then, prepare an organic semiconductor SII layer 5 (C8-BTBT or C12-BTBT) by evaporation deposition, with an evaporation rate of 0.1 to 0.4 As –1 , and a thickness of 40 to 100 nm. Step 4: Prepare the source electrode 6 and the drain electrode 7 by evaporation deposition. The evaporation material is gold, and the evaporation rate is 0.5 to 0.8 As –1, with a thickness of 40 - 60 nm; using a mask to control the channel length to be 1 - 300 μm and the channel width to be 3 - 5 mm; Step 5, prepare a doped layer 8 on the organic semiconductor SII layer 5 by evaporation method, with an evaporation rate of 0.1 - 0.4 As –1 , with a thickness of 3 - 8 nm, to obtain a novel characteristic double-channel transistor.

[0057] The applicant has also verified through experiments that the transistors obtained within the above ranges all have unconventional characteristics, and the devices exhibit non-volatility.

[0058] Comparative Example 1 Comparative Example 1 provides a transistor with conventional characteristics.

[0059] Step 1, use doped silicon / silicon dioxide (Si / SiO2) as the substrate, the thickness of SiO2 is 300 nm, and the doped silicon is used as the gate of the novel characteristic double-channel transistor described in this application. The substrate is ultrasonically treated with water, acetone, and isopropyl alcohol in sequence, each for 10 min. The cleaned Si / SiO2 substrate is subjected to plasma etching treatment, and the plasma etching is carried out under a gas pressure < 20 Pa for 5 min. The etched Si / SiO2 is modified with a toluene solution of phenyltrichlorosilane, the solution concentration is 5‰, the modification temperature is 80 °C, and the duration is 2 h.

[0060] Step 2, spin-coat a PM6 solution on the substrate modified in Step 1, the solvent is o-DCB, and the concentration is 5 mg mL –1 , and the spin-coating speed is 2000 rpm. The spin-coated film is placed on a hot plate and annealed at 150 °C for 30 min.

[0061] Step 3, use an evaporator to evaporate and prepare an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2, with an evaporation rate of 0.2 As –1 , and the thickness is 40 nm.

[0062] Step 4, prepare the source and drain on the organic semiconductor SII layer by thermal evaporation, the evaporated material is Au, the thickness is 40 nm, and the evaporation rate is 0.5 As –1 , use a mask to control the channel length to be 300 μm and the channel width to be 3 mm.

[0063] Name the transistor using the materials of each layer. In this comparative example, the device is named PM6 / C12-BTBT transistor.

[0064] As Figure 10 shown, use an Agilent Keysight B2902A precision source / measurement unit to perform electrical tests on the transistor, asFigure 10 As shown in (a), the output curve of the device exhibits conventional characteristics. As Figure 10 shown in (b) and (c), at V D = -60V, I D ∝V G 2 , this is because the organic semiconductor SI layer formed by PM6 is relatively thick, and the field-induced charges will directly accumulate at the PM6 / SiO2 interface. Therefore, there is only one channel for charge transport in the device, and the device exhibits conventional characteristics. Since there is no blending with an insulating polymer, the organic semiconductor SI layer formed by PM6 is relatively thick. Therefore, controlling the thickness of the organic semiconductor SI layer is one of the key factors for forming double-channel transport.

[0065] Comparative Example 2 Comparative Example 2 provides a transistor with conventional characteristics.

[0066] Step 1: Use doped silicon / silicon dioxide (Si / SiO2) as the substrate, doped silicon as the gate of the novel characteristic double-channel transistor described in this application, and SiO2 as the dielectric layer with a thickness of 300 nm. The substrate is ultrasonically treated with water, acetone, and isopropyl alcohol in sequence, each for 10 min. The cleaned Si / SiO2 substrate is subjected to plasma etching treatment, which is carried out under a gas pressure < 20 Pa for 5 min. The etched Si / SiO2 is modified with a toluene solution of phenyltrichlorosilane, with a solution concentration of 5‰, a modification temperature of 80 °C, and a duration of 2 h.

[0067] Step 2: Spin-coat a blend solution of PBTTT and PS on the substrate modified in Step 1. The mass ratio of PS in the blend solution is 95%, the solvent is o-DCB, the concentration of PBTTT is 5 mg mL –1 , and the concentration of PS is 10 mg mL –1 , with a spin-coating speed of 2000 rpm. The spin-coated film is placed on a hot plate and annealed at 150 °C for 30 min.

[0068] Step 3: Evaporate and deposit an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2 using an evaporation coater, with an evaporation rate of 0.2 As –1 , and a thickness of 40 nm.

[0069] Step 4: Prepare the source and drain on the organic semiconductor SII layer by thermal evaporation. The evaporated material is Au, with a thickness of 40 nm and an evaporation rate of 0.5 As –1 , and a mask plate is used to control the channel length to be 300 μm and the channel width to be 3 mm.

[0070] In this example, the F4-TCNQ dopant is not evaporated and deposited.

[0071] The transistor is named using the materials of each layer. In this comparative example, the device is named PBTTT@PS / C12-BTBT transistor.

[0072] As Figure 11 shown, an Agilent Keysight B2902A precision source / measurement unit is used to perform electrical tests on the transistor. As Figure 11 shown in (a) therein, the output curve of the device presents conventional characteristics. As Figure 11 shown in (b) therein, when V D = -10 V, there is a linear relationship between I D and V G . As Figure 11 shown in (c) therein, when V D = -60 V, I D ∝ V G 2 . This is because the HOMO energy level of PBTTT is relatively high, and the field-induced charges will directly accumulate in PBTTT. Therefore, there is only one channel for charge transport in the device, and the device exhibits conventional characteristics. This indicates that the HOMO energy level of the organic semiconductor SI layer cannot be too high, and controlling the relative positions of the HOMO energy levels of the organic semiconductor SI layer and the organic semiconductor SII layer (C12-BTBT) is the key factor for realizing double-channel transport.

[0073] Comparative Example 3 Comparative Example 3 provides a transistor with conventional characteristics.

[0074] Step 1: Use doped silicon / silicon dioxide (Si / SiO2) as the substrate, doped silicon as the gate of the novel characteristic double-channel transistor described in this application, and SiO2 as the dielectric layer with a thickness of 300 nm. The substrate is ultrasonically treated with water, acetone, and isopropanol in sequence, each for 10 min. The cleaned Si / SiO2 substrate is subjected to plasma etching treatment, which is carried out under a gas pressure < 20 Pa for 5 min. The etched Si / SiO2 is modified using a toluene solution of phenyltrichlorosilane, with a solution concentration of 5‰, a modification temperature of 80 °C, and a duration of 2 h.

[0075] Step 2: Spin-coat a blend solution of PCDTPT and PS on the substrate modified in Step 1. The mass ratio of PS in the blend solution is 95%, the solvent is o-DCB, the concentration of PM6 is 5 mg mL –1 , and the concentration of PS is 10 mg mL –1 , with a spin-coating speed of 2000 rpm. The spin-coated film is placed on a hot stage and annealed at 150 °C for 30 min Step 3: Use an evaporation coater to deposit an organic semiconductor SII layer (C12-BTBT) on the film obtained in Step 2, with an evaporation rate of 0.2 Å / s. –1 The thickness is 40 nm.

[0076] Step 4: Fabricate the source and drain on the organic semiconductor SII layer by thermal evaporation. The deposited material is Au, with a thickness of 40 nm and an evaporation rate of 0.5 Å / s. –1 Use a mask to control the channel length to be 300 μm and the channel width to be 3 mm.

[0077] In this example, no F4-TCNQ dopant is deposited.

[0078] Name the transistor using the materials of each layer. In this comparative example, the device is named PCDTPT@PS / C12-BTBT transistor.

[0079] As Figure 12 shown, use an Agilent Keysight B2902A precision source / measurement unit to perform electrical tests on the transistor. As Figure 12 shown in (a) therein, the output curve of the device shows conventional characteristics. As Figure 12 shown in (b) therein, at V D = -10 V, there is a linear relationship between I D and V G . As Figure 12 shown in (c) therein, at V D = -60 V, I D ∝V G 2 . This is because the HOMO energy level of PCDTPT is relatively high, and the field-induced charges will directly accumulate in PCDTPT. Therefore, there is only one channel for charge transport in the device, and the device shows conventional characteristics. This indicates that the HOMO energy level of the organic semiconductor SI layer cannot be too high, and controlling the relative positions of the HOMO energy levels of the organic semiconductor SI layer and the organic semiconductor SII layer (C12-BTBT) is the key factor for realizing double-channel transport.

[0080] The present application discloses a new - characteristic dual - channel transistor and a preparation method. The transistor includes a gate, a dielectric layer, an organosilane layer, a blend layer, and an organic semiconductor SII layer stacked in sequence from bottom to top. A doping layer is also vapor - deposited on the upper layer of the organic semiconductor SII layer, and source and drain electrodes are vapor - deposited above the organic semiconductor SII layer. The blend layer includes an organic semiconductor SI layer and an insulating polymer layer. The energy levels and mobilities of the organic semiconductor SI layer and the organic semiconductor SII layer are different, and they jointly serve as a channel layer for charge transport. The insulating polymer and the organic semiconductor SI are blended to prepare an ultrathin organic semiconductor SI layer through vertical phase separation. The insulating polymer also serves as a charge - storage layer to regulate the device characteristics. The organosilane layer is used for surface modification of the dielectric layer to induce vertical phase separation of the insulating polymer and the organic semiconductor SI. The doping layer is used to fill the trap states of the channel material and change the charge - transport energy level. The dual - channel transistor of the present application has unconventional electrical characteristics: (1) The output - characteristic curve has an extended linear region, and the curves under different gate voltages V G conditions are almost coincident within the linear - region range; (2) On the transfer - characteristic curve, when the source - drain voltage V D <V G –V T , I D does not change with V G ; when V D ≥V G –V T , I D has a linear relationship with V G ; (3) The working state of the device can be modulated through programming and erasing, and the device state has non - volatility.

[0081] The present application discloses an organic dual - channel transistor prepared from the same - type semiconductor. An organosilane layer and a blend layer are designed. The insulating polymer in the organosilane layer and the blend layer has the same group, resulting in a layered structure of the blend layer. Among them, the insulating polymer is distributed at the bottom layer as an electret, making the device have non - volatility. The organic semiconductor SI layer is distributed at the top layer as one of the channels. The organic semiconductor SI layer formed in this way has a very thin thickness, ensuring that charges can be transported in both the organic semiconductor SI layer and the organic semiconductor SII layer simultaneously, that is, the formation of a dual - channel. Because for an overly thick organic semiconductor SI layer, charges tend to accumulate at the bottom of the organic semiconductor SI layer under the action of the gate voltage, far away from the organic semiconductor SII layer, thus unable to form a dual - channel.

[0082] This application proposes the selection principles for the materials of the organic semiconductor SI layer and the organic semiconductor SII layer: the organic semiconductor SI layer is a polymer semiconductor, the organic semiconductor SII layer is a small molecule semiconductor, and the mobility of the organic semiconductor SII layer is higher than that of the organic semiconductor SI layer; the HOMO energy level of the organic semiconductor SI layer should be slightly higher than that of the organic semiconductor SII layer to ensure that charges can accumulate in both semiconductor layers simultaneously, forming a double channel; because if the HOMO energy level of the organic semiconductor SI layer is too high, charges tend to accumulate only in the organic semiconductor SI layer, and conversely, charges tend to accumulate in the high-mobility organic semiconductor SII layer, and both of these situations are not conducive to the formation of a double channel.

[0083] This application discloses the new characteristics of the double-channel transistor, and these new characteristics are different from those of the double-channel transistors in the existing patents: the output characteristic curve has an extended linear region, and the curves under different gate voltages V within the linear region range coincide; on the transfer characteristic curve, when the source-drain voltage V G conditions, the curve coincides; on the transfer characteristic curve, when the source-drain voltage V D < V G – V T , I D does not change with V G ; when V D ≥ V G – V T , I D has a linear relationship with V G , I D is the source-drain current, and V T is the threshold voltage; in addition, the device also exhibits non-volatility, which makes such devices have great potential application value in fields such as reconfigurable signal modulation.

[0084] The above has made a detailed description of the preferred embodiments of this application, but this application is not limited to the above embodiments. Within the knowledge scope of those of ordinary skill in the art, various changes can be made without departing from the purpose of this application.

[0085] Many other changes and modifications can be made without departing from the concept and scope of this application. It should be understood that this application is not limited to specific embodiments, and the scope of this application is defined by the appended claims.

Claims

1. A new feature double-channel transistor, characterized in that: It includes a gate (1), a dielectric layer (2), an organosilane layer (3), a blend layer (4), and an organic semiconductor SII layer (5) stacked in sequence from bottom to top. An anode (6) and a drain (7) are evaporated above the organic semiconductor SII layer (5); The blend layer (4) is prepared by blending an insulating polymer and an organic semiconductor SI through vertical phase separation, forming a vertically phase-separated organic semiconductor SI layer (41) and an insulating polymer layer (42). The organic semiconductor SI layer (41) is close to the organic semiconductor SII layer (5), and the insulating polymer layer (42) is close to the organosilane layer (3); The mobility of the organic semiconductor SII layer (5) is higher than that of the organic semiconductor SI layer (41), and the highest occupied molecular orbital energy level of the organic semiconductor SII layer (5) is lower than that of the organic semiconductor SI layer (41); The materials of the organic semiconductor SI layer (41) and the organic semiconductor SII layer (5) are both p-type semiconductors; The material of the organosilane layer (3) and the material of the insulating polymer layer (42) have the same group, and the same group is selected from one of a benzene ring, a methoxy group, an ethoxy group, or a halogen atom.

2. The novel feature dual-channel transistor according to claim 1, wherein: The material of the organosilane layer (3) is selected from one of phenyltrichlorosilane, octadecyltrichlorosilane, trimethoxysilane, or triethoxysilane; the material of the organic semiconductor SI layer (41) is selected from PDVT-10 or PM6; the material of the insulating polymer layer (42) is selected from one of PS, PVN, PMMA, or PαMS; the material of the organic semiconductor SII layer (5) is selected from an organic small molecule C8-BTBT or C12-BTBT.

3. A novel feature dual-channel transistor according to claim 1, characterized in that: A doping layer (8) is further evaporated above the organic semiconductor SII layer (5). The doping material of the doping layer (8) is selected from one of F4-TCNQ, F6-TCNNQ, or F2-HCNQ, and the lowest unoccupied molecular orbital energy level of the doping layer (8) is lower than the defect energy level of the organic semiconductor SII layer (5).

4. A novel feature dual-channel transistor according to claim 3, characterized in that: The thickness of the doping layer (8) is 3 - 8 nm.

5. A novel characteristic dual-channel transistor according to claim 1, wherein: The mobility range of the material of the organic semiconductor SI layer (41) is 0.01 cm –2 V –1 s –1 ~1 cm –2 V –1 s –1 , and the mobility range of the material of the organic semiconductor SII layer (5) is 2.5 cm –2 V –1 s –1 ~20 cm –2 V –1 s –1 .

6. A novel feature dual-channel transistor according to claim 1, characterized in that: The thickness of the organic semiconductor SII layer (5) is 40 - 100 nm, and the thickness of the blend layer (4) is 40 - 100 nm, where the thickness of the organic semiconductor SI layer (41) is 2 - 8 nm.

7. A method for preparing a new feature dual-channel transistor, characterized in that: It includes the following steps: Step 1, purchase a dielectric layer (2) with a gate (1), perform plasma etching on the cleaned dielectric layer (2), and perform surface modification with an organosilane to obtain an organosilane layer (3); Step 2, spin-coat a blend solution of an insulating polymer and an organic semiconductor SI on the organosilane layer (3) modified in Step 1. The mass ratio of the insulating polymer to the organic semiconductor SI is 4:1 to 19:

1. The solvent of the blend solution is orthodichlorobenzene, and the concentration of the organic semiconductor SI is 5 to 8 mg mL –1 , with a spin-coating speed range of 1000 rpm to 3000 rpm. Then anneal at 120 to 180 °C for 30 min to obtain a blend layer (4), forming a vertically phase-separated organic semiconductor SI layer (41) and an insulating polymer layer (42); Step 3, then prepare the organic semiconductor SII layer (5) by evaporation coating method, with an evaporation rate of 0.1~0.4 Å / s –1 , and the thickness is 40~100 nm; Step 4, the source electrode (6) and the drain electrode (7) are prepared by evaporation coating. The evaporation coating material is gold, and the evaporation rate is 0.5 - 0.8 Å / s. –1 , and the thickness is 40 - 60 nm; a mask plate is used to control the channel length to be 1 - 300 μm and the channel width to be 3 - 5 mm; Step 5, a doping layer (8) is prepared on the organic semiconductor SII layer (5) by evaporation method, and the evaporation rate is 0.1~0.4 Å / s –1 , with a thickness of 3~8 nm, to obtain a new characteristic double-channel transistor; The output characteristic curve of the new feature double-channel transistor has an extended linear region, and the curves under different gate voltages V within the linear region overlap; on the transfer characteristic curve, when the source-drain voltage V G conditions, the curves coincide; when the source-drain voltage V D < V G – V T , I D does not change with V G ; when V D ≥ V G – V T , I D has a linear relationship with V G , and I D is the source-drain current, and V T is the threshold voltage.

8. The manufacturing method of a new characteristic dual-channel transistor according to claim 7, characterized in that: Specifically, in Step 1: the dielectric layer (2) is ultrasonically treated with water, acetone, and isopropanol in sequence for 10 - 15 min. The cleaned dielectric layer (2) is subjected to plasma etching, and the plasma etching is carried out under a gas pressure < 20 Pa for a treatment time of 5 - 10 min. The etched dielectric layer (2) is modified with a toluene solution of an organosilane, the solution concentration is 5‰, the modification temperature is 80 - 90 °C, and the duration is 1.5 - 3 h.

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