Endpoint detection for backside metal thickness control

Abstract

A method of controlling the thickness of a layer of material applied to a surface, where the surface has disposed therein one or more bodies of another material that is significantly harder than the first mentioned material, before applying the layer of material to the surface, the one or more bodies of the other material are substantially less than the first mentioned material, and before applying the layer of material to the surface, the one or more bodies of the other material are substantially less than the first mentioned material. One or more bodies of the other material are disposed on the surface, the material layer has a sufficient thickness to cover the one or more bodies of the other material when applied to the surface, and then the thickness of the material layer is mechanically reduced, such as by polishing, to expose at least a portion of the one or more bodies of the other material.

Description

[0001] Cross - reference to related patents and patent applications

[0002] This application relates to the technologies disclosed in U.S. Patent No. 8,617,927, authorized on December 31, 2013, U.S. Patent No. 9,214,404, authorized on December 15, 2015, and U.S. Patent No. 10,998,273, authorized on May 4, 2021, the disclosures of which are incorporated herein by reference.

[0003] This application also relates to the technologies disclosed in U.S. Patent Application Serial No. 17 / 361,186, entitled "Singulation Process for Chiplets", filed on June 28, 2021, the disclosure of which is incorporated herein by reference.

[0004] This application claims the priority of U.S. Patent Application No. 18 / 081,394, entitled "End - Point Detection for Backside Metal Thickness Control", filed on December 14, 2022, the disclosure of which is incorporated herein by reference.

[0005] Statement regarding federally sponsored research or development

[0006] None. Technical field

[0007] Semiconductor chip manufacturing: Process control for controlling the thickness of metal (or other) layers. Background art

[0008] In the art, there is a need to fabricate device wafers or chips including integrated circuits that have accommodation cavities through the wafer or through the chip (which cavities can be filled during fabrication with small components sometimes referred to as "chiplets"), which is addressed in the above - mentioned U.S. patents. These patents disclose metal - embedded chip components for microwave integrated circuit (MECAMIC) devices and processes, and teach embedding microelectronic transistor chiplets at the wafer level into a device wafer (which can also be referred to as an interposer) or a chip (which can also be referred to as an interposer), where the device wafer or chip can have pre - fabricated interconnects and integrated circuits, including for example passive components. This allows for faster fabrication of the resulting chips or devices at a lower cost, and for extending transistor technology to circuits without the cost and cycle - time burden of technologies, especially when compared to the technologies and components used to fabricate the device wafer or chip that houses one or more chiplets, and the chiplets utilize one or more more expensive fabrication technologies and components on a surface - area basis.

[0009] The small chips may include GaN or other semiconductor chemical devices or even passive devices (such as resistors, capacitors) on a substrate (such as an SiC substrate). Such small chips can be used to fabricate the MECAMIC devices described in the aforementioned U.S. patents or other applications. The device wafer or chip 20 embedded with the small chip 10 can be fabricated by a manufacturing process that is less costly than the manufacturing process used for the small chips. Thus, the resulting integrated circuit or chip 20 can be mainly made of a first material (such as a dielectric material), and the transistor small chip 10 can be mainly formed of a second material (such as a III / V material system material like GaN), and the second material is much more expensive to obtain and utilize than the first material. The resulting interposer chip, device, or wafer 20 generally contains significantly more of the first material than the second material and is desired to have many of the benefits provided by III / V material system transistors, but the manufacturing cost is closer to that of silicon-based technology.

[0010] The MECAMIC technology relies on integrating the aforementioned transistor small chips into the volume of the device or interposer wafer via a backside electroformed metal anchoring method. The backside metal provides structural mechanical integrity for the combination of the small chips and the device / interposer wafer and for DC and RF electrical grounding.

[0011] The circuit design in MECAMIC can use microstrip for matching networks and interconnections on 50 μm thick SiC (or 60 μm thick high-resistivity silicon). The substrate thickness is critical because it sets the characteristic impedance of the transmission line, and those skilled in the art will recognize that it should be close to 50 Ω.

[0012] The backside metal thickness is also critical. However, there is currently no known way to in-situ measure its thickness during the process.

[0013] This disclosure focuses on the design, fabrication, and integration of small chips for "in-situ endpoint detection" of backside thickness control for MECAMIC. Embedded in the wafer, these small chips provide unique process control but are not part of the actual product circuit (only seen at the wafer level). The small chips also provide "polish stop" capability and backside alignment capability (required for creating backside scribe lanes).

[0014] This disclosure provides accurate control of the backside metal thickness through an in-situ small chip integration method (instead of inaccurate timed removal). This disclosure can also provide a way to significantly slow down the polishing of the small chips ("polish stop") and can provide alignment marks for subsequent frontside and backside processing steps. Summary of the Invention

[0015] In one aspect, the present invention provides an apparatus that includes an electronic component having a first thickness, and one or more end-detection chips disposed in a cavity within the electronic component, the one or more end-detection chips having a second thickness greater than the first thickness and a first hardness, the electronic component being at least partially covered with a material having a hardness less than the first hardness of the end-detection chips, and the thickness of the material being limited by the thickness of the end-detection chips.

[0016] According to an embodiment of the present disclosure, the electronic component has additional cavities therein, in which transistor chips are disposed.

[0017] According to an embodiment of the present invention, the number of additional cavities exceeds the number of cavities in which the end-detection chips are disposed by at least 10 times.

[0018] According to an embodiment of the present disclosure, the electronic component has at least a single cavity in which the end-detection chips are disposed and a plurality of additional cavities in which transistor chips are disposed, the electronic component being mainly formed of a first material, and the transistor chips being mainly formed of a second material, the obtaining and utilization of the second material being more expensive than that of the first material.

[0019] According to an embodiment of the present invention, the material of the one or more end-detection chips is SiC, and the material having a hardness less than the hardness of the end-detection chips is selected from the group including Cu and Al.

[0020] According to an embodiment of the present invention, the one or more end-detection chips have one or more alignment marks formed on at least one of their end faces.

[0021] In another aspect, the present invention provides an apparatus that includes an electronic component having an inner surface, and one or more end-detection chips disposed in a cavity within the electronic component, the one or more end-detection chips protruding from the inner surface and having a first hardness, the electronic component being at least partially covered with a material having a hardness less than the first hardness of the end-detection chips, and the thickness of the material being limited by the distance by which the one or more end-detection chips protrude from the first surface.

[0022] According to an embodiment of the present disclosure, the electronic component has additional cavities therein, in which transistor chips are disposed.

[0023] According to an embodiment of the present invention, the number of additional cavities far exceeds the number of cavities in which the end-detection chips are disposed.

[0024] According to an embodiment of the present invention, the electronic component has at least a single cavity in which the end-detection chips are disposed and a plurality of additional cavities in which transistor chips are disposed.

[0025] According to an embodiment of the present invention, the material of one or more end point detection chips is SiC, and the material having a hardness less than that of the end point detection chips is selected from the group including Cu and Al.

[0026] According to an embodiment of the present invention, one or more end point detection chips have one or more alignment marks formed on at least one end face thereof.

[0027] In yet another aspect, the present invention provides a method for controlling the thickness of a layer of a material applied to a surface, wherein the surface has one or more bodies of another material disposed therein, the another material being harder than the first-mentioned material. Before applying the layer of the first-mentioned material to the surface, the one or more bodies of the another material are disposed on the surface. The layer of the first-mentioned material has a sufficient thickness when applied to the surface to cover the one or more bodies of the another material, and then the thickness of the layer of the first-mentioned material is mechanically reduced, for example, by polishing, to expose at least a portion of the one or more bodies of the another material.

[0028] According to an embodiment of the present invention, the surface is the surface of an electronic component, and the electronic component has one or more cavities therein for receiving the one or more bodies of the another material, and at least a portion of the one or more bodies of the another material protrudes from the surface.

[0029] According to an embodiment of the present invention, the method further includes forming the electronic component as one of an array of electronic components, and at least a portion of each of the one or more bodies of the another material includes one or more alignment marks formed on at least one end face of the body of the another material, and the one or more alignments are used to achieve cutting the array of electronic components into individual electronic components.

[0030] Other embodiments of the present specification relate to a method for controlling the thickness of a material layer applied to a surface, wherein the surface has one or more bodies of another material disposed therein, the another material being significantly harder than the first-mentioned material. Before applying the material layer to the surface, the one or more bodies of the another material are disposed on the surface. The material layer has a sufficient thickness when applied to the surface to cover the one or more bodies of the another material, and then the thickness of the material layer is mechanically reduced, for example, by polishing, to expose at least a portion of the one or more bodies of the another material. Description of the Drawings

[0031] Figures 1a to 1fDepicts the MECA / MECAMIC technology taught by U.S. Patent No. 10,998,273, authorized on May 4, 2021.

[0032] Figures 2a to 2c Shows additional details of step 5 as referenced Figures 1a to 1f described.

[0033] Figures 3a to 3e Depicts an embodiment of the subject matter of the presently disclosed technology.

[0034] Figures 4a to 4c Is a close-up view corresponding to Figures 3a to 3e an embodiment of the technology of the present disclosure, where Figure 4a is Figure 3c a detail of a part of Figure 4b is Figure 3d a detail of a part of Figure 4c and is Figure 3e a detail of a part of

[0035] Figure 5 Presents a process flow block diagram.

[0036] Figure 6 Depicts alignment marks etched in the die and that will be visible after completion of metal polishing.

[0037] Figure 7 Shows an example of a MECAMIC interposer layout wafer 20.

[0038] Figure 8 Depicts an example of a MECAMIC interposer layout scale (10 mm) and one example of a "die end detection" die 11. This will give a die every 10 mm on the wafer, but a denser pattern can also be easily achieved. DETAILED DESCRIPTION

[0039] The following description is presented to enable a person having ordinary skill in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications and various uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Thus, the invention is not intended to be limited to the embodiments presented, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0040] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the present invention.

[0041] The reader's attention is directed to (i) all papers and documents that are simultaneously filed with this specification and that are open to public inspection of this specification (the contents of all such papers and documents are hereby incorporated by reference) and (ii) all papers and documents that are incorporated by reference in some other manner (but not physically filed with this specification).

[0042] Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose. Thus, unless otherwise expressly stated, each feature disclosed is only an example of a series of general equivalent or similar features.

[0043] Furthermore, no element in a claim that does not expressly state "means for" performing a specified function or "step for" performing a particular function should be construed as a "means" or "step" clause as specified in paragraph 6 of Section 112 of Title 35, United States Code. In particular, the use of "step" or "act" in the claims herein is not intended to invoke the provisions of paragraph 6 of Section 112 of Title 35, United States Code.

[0044] The MECAMIC (Metal-Embedded Chiplet Assembly for Microwave Integrated Circuits) process enables rapid prototyping and low-cost manufacturing of RF integrated circuits. The manufacturing method was previously described in U.S. Patent No. 10,998,273, which was issued on May 4, 2021, and is depicted by Figures 1a to 1f depicted.

[0045] Figures 1a to 1f The MECAMIC technology taught by U.S. Patent No. 10,998,273 is described. The transistor chiplet 10 is integrated into the interposer wafer 20, which may be formed of a semiconductor dielectric material such as BCB, SiO2, SiN, etc. The cross-hatched regions represent metal, preferably commonly used in semiconductor manufacturing. The interposer wafer 20 features a through-substrate chip / die cavity 22. See Figure 1a and Figure 1b Steps 1 and 2 shown. The chiplet 10 is preferably formed on a temporary carrier wafer 12 covered with an adhesive ( Figure 1c Step 3 shown), flip-chip bonded into the cavity 22 (see Figure 1dStep 4) as shown, and then mechanically locked into place in the inserted wafer 20 by dorsal metal plating and polishing (see Figure 1e Step 5) as shown. As will be explained, according to the inventive aspects of the present disclosure, Step 5 is improved.

[0046] After Step 5, preferably Step 6 occurs, where the adhesive-covered temporary carrier wafer 12 is removed (the interposer wafer 20 with the embedded transistor die 10 is detached from the adhesive-covered temporary carrier wafer 12), and additional interconnect metals (air bridges) and microstrip transmission lines (not shown) are added as needed, for example, to complete the circuit of the interposer 20. The interposer 20 is generally formed of a plurality of passive components (such as capacitors and / or resistors) and a plurality of transistor dies 10. For purposes of illustration and explanation, only two passive components and one die 10 are shown in Figures 1a to 1f .

[0047] Generally, a large number of interposer chips are made into a wafer simultaneously. For purposes of illustration, only one interposer chip with one embedded transistor die 10 is shown, and it should be understood that generally a large number of interposer chips will be manufactured simultaneously with the wafer, and then the wafer is diced into individual interposer chips 20, and the individual chips 20 can carry many transistor dies 10.

[0048] In contrast to more expensive semiconductor technologies, the interposer 20 is generally formed using relatively inexpensive semiconductor processing technologies such as using a silicon or SiC substrate, but more expensive semiconductor technologies can be used if desired. On the other hand, the die 10 is generally formed using relatively more expensive semiconductor processing technologies, such as using III / V materials. Thus, Figures 1a to 1f 's MECA / MECAMIC technology allows for the use of relatively expensive semiconductor processing technologies to form transistor dies (for example) that are embedded in a wafer formed using a cheaper manufacturing technology.

[0049] The interposer wafer, which generally carries many interposer chips (see Figure 7 and Figure 8 ), mates with the transistor dies 10 disposed on the wafer or on the tape. This allows for the use of relatively inexpensive manufacturing technologies to fabricate the interposer wafer, while the transistor dies 10, which generally only account for a small portion of the total area of the interposer chip, utilize more expensive manufacturing technologies.

[0050] A single interposer chip is shown in the drawings, and it should be understood that generally a large number of interposer chips will be manufactured simultaneously on a wafer. See Figure 7 and Figure 8 , which show the wafer ( Figure 7 ) and the individual interposer chips ( Figure 8)。In the following description, the term wafer is used, but for ease of illustration, only a single interposer chip is depicted. Additionally, the interposer chip (wafer) in the figures has a much simpler circuit design than the Figure 8 interposer chip or Figure 7 the wafer, in order to more easily depict and describe the novel aspects of the technology described herein.

[0051] The interposer wafer 20 is prefabricated with passive components (step 1) and is thinned and etched for cavity fabrication (step 2). In parallel, the transistor die 10 is placed face - down on a temporary carrier wafer. Optionally, the die 10 can be tape - mounted as described in U.S. Patent Application Serial No. 17 / 361,186, titled "Singulation Process for Chiplets", filed on June 28, 2021.

[0052] Before forming the back - side metal 26 (step 5), preferably by a combination of sputtering metal, electroplating, and polishing, the MECAMIC interposer wafer 20 is placed and bonded (face - down) to the wafer carrying the transistor die 10 (step 4). The back - side metal enables 1) mechanical locking of the die in the interposer wafer, 2) back - side grounding for DC and RF operation of the resulting chip, and 3) thermal management. After removing the reconstructed wafer with the integrated die from the carrier, the top - side interconnects that connect the die to the wafer are preferably fabricated using conventional micro - manufacturing processes.

[0053] Figure 2b and Figure 2c shows additional details of step 5 above, where step 5 is divided into two steps 5a (see Figure 2b ) and 5b (see Figure 2c ). Figure 2a shows the previous step 4, which was also described above with respect to Figure 1d . According to the process described with reference to Figures 1a to 2c , the transistor die 10 and the MECAMIC interposer wafer 20 have approximately the same thickness (50 μm), but sometimes it is desirable to use a thicker interposer wafer (this can occur if a high - resistivity Si interposer wafer is used instead of SiC). The high - resistivity Si wafer can be approximately 60 μm thick to maintain the same characteristic impedance of the microstrip transmission line on the top - side of the interposer as that made of SiC. Of course, there may be other reasons why the transistor die 10 has a different thickness from the interposer wafer 20. As will now be described, this thickness difference (60 μm vs. 50 μm) presents manufacturing difficulties.

[0054] After bonding the die 10 to the temporary carrier wafer 12 using an adhesive, the interposer wafer 20 with the prefabricated cavity 22 and vias is also aligned and placed face - down on the temporary carrier wafer 12 (see Figure 2a step 4 thereof (which also appears as Figure 1d ) in the above discussion). In the MECAMIC process, the die 10 and the interposer wafer 20 preferably have the same thickness, but this is not necessarily required as explained in the previous paragraph. Subsequently, metal is sputtered on the stack and metal plating is performed. Due to the topography of the embedded die and vias, the thick metal needs to be polished back to 5 to 10 μm (see Figure 2c step 5b) shown). However, currently, there is no in - situ technique to accurately measure the metal thickness during polishing. In addition, with the planarized back - side metal, further alignment of layers (such as using scribe lanes) is not possible.

[0055] As shown in step 5 (see Figure 5 and Figure 2b ), the back - side metal 26 is over - plated and has some topography due to the vias 23 and the cavity 22 being filled with the back - side metal 26. Therefore, polishing is typically performed to make the thickness of the back - side metal 26 more uniform.

[0056] The thickness of the back - side metal 26 is important, especially as the diameter of the wafer is scaled up. For example, if the thickness or stress of the back - side metal 26 is too large, wafer warping can be observed. Therefore, it is preferred to polish (commonly referred to as planarize) the thickness of the back - side metal 26 to less than 10 μm.

[0057] However, according to the process described in U.S. Patent No. 10,998,273, which does not describe a way to accurately control the thickness of the back - side metal 26 during processing, it is difficult to control the thickness and uniformity of the back - side metal 26 after planarization. In addition, planarization makes it impossible to subsequently align the photolithography layers. As an example, metal is typically removed in the scribe lanes while aligning these metals with the front - side circuit. This cannot be done according to the process described in the aforementioned U.S. patent because there is no visible reference pattern on the back - side of the interposer wafer.

[0058] To address these issues, the use of a "process - control" die (alternatively referred to herein as an "endpoint - detection" die 11) will now be described. The above process steps 3, 4, and 5 are replaced with the new versions described below. The die 11 is preferably formed of a material such as SiC, and thus, in the disclosed embodiments, is not used as a die for traditional circuit implementation, but the possibility that the die 11 may include circuitry is not excluded from the scope of possibilities.

[0059] Figure 3a and Figure 3b show fromFigure 3a Start and then continue to Figure 3b the process flow. The "process control" or "endpoint detection" die 11 is preferably 5 to 10 μm thicker (higher) than the MECAMIC interposer wafer 20. First, the transistor die 10 is bonded, and then the die 11 is bonded face down (see Figure 3a new step 3). Of course, this can be reversed, first bonding die 11 and then die 10. Next, the MECAMIC interposer wafer 20 is also bonded (see new steps 4a to 4b and Figures 3b to 3c ). Note that the interposer 20 includes additional cavities 23 for accommodating these new dies 11. As Figure 3c shown, depicting new step 4b, the die 11 projects from the back side of the interposer wafer 20 by a height equal to (or slightly greater than) the desired thickness of the metal layer 26 to be deposited. Then, the back-side metal layer 26 is preferably deposited by sputtering metal and electroplating metal, similar to the original method described in the above-mentioned U.S. patent and shown herein as new step 5a (see Figure 3d ).

[0060] After depositing the metal 26, the metal 26 is polished with the "process control" or "endpoint detection" die 11, thereby providing an in-situ endpoint detection surface, as shown in new step 5b (see Figure 3e ). This effectively means that the "process control" or "endpoint detection" die 11 provides a way to precisely control the thickness of the deposited back-side metal 26. When the "process control" die becomes visible, the polishing step is complete, as shown in new step 5b as Figure 3e shown. Since the polishing of the "process control" die is not as fast as that of the deposited metal layer (for example, if copper is used as the metal for the metal layer 26, it is 100 times faster than SiC polishing if SiC is the material selected for the die 11), the die 11 not only becomes visible, but also due to their relatively high hardness, they also provide an "effective polishing stop" to prevent significant over-polishing of the metal layer 26. The metal 26 is preferably a metal selected from the group including Cu and Al, but it should be understood that other metals (or metal alloys) or even non-metals can also be used as long as the hardness of the selected material is less than the hardness of the "endpoint detection" die 11.

[0061] The die 11 is used for back-side metal 26 endpoint detection and is preferably also used for back-side alignment. These dies are 5 to 10 μm thicker than the interposer wafer 20. After metal plating (new step 5a), the back-side metal 26 is polished all the way back to these dies 11, and thus the "endpoint detection" label sometimes used for these dies in this article. This process precisely controls the thickness of the back-side metal 26 to provide more uniformity and thickness control, thereby also reducing wafer warping.

[0062] Figure 5 The process using the "process control" or "endpoint detection" die 11 is shown in block diagram format.

[0063] Figure 6 A close-up view of the "process control" or "endpoint detection" die 11 as seen through the backside metal 26 plating and polishing process is shown. In this figure, the alignment features preferably include one or more recessed (possibly etched) alignment marks. Before mounting the die 11 as Figure 3a shown, marks are preferably formed on the upper and lower surfaces of the die 11. The die 11 should be harder than the material selected for the metal 26. The backside recessed marks are filled with the metal 26 during the plating process but are visible after polishing, thereby facilitating the dicing of the wafer 20 into individual interposer chips.

[0064] Figure 7 and Figure 8 shows how the die 11 is inserted into the wafer layout. Figure 7 shows a wafer with multiple (seventy-two in this case) individual interposer chips, while Figure 8 shows an individual chip with one (in this embodiment) "process control" or "endpoint detection" die 11 and multiple transistor dies 10. The size of the "process control" or "endpoint detection" die 11 can be approximately 300x300 μm, but can be smaller (e.g., 100x100 μm) or larger. Preferably, one "process control" die is placed per chip mask (per 10 mm in this embodiment). However, the density can be increased or decreased based on the process margin.

[0065] The present invention has now been described in accordance with the requirements of the patent statutes, and those skilled in the art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications can be made without departing from the scope and spirit of the present invention disclosed herein.

[0066] The foregoing detailed description of the exemplary and preferred embodiments has been presented for purposes of illustration and disclosure in accordance with legal requirements. It is not intended to be exhaustive, nor is it intended to limit the invention to the precise forms described, but rather to enable other persons skilled in the art to understand how the invention may be applied to a particular use or to a specific implementation. The possibility of modifications and variations will be apparent to persons skilled in the art. The description of the exemplary embodiments is not intended to be limiting, and the exemplary embodiments may include tolerances, feature sizes, specific operating conditions, engineering specifications, etc., and may vary or change the prior art between implementations, and no limitation should be implied therefrom. The applicant has made this disclosure in view of the current state of the art, but also contemplates advancements, and future adaptations may take those advancements into account, that is, in view of the state of the art at that time. The scope of the invention is intended to be defined by the written claims and the equivalents applicable thereto. Unless expressly stated otherwise, the recitation of a claim element in the singular is not intended to mean "one and only one." Moreover, elements, components, or steps in the present disclosure, whether or not expressly recited in the claims, are not intended to be dedicated to the public. No claim element herein shall be construed under the provisions of 35 U.S.C. § 112, as effective on the filing date, unless the element is expressly recited using the phrase "means for"; and no method or process step herein shall be construed under those provisions unless the step is expressly recited using the phrase "comprising."

[0067] Modifications, additions, or omissions may be made to the systems, devices, and methods described herein without departing from the scope of the invention. The components of the systems and devices may be integrated or separated. Additionally, the operations of the systems and devices may be performed by more, fewer, or other components. The method may include more, fewer, or other steps. Further, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

Claims

1. A device, the device includes an electronic component having a first thickness, one or more end-point detection chips disposed in a cavity within the electronic component, the one or more end-point detection chips having a first hardness and a second thickness greater than the first thickness, the electronic component being at least partially covered with a material, the hardness of the material being less than the first hardness of the end-point detection chips, and the thickness of the material being limited by the thickness of the end-point detection chips.

2. The device according to claim 1, wherein, The electronic component has additional cavities, and transistor chips are disposed in the additional cavities.

3. The device according to claim 2, wherein, The number of the additional cavities exceeds the number of the cavities in which the end-point detection chips are disposed by at least 10 times.

4. The device according to claim 2, wherein, The electronic component has at least a single cavity in which the end-point detection chips are disposed and a plurality of additional cavities in which the transistor chips are disposed, the electronic component being mainly formed of a first material, and the transistor chips being mainly formed of a second material, the second material being more expensive to obtain and utilize than the first material.

5. The apparatus according to claim 1, wherein The material of the one or more end-point detection chips is SiC, and the material having a hardness less than the hardness of the end-point detection chips is selected from the group including Cu and Al.

6. The device according to claim 1, wherein, The one or more end-point detection chips have one or more alignment marks formed on at least one of their end faces.

7. A device, the device includes an electronic component having an inner surface, one or more end-point detection chips disposed in a cavity within the electronic component, the one or more end-point detection chips protruding from the inner surface and having a first hardness, the electronic component being at least partially covered with a material, the hardness of the material being less than the first hardness of the end-point detection chips, and the thickness of the material being limited by the distance by which the one or more end-point detection chips protrude from the first surface.

8. The device according to claim 7, wherein, The electronic component has additional cavities, and transistor chips are disposed in the additional cavities.

9. The apparatus according to claim 8, wherein, The number of the additional cavities far exceeds the number of the cavities in which the end-point detection chips are disposed.

10. The apparatus according to claim 8, wherein, The electronic component has at least a single cavity in which the end-point detection chips are disposed and a plurality of additional cavities in which the transistor chips are disposed.

11. The apparatus according to claim 7, wherein, The material of the one or more end-point detection chips is SiC, and the material having a hardness less than the hardness of the end-point detection chips is selected from the group including Cu and Al.

12. The apparatus according to claim 7, wherein, The one or more end-point detection chips have one or more alignment marks formed on at least one of their end faces.

13. A method of controlling the thickness of a layer of a material applied to a surface, wherein the surface has one or more bodies of another material disposed therein, the another material being harder than the first-mentioned material, before applying the layer of the first-mentioned material to the surface, the one or more bodies of the another material are disposed on the surface, the layer of the first-mentioned material has a sufficient thickness when applied to the surface to cover the one or more bodies of the another material, and then the thickness of the layer of the first-mentioned material is mechanically reduced, such as by polishing, to expose at least a portion of the one or more bodies of the another material.

14. The method according to claim 13, wherein, The surface is the surface of an electronic component, which has one or more cavities for receiving the one or more bodies of the other material therein, and at least a part of the one or more bodies of the other material protrudes from the surface.

15. The method according to claim 14, further comprising forming the electronic component as one of an array of electronic components, and wherein at least a part of the one or more bodies of the other material each comprises one or more alignment marks formed on at least one end face of the body of the other material, and the one or more alignment marks are used to effect cutting the array of electronic components into the individual electronic components.

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