Three-dimensional memory devices including tilt

Abstract

A memory device includes: an alternating stack including insulating layers and conductive layers and tapered sidewalls extending laterally along a first horizontal direction and inclined along a second horizontal direction; a memory opening fill structure extending through each layer within the alternating stack and including a memory element and a vertical semiconductor channel; a cavity in the alternating stack, the cavity laterally bounded by the tapered sidewall, and having a bottom surface including stepped surfaces of at least some of the conductive layers; an insulating liner disposed over the tapered sidewall in the cavity; and a conductive strip adjacent to a respective one of the stepped surfaces at the bottom surface of the cavity, extending in the cavity over the insulating liner and the tapered sidewall, and including a respective topmost portion located over a topmost surface of the alternating stack.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 450,115, filed on August 15, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE INCLUDING INCLINED WORD LINE CONTACT STRIPS AND METHODS OF FORMING THE SAME", and the entire content of this U.S. Non - Provisional Application is incorporated herein by reference for all purposes. This U.S. Non - Provisional Application claims the priority of U.S. Provisional Application No. 63 / 506,902, filed on June 8, 2023. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including inclined word line contact strips and methods of forming the same. Background art

[0004] A three - dimensional memory device including a three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", IEDM Proc. (2001), pages 33 - 36. Summary of the invention

[0005] According to an embodiment of the present disclosure, a memory device includes: an alternating stack including insulating layers and conductive layers interleaved along a vertical direction, wherein the alternating stack includes tapered sidewalls that extend laterally along a first horizontal direction and are inclined along a second horizontal direction perpendicular to the first horizontal direction; memory openings extending vertically through each layer within the alternating stack; a memory opening filling structure located within the memory openings and including a respective vertical stack of memory elements and respective vertical semiconductor channels; a cavity within the alternating stack, the cavity being laterally bounded along a first side by the tapered sidewalls and having a bottom surface including a stepped surface of at least some of the conductive layers; an insulating liner located within the cavity above the tapered sidewalls; and a conductive bar adjacent to a respective one of the stepped surfaces at the bottom surface of the cavity, extending within the cavity above the insulating liner and the tapered sidewalls, and including a respective top portion located above the topmost surface of the alternating stack.

[0006] According to another aspect of the present disclosure, a method of forming a memory device includes: forming an alternating stack of insulating layers and sacrificial material layers interleaved along a vertical direction; forming a cavity within the alternating stack such that a stepped surface of the sacrificial material layer of the alternating stack is exposed at the bottom surface of the cavity; forming an insulating liner above the stepped surface, above the tapered sidewalls of the alternating stack, and above the topmost layer of the alternating stack; forming an elongate opening through the insulating liner, wherein a segment of the stepped surface is exposed through the elongate opening through the insulating liner; forming a sacrificial liner on the segment of the stepped surface and above the elongate opening such that the sacrificial liner includes a top portion located above the alternating stack; forming a dielectric filling structure above the sacrificial liner; forming memory openings extending at least vertically through the alternating stack; forming a memory opening filling structure within the memory openings, wherein each memory opening filling structure within the memory opening filling structure includes a respective vertical stack of memory elements and respective vertical semiconductor channels; forming an array of lateral isolation trenches and isolation cavities through the alternating stack, wherein the lateral isolation trenches and the isolation cavity array divide the sacrificial liner into sacrificial liner strips laterally spaced apart from each other; and partially replacing the remaining portions of the sacrificial material layer and the sacrificial liner strips with a conductive material, wherein conductive layers are formed in volumes from which the remaining portions of the sacrificial material layer are removed and conductive bars are formed in volumes from which the sacrificial liner strips are removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view of an exemplary semiconductor die including a plurality of three-dimensional memory array regions according to an embodiment of the present disclosure.

[0008] Figures 2A to 2D These are various views of an exemplary structure after forming an optional semiconductor device, an optional underlying dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, a first insulating layer and a first alternating layer stack of a sacrificial material layer, and a first cavity, according to an embodiment of the present disclosure. Figure 2B This is a top view. Figure 2A This is a vertical cross-sectional view along the Figure 2B vertical plane A-A'. Figure 2C This is a vertical cross-sectional view along the Figure 2B vertical plane C-C'. Figure 2D This is a vertical cross-sectional view along the Figure 2B vertical plane D-D'. Figures 2A to 2D The illustrated region of Figure 1 corresponds to the region M1 in

[0009] Figures 3A to 3E These are various views of an exemplary structure after deposition and patterning of a first insulating liner, according to an embodiment of the present disclosure. Figure 3B This is a top view. Figure 3A This is a vertical cross-sectional view along the Figure 3B vertical plane A-A'. Figure 3C This is a vertical cross-sectional view along the Figure 3B vertical plane C-C'. Figure 3D This is a vertical cross-sectional view along the Figure 3B vertical plane D-D'. Figure 3E This is a vertical cross-sectional view along the Figure 3B vertical plane E-E'.

[0010] Figures 4A to 4E These are various views of an exemplary structure after deposition and patterning of a first sacrificial liner, according to an embodiment of the present disclosure. Figure 4B This is a top view. Figure 4A This is a vertical cross-sectional view along the Figure 4B vertical plane A-A'. Figure 4C This is a vertical cross-sectional view along the Figure 4B vertical plane C-C'. Figure 4D This is a vertical cross-sectional view along the Figure 4B vertical plane D-D'. Figure 4E This is a vertical cross-sectional view along the Figure 4B vertical plane E-E'.

[0011] Figures 5A to 5E These are various views of an exemplary structure after forming a first insulating cap layer and a first dielectric fill structure, according to an embodiment of the present disclosure. Figure 5B This is a top view.

[0012] Figure 5A This is a vertical cross-sectional view along theFigure 5B Vertical sectional view of the vertical plane A-A'. Figure 5C is along Figure 5B Vertical sectional view of the vertical plane C-C'. Figure 5D is along Figure 5B Vertical sectional view of the vertical plane D-D'. Figure 5E is along Figure 5B Vertical sectional view of the vertical plane E-E'.

[0013] Figures 6A to 6E are various views of an exemplary structure after forming a first-tier memory opening and a first-tier support opening according to an embodiment of the present disclosure. Figure 6B is a top view. Figure 6A is along Figure 6B Vertical sectional view of the vertical plane A-A'. Figure 6C is along Figure 6B Vertical sectional view of the vertical plane C-C'. Figure 6D is along Figure 6B Vertical sectional view of the vertical plane D-D'. Figure 6E is along Figure 6B Vertical sectional view of the vertical plane E-E'.

[0014] Figures 7A to 7E are various views of an exemplary structure after forming a first-tier sacrificial opening filling structure according to an embodiment of the present disclosure. Figure 7B is a top view. Figure 7A is along Figure 7B Vertical sectional view of the vertical plane A-A'. Figure 7C is along Figure 7B Vertical sectional view of the vertical plane C-C'. Figure 7D is along Figure 7B Vertical sectional view of the vertical plane D-D'. Figure 7E is along Figure 7B Vertical sectional view of the vertical plane E-E'.

[0015] Figures 8A to 8E are various views of an exemplary structure after forming a second alternating layer stack of a second insulating layer and a second sacrificial material layer and a second cavity according to an embodiment of the present disclosure. Figure 8B is a top view. Figure 8A is along Figure 8B Vertical sectional view of the vertical plane A-A'. Figure 8C is along Figure 8B Vertical sectional view of the vertical plane C-C'. Figure 8D is along Figure 8B Vertical sectional view of the vertical plane D-D'. Figure 8E is along Figure 8BVertical sectional view of the vertical plane E-E'.

[0016] Figures 9A to 9E Are various views of an exemplary structure after deposition and patterning of a second insulating layer according to an embodiment of the present disclosure. Figure 9B Is a top view. Figure 9A Is along Figure 9B Vertical sectional view of the vertical plane A-A'. Figure 9C Is along Figure 9B Vertical sectional view of the vertical plane C-C'. Figure 9D Is along Figure 9B Vertical sectional view of the vertical plane D-D'. Figure 9E Is along Figure 9B Vertical sectional view of the vertical plane E-E'.

[0017] Figures 10A to 10E Are various views of an exemplary structure after deposition and patterning of a second sacrificial layer according to an embodiment of the present disclosure. Figure 10B Is a top view. Figure 10A Is along Figure 10B Vertical sectional view of the vertical plane A-A'. Figure 10C Is along Figure 10B Vertical sectional view of the vertical plane C-C'. Figure 10D Is along Figure 10B Vertical sectional view of the vertical plane D-D'. Figure 10E Is along Figure 10B Vertical sectional view of the vertical plane E-E'.

[0018] Figures 11A to 11E Are various views of an exemplary structure after forming a second insulating capping layer and a second dielectric fill structure according to an embodiment of the present disclosure. Figure 11B Is a top view. Figure 11A Is along Figure 11B Vertical sectional view of the vertical plane A-A'. Figure 11C Is along Figure 11B Vertical sectional view of the vertical plane C-C'. Figure 11D Is along Figure 11B Vertical sectional view of the vertical plane D-D'. Figure 11E Is along Figure 11B Vertical sectional view of the vertical plane E-E'.

[0019] Figures 12A to 12E Are various views of an exemplary structure after forming an inter-level memory opening and an inter-level support opening according to an embodiment of the present disclosure. Figure 12B Is a top view. Figure 12A Is along Figure 12B Vertical sectional view of the vertical plane A-A'. Figure 12Cis a vertical sectional view along the Figure 12B vertical plane C-C'. Figure 12D is a vertical sectional view along the Figure 12B vertical plane D-D'. Figure 12E is a vertical sectional view along the Figure 12B vertical plane E-E'.

[0020] Figures 13A to 13E are various views of an exemplary structure after forming a sacrificial opening fill structure according to an embodiment of the present disclosure. Figure 13B is a top view. Figure 13A is a vertical sectional view along the Figure 13B vertical plane A-A'. Figure 13C is a vertical sectional view along the Figure 13B vertical plane C-C'. Figure 13D is a vertical sectional view along the Figure 13B vertical plane D-D'. Figure 13E is a vertical sectional view along the Figure 13B vertical plane E-E'.

[0021] Figures 14A to 14E are various views of an exemplary structure after replacing the sacrificial support opening fill structure with a support pillar structure according to an embodiment of the present disclosure. Figure 14B is a top view. Figure 14A is a vertical sectional view along the Figure 14B vertical plane A-A'. Figure 14C is a vertical sectional view along the Figure 14B vertical plane C-C'. Figure 14D is a vertical sectional view along the Figure 14B vertical plane D-D'. Figure 14E is a vertical sectional view along the Figure 14B vertical plane E-E'.

[0022] Figures 15A to 15E are various views of an exemplary structure after removing the sacrificial memory opening fill structure according to an embodiment of the present disclosure. Figure 15B is a top view. Figure 15A is a vertical sectional view along the Figure 15B vertical plane A-A'. Figure 15C is a vertical sectional view along the Figure 15B vertical plane C-C'. Figure 15D is a vertical sectional view along the Figure 15B vertical plane D-D'. Figure 15E is a vertical sectional view along the Figure 15B vertical plane E-E'.

[0023] Figures 16A to 16Fis a sequential vertical cross-section of an inter-level memory opening during the formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0024] Figures 17A to 17G are various views of an exemplary structure after the formation of a memory opening fill structure according to an embodiment of the present disclosure. Figure 17B is a top view. Figure 17A is along Figure 17B vertical cross-section of the vertical plane A-A'. Figure 17C is along Figure 17B vertical cross-section of the vertical plane C-C'. Figure 17D is along Figure 17B vertical cross-section of the vertical plane D-D'. Figure 17E is along Figure 17B vertical cross-section of the vertical plane E-E'. Figure 17F is along Figure 17B vertical cross-section of the vertical plane F-F'. Figure 17G is along Figure 17B vertical cross-section of the vertical plane G-G'.

[0025] Figures 18A to 18I are various views of an exemplary structure after the formation of a lateral isolation trench and an isolation cavity according to an embodiment of the present disclosure. Figure 18B is a top view. Figure 18A is along Figure 18B vertical cross-section of the vertical plane A-A'. Figure 18C is along Figure 18B vertical cross-section of the vertical plane C-C'. Figure 18D is along Figure 18B vertical cross-section of the vertical plane D-D'. Figure 18E is along Figure 18B vertical cross-section of the vertical plane E-E'. Figure 18F is along Figure 18B vertical cross-section of the vertical plane F-F'. Figure 18G is along Figure 18B vertical cross-section of the vertical plane G-G'. Figure 18H is along Figure 18B vertical cross-section of the vertical plane H-H'. Figure 18I is along Figure 18B vertical cross-section of the vertical plane I-I'.

[0026] Figures 19A to 19I are various views of an exemplary structure after the formation of a laterally extending cavity according to an embodiment of the present disclosure. Figure 19B is a top view. Figure 19A is along Figure 19B vertical cross-section of the vertical plane A-A'. Figure 19Cis a vertical sectional view along the Figure 19B vertical plane C-C'. Figure 19D is a vertical sectional view along the Figure 19B vertical plane D-D'. Figure 19E is a vertical sectional view along the Figure 19B vertical plane E-E'. Figure 19F is a vertical sectional view along the Figure 19B vertical plane F-F'. Figure 19G is a vertical sectional view along the Figure 19B vertical plane G-G'. Figure 19H is a vertical sectional view along the Figure 19B vertical plane H-H'. Figure 19I is a vertical sectional view along the Figure 19B vertical plane I-I'.

[0027] Figures 20A to 20I are various views of an exemplary structure after forming a conductive layer, conductive bars, and isolation cavities according to an embodiment of the present disclosure. Figure 20B is a top view. Figure 20A is a vertical sectional view along the Figure 20B vertical plane A-A'. Figure 20C is a vertical sectional view along the Figure 20B vertical plane C-C'. Figure 20D is a vertical sectional view along the Figure 20B vertical plane D-D'. Figure 20E is a vertical sectional view along the Figure 20B vertical plane E-E'. Figure 20F is a vertical sectional view along the Figure 20B vertical plane F-F'. Figure 20G is a vertical sectional view along the Figure 20B vertical plane G-G'. Figure 20H is a vertical sectional view along the Figure 20B vertical plane H-H'. Figure 20I is a vertical sectional view along the Figure 20B vertical plane I-I'.

[0028] Figures 21A to 21I are various views of an exemplary structure after forming a lateral isolation trench filling structure and a lateral isolation structure according to an embodiment of the present disclosure. Figure 21B is a top view. Figure 21A is a vertical sectional view along the Figure 21B vertical plane A-A'. Figure 21C is a vertical sectional view along the Figure 21B vertical plane C-C'. Figure 21D is a vertical sectional view along the Figure 21B vertical plane D-D'. Figure 21E is a vertical sectional view along theFigure 21B Vertical cross-section of the vertical plane E-E'. Figure 21F It is along Figure 21B Vertical cross-section of the vertical plane F-F'. Figure 21G It is along Figure 21B Vertical cross-section of the vertical plane G-G'. Figure 21H It is along Figure 21B Vertical cross-section of the vertical plane H-H'. Figure 21I It is along Figure 21B Vertical cross-section of the vertical plane I-I'.

[0029] Figure 22A is a vertical cross-sectional view of a first alternative configuration of an exemplary structure after forming lateral isolation trench-fill structures and lateral isolation structures according to an embodiment of the present disclosure. Figure 22B yes Figure 22A A top view of a first alternative configuration of an exemplary structure of FIG. The vertical plane AA' is Figure 22A cutting plane.

[0030] Figure 23A is a vertical cross-sectional view of a second alternative configuration of the exemplary structure after forming lateral isolation trench-fill structures and lateral isolation structures according to an embodiment of the present disclosure. Figure 23B yes Figure 23A A top view of a second alternative configuration of the exemplary structure of FIG. The vertical plane AA' is Figure 23A cutting plane.

[0031] Figure 24A is a vertical cross-sectional view of a third alternative configuration of the exemplary structure after forming lateral isolation trench-fill structures and lateral isolation structures according to an embodiment of the present disclosure. Figure 24B yes Figure 24A A top view of a third alternative configuration of the exemplary structure of FIG. The vertical plane AA' is Figure 24A cutting plane.

[0032] Figure 25A is a vertical cross-sectional view of a fourth alternative configuration of the exemplary structure after forming lateral isolation trench-fill structures and lateral isolation structures according to an embodiment of the present disclosure. Figure 25B yes Figure 25A A top view of a fourth alternative configuration of the exemplary structure of FIG. The vertical plane AA' is Figure 25A cutting plane.

[0033] Figure 26A is a vertical cross-sectional view of a fifth alternative configuration of the exemplary structure after forming lateral isolation trench-fill structures and lateral isolation structures according to an embodiment of the present disclosure. Figure 26B yes Figure 26AA top view of a fifth alternative configuration of the exemplary structure of FIG. The vertical plane AA' is Figure 26A cutting plane.

[0034] Figures 27A to 27E are various views of an exemplary structure after forming a drain select level isolation structure according to an embodiment of the present disclosure. Figure 27B It is a top view. Figure 27A It is along Figure 27B Vertical cross-section of the vertical plane A-A'. Figure 27C It is along Figure 27B Vertical cross-section of the vertical plane C-C'. Figure 27D It is along Figure 27B Vertical cross-section of the vertical plane D-D'. Figure 27E It is along Figure 27B Vertical cross-section of the vertical plane E-E'.

[0035] Figures 28A to 28G are various views of an exemplary structure after forming a contact-level dielectric layer and various metal via structures according to embodiments of the present disclosure. Figure 28B It is a top view. Figure 28A It is along Figure 28B Vertical cross-section of the vertical plane A-A'. Figure 28C It is along Figure 28B Vertical cross-section of the vertical plane C-C'. Figure 28D It is along Figure 28B Vertical cross-section of the vertical plane D-D'. Figure 28E It is along Figure 28B Vertical cross-section of the vertical plane E-E'. Figure 28F is a cutaway perspective view of a portion of an exemplary structure. Figure 28G yes Figure 28B of Figure 1 A vertical cross-sectional view in region M2 of FIG. DETAILED DESCRIPTION

[0036] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device including an inclined word line contact strip located above a tapered sidewall of a well exposing a word line step and a method of forming the same, and various aspects of the three-dimensional memory device are now described in detail.

[0037] The drawings are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be replicated unless otherwise expressly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first," "second," and "third" are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0038] Like reference numerals denote like or similar elements. Unless otherwise indicated, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise indicated, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly, these two elements are "separated" from each other or "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or a "work-in-progress" structure refers to an instantaneous structure in which the shape or composition of at least one component is subsequently modified.

[0039] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or the extent of the layer may be less than the extent of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the first continuous structure. For example, a layer may be located between the top surface and the bottom surface of the first continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the first continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0040] As used herein, if a second surface is above or below a first surface and there is a vertical or substantially vertical plane including the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that extends straight along a direction deviating from the vertical direction by less than 5 degrees. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0041] As used herein, a "memory level" or "memory array level" refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of an array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through the memory level.

[0042] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 - 5 S / m to 1.0 S / m in the absence of electrical dopants and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with electrical dopants. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material (i.e., provide a conductivity greater than 1.0×10 5 S / m) when formed into a crystalline material or when converted into a crystalline material by an annealing process (e.g., from an initial amorphous state). A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material having a concentration of electrical dopants (i.e., p-type dopants and / or n-type dopants) that provides a conductivity in the range of 1.0×10 - 5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semi-conductive or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements are made under standard conditions.

[0043] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips that are fully bonded, for example, through flip-chip bonding or another chip-to-chip bonding method. A package or a chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or a chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operations can be executed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be executed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0044] Reference Figure 1 , an exemplary semiconductor die 1000 according to an embodiment of the present disclosure is illustrated. The exemplary semiconductor die 1000 includes multiple three-dimensional memory array regions and multiple contact regions. The first exemplary semiconductor die 1000 may include multiple planes, and each of these planes includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart through corresponding contact regions 200. Generally speaking, the semiconductor die 1000 may include a single plane or multiple planes. The total number of planes in the semiconductor die 1000 can be selected based on the performance requirements for the semiconductor die 1000. A pair of memory array regions 100 in a plane may be laterally spaced apart along a first horizontal direction hd1 (the first horizontal direction may be the word line direction). For example, each pair of memory array regions 100 in a plane may include a first memory array region 100A and a second memory array region 100B that are laterally spaced apart through a contact region 200 along the first horizontal direction hd1. A second horizontal direction hd2 (which may be the bit line direction) may be perpendicular to the first horizontal direction hd1. Various embodiments of the present disclosure to be described below can be employed to fabricate Figure 1 the exemplary semiconductor die 1000.

[0045] Reference Figures 2A to 2D, which illustrates an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 8, which includes a substrate semiconductor layer 9. The substrate 8 can be a single-crystalline silicon wafer, a silicon-on-insulator (SOI) substrate, or an insulating (e.g., glass or quartz) substrate. The substrate semiconductor layer 9 can be a single-crystalline semiconductor material layer, such as a single-crystalline silicon layer epitaxially grown on a silicon wafer or an SOI substrate, or a doped well in an upper portion of a silicon wafer or an SOI substrate. A semiconductor device 720 can be formed on the top surface of the substrate semiconductor layer 9. For example, the semiconductor device 720 can include field-effect transistors, resistors, capacitors, diodes, and / or various other semiconductor devices known in the art. In one embodiment, the semiconductor device 720 can include peripheral (i.e., driver) circuits for controlling the operation of a three-dimensional memory array to be formed thereabove subsequently. A metal interconnect structure embedded in a dielectric material layer can be formed above the semiconductor device. The metal interconnect structure is referred to herein as a lower-level metal interconnect structure 780, and the dielectric material layer is referred to herein as a lower-level dielectric material layer 760. The lower-level metal interconnect structure 780 is electrically connected to various nodes of the semiconductor device 720 and can include metal wire structures and metal via structures located at various levels of the lower-level dielectric material layer 760.

[0046] A semiconductor material layer 110 can be formed on the top surface of the lower-level dielectric material layer 760. The semiconductor material layer 110 can be single-crystalline or polycrystalline and can be formed by layer transfer from a source substrate (such as a single-crystalline silicon layer including a buried hydrogen implantation layer), or can be formed by deposition of a semiconductor material (which can be a polycrystalline semiconductor material, such as polysilicon).

[0047] A first alternating stack of a first insulating layer 132 and a first sacrificial material layer 142 can be formed on the semiconductor material layer 110. As used herein, an alternating stack refers to a sequence of multiple instances of a first element and multiple instances of a second element, which are arranged such that instances of the second element are located between each pair of vertically adjacent instances of the first element, and instances of the first element are located between each pair of vertically adjacent instances of the second element. Thus, instances of the first material layer and instances of the second material layer are interleaved within the alternating stack.

[0048] The first insulating layer 132 may comprise and / or may consist essentially of a first material. The first sacrificial material layer 142 may comprise a second material different from the first material and / or may consist essentially of the second material. Each of the first insulating layers 132 extends continuously over the entire area of the substrate 8 and may have a uniform thickness throughout. Each of the first sacrificial material layers 142 extends continuously over the entire area of the substrate 8 and may have a uniform thickness throughout. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0049] The second material of the first sacrificial material layer 142 is a first-level sacrificial material that can be selectively removed relative to the first material of the first insulating layer 132. As used herein, if a removal process removes the first material at a rate of at least twice the removal rate of the second material, the removal of the first material is "selective" "with respect to" the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The second material of the first sacrificial material layer 142 can subsequently be replaced with conductive electrodes, which can be used as, for example, control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0050] Each of the first insulating layers 132 may have a first thickness, which may be in the range of 15 nm to 60 nm, but smaller and larger thicknesses may also be employed. Each of the first sacrificial material layers 142 may have a second thickness, which may be in the range of 15 nm to 60 nm, but smaller and larger thicknesses may also be employed. The total number of repetitions of a pair of the first insulating layer 132 and the first sacrificial material layer 142 in the first alternating stack (132, 142) may be in the range of 16 to 1024 (such as 64 to 512), but smaller and larger numbers may also be employed.

[0051] In an alternative embodiment, the semiconductor device 720, the lower metal interconnect structure 780, and the lower dielectric material layer 760 may be positioned adjacent to the first alternating stack (132, 142) on top of the substrate 8 instead of being positioned below the first alternating stack (132, 142). In yet another alternative embodiment, the semiconductor device 720, the lower metal interconnect structure 780, and the lower dielectric material layer 760 may be omitted and not formed on top of the substrate 8. Instead, the semiconductor device 720 of the peripheral (i.e., driver) circuit may be formed on a separate substrate and then bonded on top of the three-dimensional memory device. Optionally, in the case where the substrate 8 is later removed and the top source contact layer is formed on the exposed surface of the memory device, the semiconductor material layer 110 may also be omitted, or the semiconductor material layer may be modified to be part of a lateral source contact (e.g., a direct band contact) formed later under the alternating stack.

[0052] In the case where a plurality of hierarchical structures are formed on top of the substrate 8, the first insulating layer 132 may be a first subset of the insulating layer 32 formed on top of the substrate 8, and the first sacrificial material layer 142 may be a first subset of the sacrificial material layer 42 formed on top of the substrate 8.

[0053] A plurality of stepped surfaces S may be simultaneously formed in the contact region 200 by patterning the first alternating stack (132, 142). In one embodiment, the pattern of the stepped surfaces S may be repeated periodically along the second horizontal direction hd2. In this case, the cell pattern may be formed within the cell area, and the cell pattern may be repeated along the second horizontal direction hd2 such that the lateral dimension of the cell pattern along the second horizontal direction hd2 is the same as the periodicity of the repetition of the cell pattern along the second horizontal direction hd2. The area of each cell pattern is referred to herein as the repeating unit RU.

[0054] In one embodiment, a hard mask layer (not shown), such as a metal or dielectric mask material layer, may be formed on top of the first alternating stack (132, 142) and may be patterned to form a plurality of rectangular openings. The area of the openings in the hard mask layer corresponds to the area where a cavity 169 including a stepped bottom surface is to be formed subsequently. Each opening through the hard mask layer may be rectangular and may have a pair of sides parallel to the first horizontal direction (e.g., the word line direction) hd1 and a pair of sides parallel to the second horizontal direction (e.g., the bit line direction) hd2. The rectangular openings through the hard mask layer may be arranged along the second horizontal direction hd2 and may or may not be alternately staggered along the first horizontal direction hd1.

[0055] A trimable mask layer (not shown) may be applied over the alternating stack. The trimable mask layer may include a trimable photoresist layer that may be controllably trimmed by a timed ashing process. The trimable mask layer may be patterned with an initial pattern such that the segment of each rectangular opening in the hard mask layer closest to the memory array region 100 is not masked by the trimable mask layer, while the remainder of each rectangular opening is covered by the trimable mask layer. For example, the trimable mask layer may have a rectangular shape with straight edges parallel to the second horizontal direction hd2 such that the straight edges are located over the vertical steps of the corresponding stepped surface S closest to one of the memory array regions 100.

[0056] A stepped surface S may be formed in the region of the rectangular openings in the hard mask layer by iteratively performing a set of layer patterning process steps. The set of layer patterning process steps includes: an anisotropic etching process that etches unmasked portions of a pair of first insulating layers 132 and a first sacrificial material layer 142; and a mask trimming process in which the trimable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 100. A final anisotropic etching process may be performed after the last mask trimming process, and the trimable mask layer may be removed, for example, by ashing. The hard mask layer may be removed selectively to the material of the first alternating stack (132, 142) by an isotropic etching process such as a wet etching process. Alternatively, any other suitable process may be used to form the stepped surface.

[0057] A first cavity 169 having a corresponding stepped bottom surface may be formed in each region of the rectangular openings in the hard mask layer. Each first cavity 169 may include a steep wall region in which a first end wall EW1 of the first alternating stack (32, 42) extends from the bottommost first sacrificial material layer 142 of the first alternating stack (132, 142) to the topmost layer of the first alternating stack (132, 142). The first end wall EW1 may taper (i.e., be inclined) at an angle of 1 degree to 30 degrees along a first horizontal direction hd1 with respect to the vertical direction orthogonal to the top surface of the substrate. Each first cavity 169 has a stepped bottom surface. The stepped bottom surface of each cavity 169 extends laterally along the first horizontal direction hd1 and is located below the volume of the void of the first cavity 169. Generally, the stepped surface S may be formed by patterning the first alternating stack (132, 142) in each contact region 200 that is located between a corresponding first memory array region 100A and a second memory array region 100B.

[0058] Generally speaking, each first cavity 169 may have a stepped surface S including vertically extending surface segments that are interleaved with horizontally extending surface segments forming the bottom surface of the first cavity 169. Additionally, each first cavity 169 may include a pair of first tapered (e.g., inclined) sidewalls TS1 that are parallel to a first horizontal direction hd1, laterally spaced from each other along a second horizontal direction hd2, and have respective stepped bottom ends adjacent to the corresponding stepped perimeters of the stepped bottom surface. The first tapered sidewalls TS1 may taper (i.e., incline) at an angle of 5 degrees to 45 degrees relative to the vertical direction. The lateral distance along the second horizontal direction hd2 between the pair of first tapered sidewalls TS1 is the width of the corresponding first cavity 169, and this width increases with the vertical distance from the substrate 8.

[0059] Reference Figures 3A to 3E , the first insulating liner 160 may be conformally deposited over the underlying structure. The first insulating liner 160 includes an insulating material such as silicon oxide. The material of the first insulating liner 160 is different from the material of the first sacrificial material layer 142. The first insulating liner 160 is deposited over the stepped surface S of the first alternating stack (132, 142), over each first tapered sidewall TS1 of the first alternating stack (132, 142), and over the topmost layer of the first alternating stack (132, 142). The thickness of the first insulating liner 160 may be in the range of 50 nm to 200 nm (such as 100 nm to 150 nm), but smaller and larger thicknesses may also be employed.

[0060] A photoresist layer (not illustrated) may be formed over the first insulating liner 160 and may be lithographically patterned to form an elongate opening, such as a rectangular opening, that spans an intermediate portion of the stepped bottom surface of the corresponding first cavity 169. In one embodiment, the width of the rectangular opening along the second horizontal direction hd2 is less than the width of the bottommost horizontal surface of the stepped bottom surface. In one embodiment, each horizontal surface segment of the stepped bottom surface may have two horizontal surface segments that are not covered by the patterned photoresist layer and are laterally spaced along the second horizontal direction hd2. An etch process may be performed to etch the unmasked portions of the first insulating liner 160. The etch process may include an isotropic etch process or an anisotropic etch process. An elongate opening through the first insulating liner 160 is formed within the region of each first cavity 169. Segments of the stepped surface S are exposed through the elongate opening through the first insulating liner 160 underlying the first cavity that is present within the volume of the corresponding first cavity 169.

[0061] In one embodiment, the elongate opening through the first insulating liner 160 extends laterally along a first horizontal direction hd1 and may have a uniform width along a second horizontal direction hd2. In one embodiment, each first insulating liner 160 includes a first horizontally extending portion located above the first alternating stack (132, 142), and a plurality of tapered vertically extending portions located above respective first tapered sidewalls TS1. In one embodiment, each first insulating liner 160 includes a plurality of second horizontally extending portions located above the bottom surface of a respective first cavity 169 within an array of first cavities 169. A pair of second horizontally extending portions of the first insulating liner 160 may contact segments of the respective top surface of the first sacrificial material layer 142 and may be laterally spaced from each other by a rectangular region of the opening through the first insulating liner 160.

[0062] Reference Figures 4A to 4E , the first sacrificial liner material may be conformally deposited over the first insulating liner 160 and may subsequently be patterned to form the first sacrificial liner 182. The first sacrificial liner material includes a material that may subsequently be selectively removed with respect to the materials of the first insulating layer 132 and the first insulating liner 160. In one embodiment, the first sacrificial liner material may be the same as the first level sacrificial material of the first sacrificial material layer 142. In one embodiment, the first sacrificial liner 182 may comprise or may consist essentially of silicon nitride. The thickness of each first sacrificial liner 182 may be in the range of 10 nm to 50 nm (such as 15 nm to 30 nm), although smaller and larger thicknesses may also be employed.

[0063] Within the region of each repeating unit RU, the first sacrificial liner 182 may be formed such that the overall formed physical exposed sidewalls of the first sacrificial liner 182 are above the horizontal plane including the topmost surface of the first alternating stack (132, 142). In other words, the end portions of the first sacrificial liner 182 extend along the second horizontal direction hd2 above the tapered sidewalls TS1 and above the top of the first alternating stack (132, 142). Accordingly, the length of the first sacrificial liner 182 along the second horizontal direction hd2 may be longer than the length of the underlying first cavity 169 along the second horizontal direction hd2. The length of the first sacrificial liner 182 along the first horizontal direction hd1 may be the same as, shorter than, or longer than the length of the underlying first cavity 169 along the first horizontal direction hd1. The first cavity 169 is present within the volume laterally enclosed by the first sacrificial liner 182. The first sacrificial liner 182 may be formed directly on the physically exposed portion of the stepped surface S of the first alternating stack (132, 142) such that each first sacrificial layer 142 includes a respective horizontal top surface segment HS1 that contacts a respective bottom surface segment BP1 of the first sacrificial liner 182. As Figure 4CAs shown, the first sacrificial liner 182 includes a horizontally extending top portion TP1 that is located above the first alternating stack (132, 142) and above the horizontally extending top portion of the first insulating liner 160. In one embodiment, the first insulating liner 160 contacts the entirety of a pair of first tapered sidewalls TS1 and a first end wall EW1, and the first sacrificial liner 182 is spaced apart from the pair of first tapered sidewalls TS1 and the first end wall EW1 by the first insulating liner 160.

[0064] Referring Figures 5A to 5E , a first dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) can be deposited over the first sacrificial liner 182 and the first alternating stack (132, 142) to fill the first cavity 169. A planarization process (such as a chemical mechanical polishing process) can be performed to remove portions of the first dielectric fill material above a horizontal plane that includes the topmost surface of the first sacrificial liner 182. The first sacrificial liner 182 can be used as an endpoint detection structure and / or as a planarization stop structure. Each remaining portion of the first dielectric fill material that fills the corresponding first cavity 169 constitutes a first dielectric fill structure 165. The continuous remaining portion of the first dielectric fill material that is above the top surface of the horizontally extending portion of the first insulating liner 160 and above the first alternating stack (132, 142) constitutes a first insulating capping layer 170. Thus, a first hierarchical structure is formed over the semiconductor material layer 110. The first hierarchical structure includes all material portions that are above the semiconductor material layer 110 at this processing step.

[0065] Referring Figures 6A to 6E , a first etch mask layer (not shown) can be formed over the first insulating capping layer 170 and the first dielectric fill structure 165 and can be lithographically patterned to form various discrete openings therein. A first anisotropic etch process can be performed to transfer the pattern of the discrete openings in the first etch mask layer through the first insulating capping layer 170, the first alternating stack (132, 142), and the first dielectric fill structure 165. Various openings can be formed through the first insulating capping layer 170, the first alternating stack (132, 142), and the first dielectric fill structure 165. The various openings can include a first hierarchical memory opening 149 formed in the memory array region 100 and a first hierarchical support opening 119 formed in the contact region 200. Each of the first hierarchical memory opening 149 and the first hierarchical support opening 119 can vertically extend through the first alternating stack (132, 142) and into the semiconductor material layer 110.

[0066] In one embodiment, the memory array region 100 may be laterally spaced apart from the contact region 300 along a first horizontal direction hd1. The first-level memory openings 149 may include multiple rows of first-level memory openings 149 that are arranged along the first horizontal direction hd1 and are laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd2. Each region of the memory array region 100 located within the repeating unit RU includes a corresponding two-dimensional array of first-level memory openings 149 that are arranged as a cluster. Adjacent clusters of the first-level memory openings 149 may be laterally spaced apart along the second horizontal direction hd2.

[0067] In one embodiment, the first-level support openings 119 in the contact region 200 may be arranged as a two-dimensional periodic array of first-level support openings 119 within a respective one of the repeating units RU. In one embodiment, each two-dimensional periodic array of the first-level support openings 119 may be a corresponding rectangular periodic array of the first-level support openings 119.

[0068] In one embodiment, the first-level support openings 119 in the contact region 200 may extend along the second horizontal direction hd2. In another embodiment, the first-level support openings 119 in the contact region 200 may have a circular horizontal cross-section. In one embodiment, multiple columns of the first-level support openings 119 arranged along the second horizontal direction hd2 may cut through corresponding vertically extending straight surface segments of the stepped bottom surface of the first alternating stack (132, 142). The vertically extending straight surface segments may be perpendicular to the first horizontal direction hd1.

[0069] Reference Figures 7A to 7E optionally, an etch stop layer (not shown) and a first sacrificial fill material may be deposited in the first-level memory openings 149 and the first-level support openings 129. The optional etch stop layer (if present) includes a thin silicon oxide layer having a thickness in the range of 1 nm to 6 nm. The first sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon) or a semiconductor material (such as amorphous silicon). The excess portion of the first sacrificial fill material located above the horizontal plane of the top surface including the first insulating capping layer 170 may be removed by a planarization process that may employ a grooved etch process or a chemical mechanical polishing process. Each remaining portion of the first sacrificial fill material that fills the first-level memory openings 149 constitutes a first-level sacrificial memory opening fill material portion 148. Each remaining portion of the first sacrificial fill material that fills the first-level support openings 119 constitutes a first-level sacrificial support opening fill material portion 118.

[0070] Reference Figures 8A to 8E, A second alternating stack of the second insulating layer 232 and the second sacrificial material layer 242 may be formed over the first hierarchical structure. The second insulating layer 232 may include and / or may be substantially composed of the same material as the first insulating layer 132. The second sacrificial material layer 242 may include and / or may be substantially composed of the same material as the first sacrificial material layer 142. Each of the second insulating layers 232 extends continuously over the entire area of the substrate 8 and may have a uniform thickness throughout. Each of the second sacrificial material layers 242 extends continuously over the entire area of the substrate 8 and may have a uniform thickness throughout.

[0071] The thickness range for the second insulating layer 232 may be the same as the thickness range for the first insulating layer 132. The thickness range for the second sacrificial material layer 242 may be the same as the thickness range for the first sacrificial material layer 142. The total number of repetitions of a pair of the second insulating layer 232 and the second sacrificial material layer 242 in the second alternating stack (232, 242) may be in the range of 26 to 1024 (such as 64 to 512), but smaller and larger numbers may also be employed. The second insulating layer 232 is a second subset of the insulating layer 32 formed over the substrate 8, and the second sacrificial material layer 242 is a second subset of the sacrificial material layer 42 formed over the substrate 8.

[0072] Multiple stepped surfaces S may be simultaneously formed in the contact region 200 by patterning the second alternating stack (232, 242). In one embodiment, a hard mask layer (not shown), such as a metal or dielectric mask material layer, may be formed over the second alternating stack (232, 242) and may be patterned to form a plurality of rectangular openings. The area of the openings in the hard mask layer corresponds to the area where a cavity 269 including a stepped bottom surface is subsequently to be formed. Each opening through the hard mask layer may be rectangular and may have a pair of sides parallel to the second horizontal direction hd2 and a pair of sides parallel to the second horizontal direction hd2. The rectangular openings through the hard mask layer may be arranged along the second horizontal direction hd2 and may or may not be alternately staggered along the second horizontal direction hd2.

[0073] A trimable mask layer (not shown) may be applied over the second alternating stack. The trimable mask layer may include a trimable photoresist layer that may be controllably trimmed by a timed ashing process. The trimable mask layer may be patterned with an initial pattern such that the segment of each rectangular opening in the hard mask layer closest to the memory array region 100 is not masked by the trimable mask layer, while the remainder of each rectangular opening is covered by the trimable mask layer. For example, the trimable mask layer may have a rectangular shape with straight edges parallel to the second horizontal direction hd2 such that the straight edges are located over the vertical steps closest to one of the memory array regions 200 in the corresponding stepped surface.

[0074] A stepped surface S may be formed within the regions of the rectangular openings in the hard mask layer by iteratively performing a set of layer patterning process steps. The set of layer patterning process steps includes: an anisotropic etching process that etches unmasked portions of a pair of second insulating layers 232 and a second sacrificial material layer 242; and a mask trimming process in which the trimable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 200. A final anisotropic etching process may be performed after the last mask trimming process, and the trimable mask layer may be removed, for example, by ashing. The hard mask layer may be removed selectively to the materials of the second alternating stack (32, 42) by an isotropic etching process such as a wet etching process. Alternatively, any other suitable process may be used to form the stepped surface.

[0075] A second cavity 269 having a corresponding stepped bottom surface may be formed within each region of the rectangular openings in the hard mask layer. Each second cavity 269 may include a steep wall region in which a second end wall EW2 of the second alternating stack (32, 42) extends from the bottommost layer of the second alternating stack (232, 242) to the topmost layer of the second alternating stack (232, 242). The second end wall EW1 may be tapered (i.e., inclined) at an angle of 1 degree to 30 degrees with respect to the vertical direction. Each second cavity 269 has a stepped bottom surface. The stepped bottom surface of each cavity 269 extends laterally along the second horizontal direction hd2 and is located below the volume of the void in the second cavity 269. Generally, the stepped surface S may be formed by patterning the second alternating stack (232, 242) in each contact region 200 that is located between a corresponding first memory array region 100A and a second memory array region 100B. All layers of the second alternating stack (232, 242) may be removed in a region above the underlying first dielectric fill structure 165. In one embodiment, the entire top surface of the first dielectric fill structure may be physically exposed when forming the second cavity 269.

[0076] Generally speaking, each second cavity 269 may have a stepped surface S including vertically extending surface segments that are staggered with horizontally extending surface segments forming the bottom surface of the second cavity 269. In addition, each second cavity 269 may include a pair of second tapered (e.g., inclined) sidewalls TS2 that are parallel to a first horizontal direction hd1, laterally spaced apart from each other along a second horizontal direction hd2, and have corresponding stepped bottom ends adjacent to the corresponding stepped perimeters of the stepped bottom surface. The second tapered sidewalls TS2 may taper (i.e., incline) at an angle of 5 degrees to 45 degrees relative to the vertical direction. The lateral distance along the second horizontal direction hd2 between the pair of second tapered sidewalls TS2 is the width of the corresponding second cavity 269, and this width increases with the vertical distance from the substrate 8.

[0077] Generally, at least one alternating stack of the insulating layer 32 and the first-level sacrificial material layer 42 may be formed, and at least one cavity (169, 269) may be formed through the at least one alternating stack (32, 42). The combination of the first alternating stack (132, 142) and the second alternating stack (232, 242) constitutes another alternating stack with a greater height, and this alternating stack may be referred to as the alternating stack (32, 42) of the insulating layer 32 and the first-level sacrificial material layer 42. The horizontal plane including the topmost surface of the alternating stack (32, 42) is referred to herein as the first horizontal plane HP1, and the horizontal plane including the bottommost surface of the alternating stack (32, 42) is referred to herein as the second horizontal plane HP2.

[0078] The cavities (169, 269) may be formed in the alternating stack (32, 42) such that the stepped surface S of the alternating stack (32, 42) is exposed below the cavities (169, 269). The alternating stack (32, 42) includes tapered sidewalls (TS1, TS2) that extend laterally along the first horizontal direction hd1 in the contact region 200.

[0079] Reference Figures 9A to 9E , the second insulating liner 260 may be conformally deposited over the underlying structure. The second insulating liner 260 includes an insulating material such as silicon oxide. The material of the second insulating liner 260 is different from the material of the second sacrificial material layer 242. The second insulating liner 260 is deposited over the stepped surface of the second alternating stack (232, 242), over each second tapered sidewall TS2 of the second alternating stack (232, 242), and over the topmost layer of the second alternating stack (232, 242). The thickness of the second insulating liner 260 may be in the range of 50 nm to 200 nm (such as 100 nm to 150 nm), but smaller and larger thicknesses may also be employed.

[0080] A photoresist layer (not shown) may be formed over the second insulating liner 260 and may be lithographically patterned to form an opening that laterally extends across the entire lateral extent of the stepped surface of the second alternating stack (232, 242) and the underlying first dielectric fill structure 165. An etching process may be performed to etch the unmasked portions of the second insulating liner 260. The etching process may include an isotropic etching process or an anisotropic etching process. An opening is formed through the second insulating liner 260 in the region of each second cavity 269. The opening may include a first rectangular region and a second rectangular region. The first rectangular region is located below the stepped surface of the second alternating stack (232, 242), and the horizontally extending portion of the first sacrificial liner 182 that is located above the first alternating stack (132, 142) and the top surface of the underlying first dielectric fill structure 165 are entirely exposed under the second rectangular region. Segments of the stepped surface of the second alternating stack (232, 242) are exposed through an elongate opening that passes through the second insulating liner 260 below the second cavity 269, which second cavity is present within the volume of the respective second cavity 269. The physically exposed surface of the first sacrificial liner 182 may have a generally rectangular frame shape, i.e., the shape of a first rectangle from which the area of a smaller second rectangle is subtracted such that the outer rectangular perimeter of the shape is spaced apart from the inner rectangular perimeter of the shape.

[0081] In one embodiment, a portion of the opening through the second insulating liner 260 that is located above the stepped surface of the second alternating stack (232, 242) laterally extends along a second horizontal direction hd2 and may have a uniform width along the second horizontal direction hd2. In one embodiment, each second insulating liner 260 includes a first horizontally extending portion that is located above the second alternating stack (232, 242), and a plurality of tapered vertically extending portions that are located above the respective second tapered sidewall TS2. In one embodiment, each second insulating liner 260 includes a plurality of second horizontally extending portions that are located above the bottom surface of the respective second cavity 269 within the array of second cavities 269. A pair of second horizontally extending portions of the second insulating liner 260 may contact segments of the respective top surface of the second sacrificial material layer 242 and may be laterally spaced apart from each other by a rectangular region of the opening that passes through the second insulating liner 260.

[0082] Reference Figures 10A to 10E, a second sacrificial liner material may be conformally deposited over the second insulating liner 160 and may subsequently be patterned to form a second sacrificial liner 282. The second sacrificial liner material includes a material that may subsequently be selectively removed with respect to the materials of the second insulating layer 232 and the second insulating liner 260. In one embodiment, the second sacrificial liner material may be the same as the first level sacrificial material of the second sacrificial material layer 242. In one embodiment, the second sacrificial liner 282 may comprise silicon nitride or may consist essentially of silicon nitride. The thickness of each second sacrificial liner 282 may be in the range of 10 nm to 50 nm (such as 15 nm to 30 nm), although smaller and larger thicknesses may also be employed.

[0083] Within the region of each repeating unit RU, the second sacrificial liner 282 may be formed such that the entirety of the physically exposed sidewalls of the second sacrificial liner 282 is formed above a horizontal plane including the topmost surface of the second alternating stack (232, 242). In other words, the end portions of the second sacrificial liner 282 extend along a second horizontal direction hd2 over the tapered sidewalls TS2 and over the top of the second alternating stack (232, 242). Accordingly, the length of the second sacrificial liner 282 along the second horizontal direction hd2 may be longer than the length of the underlying second cavity 269 along the second horizontal direction hd2. The length of the second sacrificial liner 282 along a first horizontal direction hd1 may be the same as, shorter than, or longer than the length of the underlying second cavity 269 along the first horizontal direction hd1. The second cavity 269 is present within the volume laterally enclosed by the second sacrificial liner 282. The second sacrificial liner 282 may be formed directly on the physically exposed portion of the stepped surface S of the second alternating stack (232, 242) such that each second sacrificial layer 242 includes a respective horizontal top surface segment HS2 that contacts a respective bottom surface segment BP1 of the second sacrificial liner 282, as Figure 10D shown. The second sacrificial liner 282 includes a horizontally extending top portion TP2 that is located above the second alternating stack (232, 242) and above the horizontally extending top portion of the second insulating liner 260. In one embodiment, the second insulating liner 260 contacts the entirety of a pair of second tapered sidewalls TS2 and a second end wall EW2, and the second sacrificial liner 282 is spaced apart from the pair of second tapered sidewalls TS2 and the second end wall EW2 by the second insulating liner 260.

[0084] Reference Figures 11A to 11E, A second dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited over the second sacrificial liner 282 and the second alternating stack (232, 242) to fill the second cavity 269. A planarization process (such as a chemical mechanical polishing process) may be performed to remove portions of the second dielectric fill material above a horizontal plane including the top surface of the second sacrificial liner 282. The second sacrificial liner 282 may be used as an endpoint detection structure and / or as a planarization stop structure. Each remaining portion of the second dielectric fill material filling the corresponding second cavity 269 constitutes a second dielectric fill structure 265. The continuous remaining portion of the second dielectric fill material above the top surface of the horizontally extending portion of the second insulating capping layer 260 above the second alternating stack (232, 242) constitutes a second insulating capping layer 270. Thus, a second hierarchical structure is formed over the first hierarchical structure. The second hierarchical structure includes all material portions located above the first hierarchical structure at this processing step.

[0085] Reference Figures 12A to 12E , A second etch mask layer (not shown) may be formed over the second insulating capping layer 270 and the second dielectric fill structure 265 and may be lithographically patterned to form various discrete openings therein. The pattern of the openings in the second etch mask layer may be the same as the pattern of the first hierarchical memory openings 149 and the first hierarchical support openings 119. A second anisotropic etch process may be performed to transfer the pattern of the discrete openings in the second etch mask layer through the second insulating capping layer 270, the second alternating stack (232, 242), and the second dielectric fill structure 265. Various openings may be formed through the second insulating capping layer 270, the second alternating stack (232, 242), and the second dielectric fill structure 265. The various openings may include second hierarchical memory openings 249 formed in the memory array region 100 and second hierarchical support openings 219 formed in the contact region 200. Each of the second hierarchical memory openings 249 may be formed directly on the top surface of a corresponding one of the first hierarchical sacrificial memory opening fill portions 148. Each of the second hierarchical support openings 219 may be formed directly on the top surface of a corresponding one of the first hierarchical sacrificial support opening fill portions 118.

[0086] The second hierarchical memory openings 249 may include multiple rows of second hierarchical memory openings 249 that are arranged along a first horizontal direction hd1 and are laterally spaced apart along a second horizontal direction hd2. Each region of the memory array region 100 within the repeating unit RU includes a corresponding two-dimensional array of second hierarchical memory openings 249 that are arranged as clusters. Adjacent clusters of the second hierarchical memory openings 249 may be laterally spaced apart along the second horizontal direction hd2.

[0087] In one embodiment, the second-level support openings 219 in the contact region 200 may be arranged as a two-dimensional periodic array of second-level support openings 219 within a respective one of the repeating units RU. In one embodiment, each two-dimensional periodic array of second-level support openings 219 may be a respective rectangular periodic array of second-level support openings 219.

[0088] In one embodiment, the second-level support openings 219 in the contact region 200 may extend along a second horizontal direction hd2. In another embodiment, the second-level support openings 219 in the contact region 200 may have a circular horizontal cross-section. In one embodiment, multiple columns of second-level support openings 219 arranged along the second horizontal direction hd2 may cut through respective vertically extending straight surface segments of the stepped bottom surface of the second alternating stack (232, 242). The vertically extending straight surface segments may be perpendicular to the first horizontal direction hd1.

[0089] Subsequently, the first-level sacrificial memory opening fill structures 148 and the first-level sacrificial support opening fill structures 118 may be removed by ashing or by selectively etching the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the dielectric fill structures (165, 265), the insulating liners (160, 260), the sacrificial liners (182, 282), and the semiconductor material layer 110 selectively. Multilevel memory openings 49 (which are also referred to as memory openings 49) are formed in each contiguous volume including the volume of the second-level memory openings 249 and the volume of the first-level memory openings 149. Multilevel support openings 19 (which are also referred to as support openings 19) are formed in each continuous volume including the volume of the second-level support openings 219 and the volume of the first-level support openings 119.

[0090] Reference Figures 13A to 13E, a sacrificial filler material (such as amorphous carbon or amorphous silicon) can be deposited in the memory opening 49 and the support opening 19. The excess of the sacrificial filler material can be removed above the horizontal plane including the top surface of the second insulating capping layer 270. Each remaining portion of the sacrificial filler material filling the corresponding memory opening 49 constitutes a sacrificial memory opening filling structure 48. Each remaining portion of the sacrificial filler material filling the corresponding support opening 19 constitutes a sacrificial support opening filling structure 18. The sacrificial support opening filling structures 18 can be arranged in multiple columns of sacrificial support opening filling structures 18 that extend through the corresponding vertical extending sidewalls perpendicular to the first horizontal direction hd1 of the stepped surfaces of the alternating stacks (32, 42). Alternatively, additional sacrificial filler material can be deposited into the second-level memory opening 249 and the second-level support opening 219 above the corresponding first-level sacrificial memory opening filling structure 148 and the first-level sacrificial support opening filling structure 118 to form the sacrificial memory opening filling structure 48 and the sacrificial support opening filling structure 18 described above, rather than removing the first-level sacrificial memory opening filling structure 148 and the first-level sacrificial support opening filling structure 118 at the step shown in Figures 12A to 12E the first-level sacrificial memory opening filling structure 148 and the first-level sacrificial support opening filling structure 118 are removed.

[0091] Referring Figures 14A to 14E , a sacrificial etch mask layer (not shown) is applied over the exemplary structure and can be lithographically patterned to cover the memory array region 100 without covering the contact region 200. The sacrificial etch mask layer can include a silicon oxide layer or a silicon nitride layer having a thickness in the range of 10 m to 50 nm, but smaller or larger thicknesses can also be employed. The sacrificial opening filling structure 18 can be removed from the interior volume of the support opening 19, for example, by ashing or selective etching.

[0092] A dielectric filling material (such as silicon oxide) can be deposited in the voids within the support openings 19. The excess portion of the dielectric filling material can be removed from above the horizontal plane of the top surface including the second insulating capping layer 270 by performing a planarization process (such as a chemical mechanical polishing process or a trench etching process). During the removal of the dielectric filling material from above the horizontal plane of the top surface including the second insulating capping layer 270, the sacrificial etch mask layer can be removed concomitantly. Each remaining portion of the dielectric filling material that fills the support openings 19 constitutes a support pillar structure 20. In one embodiment, a two-dimensional array of support pillar structures 20 can be formed in the contact region 200. The two-dimensional array of support pillar structures 20 can include multiple columns of support pillar structures 20, each column of support pillar structures being arranged along the second horizontal direction hd2 and vertically extending through a respective vertical extension planar surface of the stepped surface of the first alternating stack (132, 142) or the second alternating stack (232, 242) that is perpendicular to the first horizontal direction hd1. In this processing step, the first sacrificial liner 182 is an integral structure (i.e., a single continuous structure in which each point can be continuously connected to any other point by a respective path that is entirely contained within the volume of the single continuous structure), and multiple columns of support pillar structures 20 vertically extend through this integral structure. Similarly, the second sacrificial liner 282 is an integral structure, and multiple columns of support pillar structures 20 vertically extend through this integral structure.

[0093] Reference Figures 15A to 15E , the sacrificial memory opening filling structure 48 can be removed from within the memory opening 49, for example, by performing an ashing process or a selective etching process. A cavity is formed within the volume of the memory opening 49.

[0094] Figures 16A to 16F is a sequential vertical cross-sectional view of the inter-level memory opening 49 during the formation of the memory opening filling structure 58 according to an embodiment of the present disclosure.

[0095] Reference Figure 16A , illustrates the memory opening 49 after the removal of the sacrificial memory opening filling structure 48. The memory opening 49 extends through the alternating stack {(132, 142), (232, 242)} and optionally extends into the upper portion of the semiconductor material layer 110. The depth of depression of the bottom surface of each memory opening 49 relative to the top surface of the semiconductor material layer 110 can be in the range of 0 nm to 30 nm, but a greater depth of depression can also be employed. Optionally, the sacrificial material layer 42 can be partially laterally depressed, for example, by isotropic etching to form a laterally extending cavity (not shown).

[0096] An optional base channel portion 11 (which may be a silicon base) can be formed, for example, at the bottom portion of each memory opening 49 by a selective semiconductor deposition process. In one embodiment, the base channel portion 11 can be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 110, which conductivity type is the first conductivity type. In one embodiment, the top surface of each base channel portion 11 can be formed below the horizontal plane including the top surface of the bottommost insulating layer 32. The base channel portion 11 can be part of a transistor channel that extends between a source region to be subsequently formed in the semiconductor material layer 110 and a drain region to be subsequently formed in the upper portion of the memory opening 49. A memory cavity 49' exists in the unfilled portion of the memory opening 49 above the base channel portion 11.

[0097] Reference Figure 16B , a stack of layers including a barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56 can be deposited in each memory opening 49. The stack of layers is referred to herein as the memory film 50.

[0098] The barrier dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer 52 can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. In one embodiment, the barrier dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., greater than the dielectric constant of silicon nitride). Alternatively or additionally, the barrier dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the barrier dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the barrier dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in the range of 1 nm to 20 nm, although smaller and larger thicknesses can also be employed.

[0099] The memory material layer 54 can include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of the presence or absence of charge, the direction of ferroelectric polarization, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material that includes a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer 54 can include a continuous layer or a patterned discrete portion of a conductive material (such as doped polysilicon or a metal material), which is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by forming in a laterally extending cavity that enters the sacrificial material layer 42. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 can have vertically aligned sidewalls, and the memory material layer 54 can be formed as a single continuous layer. Generally speaking, the memory material layer 54 can include a vertical stack of memory elements located at the level of the sacrificial material layer 42. For example, the vertical stack of memory elements can be embodied as an annular portion of the memory material layer 54 located at the level of the sacrificial material layer 42.

[0100] The optional dielectric liner layer 56 (if present) includes a dielectric liner material. In one embodiment, the dielectric liner layer 56 can include a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. Depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling can be performed by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. The dielectric liner layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, their alloys, and / or their combinations. In one embodiment, the dielectric liner layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the dielectric liner layer 56 can include a carbon-free silicon oxide layer or a carbon-free silicon oxynitride layer. The thickness of the dielectric liner layer 56 can be in the range of 2 nm to 20 nm, but smaller or larger thicknesses can also be employed.

[0101] Optionally, a sacrificial capping material layer 601 can be formed over the memory film 50. Refer to Figure 16C, at least one anisotropic etching process is used to anisotropically etch the optional sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 sequentially. The portions of the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 that are located above the top surface of the second insulating capping layer 270 can be removed by at least one anisotropic etching process.

[0102] In addition, the horizontal portions of the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form openings in the remaining portions of these layers. Each of the sacrificial capping material layer, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 can be etched by a corresponding anisotropic etching process using a corresponding etching chemical, which can be the same or different for the various material layers.

[0103] Each remaining portion of the sacrificial capping material layer 601 (if used) can have a tubular configuration. The surface of the base channel portion 11 (or the surface of the semiconductor material layer 110 if the base channel portion 11 is not used) can be physically exposed below the openings through the sacrificial capping material layer, dielectric liner layer 56, memory material layer 54, and dielectric metal oxide barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed such that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or from the semiconductor material layer 110 if the base channel portion 11 is not used) by a certain recess distance. In one embodiment, the sacrificial capping material layer 601, dielectric liner layer 56, memory material layer 54, and barrier dielectric layer 52 can have vertically coincident sidewalls. Subsequently, the sacrificial capping material layer 601 can be removed selectively to the material of the dielectric liner layer 56. In the case where the sacrificial capping material layer 601 comprises amorphous silicon, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be performed to remove the sacrificial capping material layer. Alternatively, if the sacrificial capping material layer 601 contains a silicon material, the sacrificial capping material layer can be retained in the final device.

[0104] Reference Figure 16D, the semiconductor channel layer 60L can be directly deposited on the semiconductor surface of the base channel portion 11 (or directly deposited on the semiconductor material layer 110 if the base channel portion 11 is omitted), and directly deposited on the memory film 50. The semiconductor channel layer 60L includes semiconductor materials, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L can be doped with a first conduction type that is the same as the conduction type of the semiconductor material layer 110 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method, such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. The semiconductor channel layer 60L can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0105] Reference Figure 16E , a dielectric core layer can be deposited to fill any remaining portion of the memory cavity 49' within each memory opening 49. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method, such as low-pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process, such as spin coating.

[0106] The horizontal portion of the dielectric core layer can be removed, for example, by a recess etching process, such that each remaining portion of the dielectric core layer is located within a corresponding memory opening 49 and has a corresponding top surface below the horizontal plane including the top surface of the second insulating capping layer 270. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0107] Reference Figure 16F , a doped semiconductor material doped with a second conduction type can be deposited in each recessed area above the dielectric core 62. The deposited semiconductor material can be doped with a second conduction type opposite to the first conduction type. For example, if the first conduction type is p-type, the second conduction type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10^18 / cm³ to 2.0×10^21 / cm³, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polycrystalline silicon.

[0108] The excess portions of the deposited semiconductor material doped with the second conductivity type and the horizontal portions of the semiconductor channel layer 60L can be removed, for example, by chemical mechanical planarization (CMP) or a trench etching process, above the horizontal plane of the top surface of the second insulating capping layer 270. Each remaining portion of the doped semiconductor material doped with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (doped with the first conductivity type) constitutes a vertical semiconductor channel 60.

[0109] Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, an optional dielectric liner 56, a plurality of memory elements including a plurality of portions of the memory material layer 54, and an optional barrier dielectric layer 52. Each combination of the pedestal channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening fill structure 58.

[0110] In an alternative embodiment where the support opening is formed simultaneously with the memory opening 49, the support pillar structure 20 can be formed in the support opening simultaneously with the memory opening fill structure 58. In this alternative embodiment, the support pillar structure 20 has the same composition as the memory opening fill structure 58 but is not electrically connected to the subsequently formed bit line.

[0111] Reference Figures 17A to 17G illustrates an exemplary structure after the memory opening fill structure 58 and the support pillar structure 20 are formed within the memory opening 49 and the support opening 19, respectively. Examples of the memory opening fill structure 58 can be formed within each memory opening 49. Examples of the support pillar structure 20 can be formed within each support opening. Other memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60 can also be used.

[0112] Generally, each of the memory opening fill structures 58 includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel 60. In one embodiment, the vertical stack of memory elements can include portions (such as portions of the memory material layer 54) of the memory film 50 at the level of the sacrificial material layer (142, 242), which are subsequently replaced by a conductive layer.

[0113] Reference Figures 18A to 18I, a capping dielectric layer 280 may be formed over the second insulating capping layer 270, the memory opening fill structure 58, and the support pillar structure 20. The capping dielectric layer 280 comprises a dielectric material such as undoped silicate glass or doped silicate glass, and may have a thickness in the range of 30 nm to 300 nm, although smaller and larger thicknesses may also be employed. In one embodiment, the top surface of the memory opening fill structure 58 is located within a first horizontal plane HP1 that includes the bottom surface of the capping dielectric layer 280.

[0114] A photoresist layer (not shown) may be applied over the capping dielectric layer 280 and may be lithographically patterned to form openings in the photoresist layer. The openings in the patterned photoresist layer may include elongate openings that extend laterally along a first horizontal direction hd1 through the memory array region 100 and the contact region 200 between corresponding clusters of pairs of memory opening fill structures 58. Additionally, the openings in the patterned photoresist layer may include an array of discrete openings that are arranged such that the combination of the regions of the support pillar structures 20 and the regions of the discrete openings covers all of the vertically extending surfaces of the stepped surface of the alternating stack (32, 42) that are not covered by the elongate openings.

[0115] An anisotropic etching process may be performed to transfer the pattern of the openings through the capping dielectric layer 280, the second level structure, and the first level structure, and downwardly into at least the top surface of the semiconductor material layer 110. Lateral isolation trenches 79 may be formed beneath the elongate openings in the photoresist layer. The lateral isolation trenches 79 extend laterally along the first horizontal direction hd1 and may have a uniform width along a second horizontal direction hd2 that is greater than the maximum thickness of the sacrificial material layer 42. In one embodiment, the uniform width of the lateral isolation trenches 79 may be in the range of two times the average thickness of the sacrificial material layer 42 to ten times the average thickness of the sacrificial material layer 42.

[0116] An array of isolation cavities 77 is formed beneath the array of discrete openings in the photoresist layer. The isolation cavities 77 may have a maximum lateral dimension (i.e., length) in the range of about one-half the average thickness of the sacrificial material layer 42 to about five times the average thickness of the sacrificial material layer 42, and may have a width (i.e., the maximum dimension along a horizontal direction perpendicular to the length) in the range of 1 / 4 the average thickness of the sacrificial material layer 42 to about two times the average thickness of the sacrificial material layer 42. In one embodiment, the isolation cavities 77 may be elongate along the second horizontal direction hd2 such that the length of each isolation cavity 77 along the second horizontal direction hd2 is greater than the width of the isolation cavity along the first horizontal direction hd1. Alternatively, the isolation cavities 77 may have a circular horizontal cross-sectional shape.

[0117] The lateral isolation trenches 79 extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2. The lateral isolation trenches 79 may include first lateral isolation trenches 79 located at the edges of the respective repeating units RU and not in contact with any of the dielectric-filled structures (165, 265), and second lateral isolation trenches 79 that divide the respective first dielectric-filled structures 165 and the respective second dielectric-filled structures 265 into respective pairs of first dielectric-filled structures 165 and respective pairs of second dielectric-filled structures 265. Thus, each first lateral isolation trench 79 is laterally offset along the second horizontal direction hd2 from the cavities (169, 269) within the alternating stack (32, 42). Each second lateral isolation trench 79 cuts through the respective stack of the first cavity 169 and the second cavity 269 (the stack that was filled with the first dielectric-filled structure 165 and the second dielectric-filled structure 265 prior to the formation of the lateral isolation trenches 79).

[0118] Generally, an array of lateral isolation trenches 79 and isolation cavities 77 may be formed through the alternating stack (32, 42). The array of lateral isolation trenches 79 and isolation cavities 77, together with the support pillar structure 20, divides each of the sacrificial liners (182, 282) into a respective array of sacrificial liner strips (182', 282') that are laterally spaced apart from each other along the first horizontal direction hd1. Specifically, each first sacrificial liner 182 is divided into an array of first sacrificial liner strips 182', and each second sacrificial liner 282 is divided into an array of second sacrificial liner strips 282'. The sacrificial liner strips (182', 282') are exposed to the respective second lateral isolation trenches 79 when the lateral isolation trenches 79 are formed. Each of the sacrificial liner strips (182', 282') contacts a stepped surface S of the respective sacrificial material layer 42 within the respective cavity (169, 269).

[0119] Each tapered sidewall (TS1, TS2) of the cavity (169, 269) may be divided into a plurality of tapered sidewalls (TS1, TS2) (each having a smaller area than the respective original tapered sidewall prior to the division) when the support pillar structure 20 is formed or when the array of isolation cavities 77 is formed. Generally, the support pillar structure 20 and / or the array of isolation cavities 77 divides each of the tapered sidewalls (TS1, TS2) of the cavities (169, 269) within the alternating stack (32, 42) into a respective plurality of tapered sidewalls (TS1, TS2) that are laterally spaced apart from each other along the first horizontal direction hd1.

[0120] In one embodiment, each of the sacrificial liner bars (182', 282') includes: a first horizontally extending portion, which is the topmost portion; a tapered vertically extending portion that is located above a respective one of the plurality of tapered sidewalls (TS1, TS2); and a second horizontally extending portion, which is the bottommost portion and abuts a respective one of the sacrificial material layers 42.

[0121] The tapered vertically extending portion extends between the topmost portion and the bottommost portion at a non-zero angle relative to the vertical direction in a straight or stepped (e.g., diagonal) plane. The second horizontally extending portion may contact the top of the stepped surface of a respective one of the sacrificial material layers 42 in the respective cavity (169, 269).

[0122] In one embodiment, each of the sacrificial liner bars (182', 282') may include a stepped profiled portion near the opening in the respective insulating liner (160, 260). In this case, each of the sacrificial liner bars (182', 282) further includes: a vertically extending portion that abuts the second horizontally extending portion; and a third horizontally extending portion that abuts the vertically extending portion and abuts the bottom end of the tapered vertically extending portion. In the case where both the first alternating stack (132, 142) and the second alternating stack (232, 242) are present within the alternating stack (32, 42), the top end of the first sacrificial liner bar 182' may contact the bottom surface of the respective second sacrificial liner bar 282'. Each second sacrificial material layer 242 may have a respective top surface segment that contacts the bottom surface of the respective second sacrificial liner bar 282'. Each first sacrificial material layer 142 may have a respective top surface segment that contacts the bottom surface of the respective first sacrificial liner bar 182', and the respective first sacrificial liner bar has a respective top surface that contacts the bottom surface of the respective second sacrificial liner bar 282'.

[0123] Optionally, an ion implantation process may be performed to implant dopants of a second conductivity type into the surface portion of the semiconductor material layer 110 that is located below the array of the lateral isolation trenches 79 or isolation cavities 77. A source region 61 doped with a first conductivity type may be formed in the implanted portion of the semiconductor material layer 110.

[0124] Reference Figures 19A to 19I, an isotropic etching process can be performed to isotropically etch the materials of the sacrificial material layer 42 and the sacrificial liner strips (182', 282') selectively with respect to the materials of the insulating layer 32, the insulating liners (160, 260), the insulating capping layers (170, 270), the dielectric capping layer 280, and the semiconductor material layer 110. The isotropic etchant can be introduced into the lateral isolation trenches 79 and into the isolation cavities 77 during the isotropic etching process. For example, if the sacrificial material layer 42 and the sacrificial liner strips (182', 282') comprise silicon nitride, the isotropic etching process can include a wet etching process using hot phosphoric acid.

[0125] The laterally extending cavities 43 are formed in the volume from which portions of the sacrificial material layer 42 have been removed by the isotropic etching process. The laterally extending cavities 43 can include a first laterally extending cavity 143 formed in the volume from which the first sacrificial material layer 142 has been removed, and a second laterally extending cavity 243 formed in the volume from which the second sacrificial material layer 242 has been removed. The strip cavities (183, 283) are formed in the volume from which the sacrificial liner strips (182', 282') have been removed. The strip cavities (183, 283) include a first strip cavity 183 formed in the volume from which the first sacrificial liner strip 282' has been removed, and a second strip cavity 283 formed in the volume from which the second sacrificial liner strip 182' has been removed. The insulating layer 32, the dielectric fill structures (165, 265), the insulating capping layers (170, 270), and the dielectric capping layer 280 can be structurally supported by the memory opening fill structure 58 and the support pillar structure 20 during and after the formation of the laterally extending cavities 43 and the strip cavities (183, 283).

[0126] Reference Figures 20A to 20I, at least one conductive material can be deposited in the unfilled volume of the laterally extending cavity 43 and the strip cavities (183, 283) by providing at least one reaction gas through the laterally isolating trench 79 and through the isolation cavity 77 into the laterally extending cavity 43 and into the strip cavities (183, 283). For example, the at least one conductive material can include a metal barrier layer and a metal filling material. The metal barrier layer includes a conductive metal material that can be used as a diffusion barrier layer and / or an adhesion promoting layer for the metal filling material to be deposited subsequently. The metal barrier layer can include a conductive metal nitride material such as TiN, TaN, WN, MoN or a stack thereof, or can include a conductive metal carbide material such as TiC, TaC, WC or a stack thereof. In one embodiment, the metal barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can be in the range of 2 nm to 8 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses can also be used. In one embodiment, the metal barrier layer can consist essentially of a conductive metal nitride such as TiN.

[0127] The metal filling material can be deposited on top of the metal barrier layer to form a metal filling material layer. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating or a combination thereof. In one embodiment, the metal filling material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metal filling material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium or tantalum. In one embodiment, the metal filling material layer can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) can be used to deposit the metal filling material layer. In one embodiment, the metal filling material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metal filling material layer is spaced apart from the insulating layer 32, the insulating liner layers (160, 260), the memory opening filling structure 58 and the support pillar structure 20 by the metal barrier layer, which blocks the diffusion of fluorine atoms therethrough.

[0128] Multiple conductive layers 46 may be formed in multiple laterally extending cavities 43. Conductive bars 84 may be formed in a first subset of bar-shaped cavities (183, 283) that are adjacent to corresponding underlying conductive layers 46. Additional conductive bars 84' that are not electrically connected to any underlying conductive layer 46 may be formed over corresponding sets of at least one end wall (EW1, EW2) of a corresponding set of at least one cavity (169, 269). A continuous metal material layer (not shown) may be formed over the dielectric capping layer 280 and over the sidewalls and bottom surfaces of the lateral isolation trenches 79 and isolation cavities 77. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal fill material layer that are located between a vertically adjacent pair of dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer that are located in the lateral isolation trenches 79 or above the dielectric capping layer 280.

[0129] By performing an etching process that etches at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from above the dielectric capping layer 280 and from the sidewalls and bottom surfaces of the lateral isolation trenches 79 and isolation cavities 77. The etching process may include an anisotropic etching process and / or an isotropic etching process. The remaining portions of the deposited metal material in each of the laterally extending cavities 43 constitute the conductive layers 46. Each conductive layer 46 may be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. The conductive layer 46 includes a first conductive layer 146 that replaces the first sacrificial material layer 142 and a second conductive layer 246 that replaces the second sacrificial material layer 242. The conductive layer 46 may include a source-side select gate electrode, a word line located above the source-side select gate electrode, and a drain-side select gate electrode located above the word line.

[0130] The conductive bars 84 are formed in the volumes of the bar-shaped cavities (183, 283). Generally, the remaining portions of the sacrificial material layers (142, 242) and the sacrificial liner bars (182', 282') are respectively replaced by conductive material portions including the conductive layers 46 and the conductive bars 84. The conductive layer 46 is formed in the volume from which the sacrificial material layer 42 has been removed, and the conductive bars 84 respectively fill the volumes from which the sacrificial liner bars (182', 282') have been removed.

[0131] An alternating stack (32, 46) of insulating layers 32 and conductive layers 46 is formed between each adjacent pair of lateral isolation trenches 79. The alternating stack (32, 46) may include a first alternating stack of a first insulating layer 132 and a first conductive layer 146 and a second alternating stack of a second insulating layer 232 and a second conductive layer 246.

[0132] In one embodiment, each of the conductive bars 84 abuts a respective one of the conductive layers 46 at the bottom portion of a respective one of the cavities (169, 269), and is located above but does not contact a respective one of the tapered sidewalls (TS1, TS2) arranged along a first horizontal direction hd1. Each of the conductive bars 84 includes a respective topmost portion 84T located above a first horizontal plane HP1, which first horizontal plane includes the topmost surface of the alternating stack (32, 46). In one embodiment, each of the conductive bars is spaced apart from the respective tapered sidewall (TS1, TS2) by a respective tapered vertical extension of a respective insulating liner (160, 260).

[0133] In one embodiment, each of the conductive bars 84 includes: a first horizontally extending portion, which is the topmost portion 84T; a tapered vertical extension 84V located above a respective one of the tapered sidewalls (TS1, TS2); and a second horizontally extending portion, which is the bottommost portion 84V and abuts a respective one of the conductive layers 46. The tapered vertical extension 84V extends between the topmost portion and the bottommost portion (84T, 84B) at a substantially non-zero angle with respect to the vertical direction in a straight or stepped inclined (e.g., diagonal) plane.

[0134] In one embodiment, each of the conductive bars 84 further includes: a vertical extension 84X that abuts the second horizontally extending portion; and a third horizontally extending portion 84Y that abuts the vertical extension and abuts the bottom end of the tapered vertical extension.

[0135] In one embodiment, each of the conductive bars 84 and a respective one of the conductive layers 46 are formed as a single-piece structure (i.e., a single continuous structure), which single-piece structure includes a conductive material portion (such as a metal barrier layer or a metal-filled material portion) that continuously extends between the volume of the respective conductive bar 84 and a respective one of the conductive layers 46. Accordingly, the second horizontally extending portion of the bar 84 forms a step on the top surface of the respective conductive layer 46 within the single-piece structure, as Figure 20A 、 Figure 20C and Figure 20D shown. Accordingly, the bar 84 serves as a word line contact via structure.

[0136] In one embodiment, the drain-side select gate electrode (i.e., the uppermost second conductive layer 246) may have a separate contact via structure located in a separate stepped region that is located at an end of each memory array region 100 opposite the end facing the contact region 200. In this embodiment, the bar 84 serves as a word line contact via structure and a source-side select gate electrode contact via structure, but does not serve as a drain-side select gate electrode contact via structure.

[0137] In one embodiment, each insulating liner (160, 260) includes a first horizontal extension portion located above the plurality of conductive layers 46, and a plurality of additional tapered vertical extension portions located above the respective tapered sidewalls (TS1, TS2) of the tapered sidewalls (TS1, TS2). In one embodiment, each insulating liner (160, 260) includes a plurality of second horizontal extension portions located above the bottom surface of the respective cavity (169, 269) and below the second horizontal extension portion of the respective one of the conductive strips 84.

[0138] refer to Figures 21A to 21I , the insulating material layer may be conformally deposited in the lateral isolation trenches 79, in the isolation cavities 77, and on the dielectric capping layer 280. In one embodiment, the insulating material layer may have a thickness greater than half of the maximum width of the isolation cavities 77. In this case, the insulating material layer may fill the isolation cavities 77 in a manner that blocks at least the top portion of each isolation cavity 77.

[0139] An anisotropic etching process may be performed to remove the horizontally extending portions of the insulating material layer. Each remaining vertically extending portion of the insulating material layer formed in a corresponding lateral isolation trench 79 constitutes an insulating isolation trench spacer 74. Each remaining portion of the insulating material layer filling the isolation cavity 77 constitutes an isolation column structure 73.

[0140] At least one conductive material may be deposited in the remaining unfilled volume of the lateral isolation trench 79 to form source contact via structures 76, which may be conductive wall structures extending laterally along a first horizontal direction hd1. Each contact combination of the insulating isolation trench spacer 74 and the source contact via structure 76 constitutes a lateral isolation trench filling structure (74, 76) filling the corresponding lateral isolation trench 79. The lateral isolation trench filling structures (74, 76) include a first lateral isolation trench filling structure (74, 76) contacting a corresponding pair of at least one dielectric filling structure (165, 265), and a second lateral isolation trench filling structure (74, 76) not contacting any dielectric filling structure (165, 265).

[0141] The spacer pillar structure 73 and the support pillar structure 20 are lateral isolation structures, and these lateral isolation structures provide electrical isolation between adjacent pairs of conductive bars 84 that are laterally spaced apart along a first horizontal direction hd1 between corresponding lateral isolation trench filling structures (74, 76) of an alternating stack of the insulating layer 32 and the conductive layer 46 and a corresponding set of tapered sidewalls (TS1, TS2). Each lateral isolation structure (73, 20) may include a corresponding contiguous set of at least one support pillar structure 20 and at least one spacer pillar structure 73 that extends continuously along a second horizontal direction hd2 between the corresponding lateral isolation trench filling structures (74, 76) of the alternating stack of the insulating layer 32 and the conductive layer 46 and the corresponding set of tapered sidewalls (TS1, TS2).

[0142] The lateral isolation structures separate (73, 20) adjacent bars 84 along the first horizontal direction (i.e., the word line direction) hd1 such that each bar 84 contacts only one corresponding conductive layer 46 in the stepped cavities (169, 269) since the conductive layers 46 form the stepped bottom surfaces of the stepped cavities. This prevents the bars 84 from short - circuiting the vertically separated conductive layers 46.

[0143] Generally, an array of lateral isolation structures (20, 73) extends vertically from a first horizontal plane HP1 that includes the topmost surface of the alternating stack (32, 46) to a second horizontal plane HP2 that includes the bottommost surface of the alternating stack (32, 46) and is located between a corresponding adjacent pair of the tapered sidewalls (TS1, TS2) among the tapered sidewalls (TS1, TS2) of the alternating stack (32, 46).

[0144] In one embodiment, the first lateral isolation trench filling structure (74, 76) may have a first longitudinal sidewall that contacts each layer of the alternating stack (32, 46) and extends laterally along the first horizontal direction hd1. The second lateral isolation trench filling structure (74, 76) may have a second longitudinal sidewall that contacts each layer of the alternating stack (32, 46), extends laterally along the first horizontal direction hd1, and is laterally spaced from the first lateral isolation trench filling structure (74, 76) along the second horizontal direction hd2. The array of lateral isolation structures (20, 73) contacts the first lateral isolation trench filling structure (74, 76) and does not contact the second lateral isolation trench filling structure (74, 76).

[0145] In one embodiment, the lateral isolation structures (20, 73) within the array of lateral isolation structures (20, 73) include: at least one support pillar structure 20 that extends vertically from a horizontal plane including the bottom surface of the capping dielectric layer 280 and extends at least to a second horizontal plane HP2 including the bottommost surface of the alternating stack (32, 46); and at least one isolation pillar structure 73 that extends vertically from a horizontal plane including the top surface of the capping dielectric layer 280 and extends at least to the second horizontal plane HP2 and contacts at least two support pillar structures 20.

[0146] Each volume laterally surrounded by the first lateral isolation trench fill structures (74, 76), the tapered sidewalls (TS1, TS2) of the alternating stack of the insulating layer 32 and the conductive layer 46, and an adjacent pair of lateral isolation structures (20, 73) forms a well. The well can be filled with a corresponding patterned set of second dielectric fill structures 265 (optionally within corresponding portions of the first dielectric fill structure 165, at least one insulating liner (160, 260), and the conductive bar 84).

[0147] Each layer of the alternating stack (32, 46) is present within the first memory array region and the second memory array region (100A, 100B). At least a portion of the first conductive layer 146 and at least a portion of the second conductive layer 246 extend continuously from the first memory array region 100A to the second memory array region 100B through the array interconnect region (e.g., the "bridge" region) 220, which is located between the corresponding lateral isolation trench fill structures (74, 76) and the corresponding contacts in the corresponding cavities (169, 269) in the contact region 200 of any dielectric fill structures (165, 265). The first horizontal extension portion of each of the conductive bars 84 is located above the alternating stack (32, 46) in the interconnect region 220. The vertical extension portion of each of the conductive bars 84 is located above the corresponding tapered sidewalls (TS1, TS2) of the interconnect region 220.

[0148] In one embodiment, the alternating stack (32, 46) extends laterally in the first memory array region 100A and in the second memory array region 100B from the first lateral isolation trench fill structure (74, 76) to the second lateral isolation trench fill structure (74, 76), and has a range smaller than the lateral spacing between the first lateral isolation trench structure (74, 76) and the second lateral isolation trench structure (74, 76) along a second horizontal direction hd2 within the interconnect region 220 of the contact region 200. The interconnect region 220 is located between the first lateral isolation trench fill structure (74, 76) and the tapered sidewalls (TS1, TS2) of the alternating stack (32, 46).

[0149] Reference Figure 22A and Figure 22B, illustrating a first alternative configuration of an exemplary structure, which may be obtained from the exemplary structure illustrated in Figures 18A to 18I by forming an elongated isolation cavity extending along a second horizontal direction hd2 instead of the isolation cavity described in the reference Figures 21A to 21I and by forming an isolation wall structure 173 at the processing step described in the reference Figures 18A to 18I instead of the isolation pillar structure 72. Each isolation wall structure 173 may extend laterally along the second horizontal direction hd2.

[0150] In this embodiment, the lateral isolation structures (20, 173) within the array of lateral isolation structures (20, 173) include: at least one support pillar structure 20 that extends vertically from a horizontal plane including the bottom surface of the capping dielectric layer 280 and extends at least to a second horizontal plane HP2 including the bottommost surface of the alternating stack (32, 46); and an elongated isolation wall structure 173 that extends vertically from a horizontal plane including the top surface of the capping dielectric layer 280 and extends at least to the second horizontal plane HP2 and contacts at least two support pillar structures 20.

[0151] Reference Figure 23A and Figure 23B , illustrating a second alternative configuration of an exemplary structure, which may be obtained from the first alternative configuration of the exemplary structure by further elongating the isolation trench along the second horizontal direction hd2 such that the elongated isolation trench abuts a corresponding one of the lateral isolation trenches 79 and intersects the corresponding tapered sidewalls (TS1, TS2). In this case, the isolation wall structure 173 may abut the corresponding insulating isolation trench spacer 74.

[0152] In this embodiment, the lateral isolation structures 173 within the array of lateral isolation structures 173 include an elongated isolation wall structure 173 that extends vertically from a horizontal plane including the top surface of the capping dielectric layer 280 and extends at least to the second horizontal plane HP2 and contacts at least two support pillar structures 20. The first lateral isolation trench filling structure (74, 76) includes first insulating wall segments that are laterally spaced apart along a first horizontal direction hd1 and contact corresponding subsets of layers within the alternating stack (32, 46) and located in the same vertical plane, and the lateral isolation structures including the isolation wall structure 173 include second insulating wall segments (such as the profiled vertical sidewalls of the isolation wall structure 173) that abut a pair of adjacent first insulating wall segments within the first lateral isolation trench filling structure (74, 76).

[0153] Reference Figure 24A and Figure 24B, illustrates a third alternative configuration of an exemplary structure, which can be obtained from any of the exemplary structures illustrated in Figures 21A to 21I , Figure 22A and Figure 22B or Figure 23A and Figure 23B by reducing the thickness of the insulating material layer such that voids are present within the volume of the isolation cavity 77 or within the volume of the elongated isolation cavity after the anisotropic etching process for forming the insulating isolation trench spacer 74. In this case, each remaining portion of the insulating material layer retained within the volume of the isolation cavity 77 or within the volume of the elongated isolation cavity constitutes an isolation liner 73' having the same lateral thickness as the insulating isolation trench spacer 74. In one embodiment, the isolation liner 73' may be formed in a tubular configuration. The conductive fill structure 75 may be formed within each remaining volume of the isolation cavity 77 or the elongated isolation cavity 77. Each conductive fill structure 75 may be laterally surrounded by a corresponding isolation liner 73'. Each abutting combination of the isolation liner 73' and the conductive fill structure 75 constitutes a component of the lateral isolation structure (20, 73', 75).

[0154] In this embodiment, the lateral isolation structures (20, 73', 75) within the array of lateral isolation structures (20, 73', 75) include: at least one support pillar structure 20 that extends vertically from a horizontal plane including the bottom surface of the capping dielectric layer 280 and extends at least to a second horizontal plane HP2 including the bottommost surface of the alternating stack (32, 46); an isolation liner 73' that may optionally have a corresponding tubular configuration; and a conductive fill structure 75 that may be partially or completely surrounded by the insulating liner 73'. Thus, the lateral isolation structures (20, 73', 75) within the array of lateral isolation structures (20, 73', 75) include an isolation liner 73' and a conductive fill structure 75 that is laterally spaced from the alternating stack (32, 46) by the isolation liner 73'.

[0155] Referring to Figure 25A and Figure 25B , a fourth alternative configuration of the exemplary structure can be obtained from the third configuration of the exemplary structure by employing an elongated isolation cavity in place of the isolation trench employed in the third alternative configuration of the exemplary structure. For example, the elongated isolation cavity illustrated in the structure of Figure 22A and Figure 22B may be employed. In one embodiment, the isolation liner 73' may be formed in a tubular configuration. The conductive fill structure 75 may be formed within each remaining volume of the isolation cavity 77 or the elongated isolation cavity 77. Each conductive fill structure 75 may be laterally surrounded by a corresponding isolation liner 73'. Each abutting combination of the isolation liner 73' and the conductive fill structure 75 constitutes a component of the lateral isolation structure (20, 73', 75).

[0156] In one embodiment, the lateral isolation structures (20, 73', 75) within the array of lateral isolation structures (20, 73', 75) include: at least one support pillar structure 20, which extends vertically from a horizontal plane including the bottom surface of the capping dielectric layer 280 and extends at least to a second horizontal plane HP2 including the bottommost surface of the alternating stack (32, 46); an isolation liner 73', which may have a corresponding tubular configuration; and a conductive filling structure 75, which may be completely surrounded by the isolation liner 73' or may be partially surrounded by the isolation liner. In one embodiment, the lateral isolation structures (20, 73', 75) within the array of lateral isolation structures (20, 73', 75) include an isolation liner 73' and a conductive filling structure 75, which is laterally spaced apart from the alternating stack (32, 46) by the isolation liner 73'.

[0157] Figure 26A is a vertical cross-sectional view of a fifth alternative configuration of the exemplary structure after forming lateral isolation trench fill structures (74, 76) and lateral isolation structures (73', 75). For example, the elongated isolation cavity can be merged with the lateral isolation trench 79, as in Figure 23A and Figure 23B In this embodiment, the isolation liner 73' can be adjacent to the corresponding insulating isolation trench spacer 74. In addition, the conductive fill structure 75 can be adjacent to the corresponding source contact via structure 76. Each adjacent combination of the isolation liner 73' and the conductive fill structure 75 constitutes a component of the lateral isolation structure (73', 75).

[0158] In this embodiment, the lateral isolation structures (73', 75) within the array of lateral isolation structures (73', 75) include: an isolation liner 73', which is adjacent to the insulating isolation trench spacer 74; and a conductive fill structure 75, which is partially surrounded by the isolation liner 73' and adjacent to the source contact via structure 76. In one embodiment, the lateral isolation structures (73', 75) within the array of lateral isolation structures (73', 75) include the isolation liner 73' and the conductive fill structure 75, which is laterally spaced apart from the alternating stack (32, 46) by the isolation liner 73'.

[0159] refer to Figure 27AUp to FIG. 27I, the drain select level isolation structure 72 can be formed by a subset of the conductive layers 46 including the topmost conductive layer 46. For example, a photoresist layer (not shown) can be applied over the dielectric capping layer 280 and can be lithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1 within each of the memory array regions 100. An anisotropic etching process can be performed to transfer the pattern of the elongated openings through a subset of the layers in the alternating stack (32, 46) including the topmost conductive layer 46. The drain select level isolation trenches can be formed between adjacent multiple rows of memory opening fill structures 58 arranged along the first horizontal direction hd1. The photoresist layer can be removed, and a dielectric fill material such as silicon oxide can be deposited in the drain select level isolation trenches. The excess portion of the dielectric fill material can be removed from above the horizontal plane including the top surface of the dielectric capping layer 280. Each remaining portion of the dielectric fill material filling the corresponding drain select level isolation trench constitutes the drain select level isolation structure 72.

[0160] Reference Figures 28A to 28G , the contact level dielectric layer 290 can be formed over the dielectric capping layer 280. The contact level dielectric layer 290 includes a dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the contact level dielectric layer 290 can be in the range of 50 nm to 500 nm (such as 100 nm to 300 nm), but smaller and larger thicknesses can also be employed.

[0161] In Figure 28G one embodiment shown, an additional stepped region 300 is formed along a first (e.g., word line) horizontal direction at the end of each memory plane, including being formed in Figure 1 the region M2 shown. Figure 28G A portion of the region M2 at the end of the alternating stack (32, 46) of the second memory array region 100B is shown. Specifically, the stepped surface is formed only in the topmost conductive layer serving as the drain side select gate electrode 246D (e.g., 46D). In one embodiment, the conductive layer 46 serving as a word line or a source side select electrode lacks a stepped surface in the additional stepped region 300. The stepped surface of the additional stepped region 300 is formed at the ends of the memory array regions 100 that are opposite to the ends of the adjacent contact regions 200 of the memory array regions 100.

[0162] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 290 and may be lithographically patterned to form discrete openings over a respective one of the drain regions 63 in the memory opening fill structure 58, over the top planar portion of a respective conductive strip 84 in the interconnect region 220, or over the stepped surface of the drain-side select gate electrode 46D in the additional stepped region 300. An anisotropic etching process may be performed to form a drain contact via cavity over the drain region 63 and to form a connection via cavity over the top planar portions of the conductive strip 84 and the drain-side select gate electrode 46D. The photoresist layer may then be removed.

[0163] At least one conductive material may be deposited in the drain contact via cavity and the connection via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 290 by a planarization process such as a chemical mechanical planarization (CMP) process or a recess etching process. Each remaining portion of the at least one conductive material that fills the respective drain contact via cavity and contacts the top surface of the respective drain region 63 constitutes a drain contact via structure 88. Each remaining portion of the at least one conductive material that fills the respective connection via cavity and contacts the top surface of the respective conductive strip 84 constitutes a connection via structure 86. Each remaining portion of at least one conductive material that fills the respective connection via cavity and contacts the top surface of the respective drain-side select gate electrode constitutes a select gate via structure 186. In this embodiment, the conductive strip 84 is not in electrical contact with the drain-side select gate electrode 46D.

[0164] In an alternative embodiment, the additional stepped region 300 and the separate select gate via structure 186 are omitted. In this embodiment, a subset of the conductive strips 84 contacts the drain-side select gate electrode 46D in the interconnect region 220 rather than the select gate via structure 186.

[0165] Subsequently, additional metal interconnect structures (not shown), additional dielectric material layers (not shown), and metal bond pads (not shown) may be formed to provide a memory die.

[0166] Referring to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a memory device includes: an alternating stack (32, 46) including insulating layers 32 and conductive layers 46 interleaved along a vertical direction, wherein the alternating stack includes tapered sidewalls (TS1, TS2) that extend laterally along a first horizontal direction hd1 and are inclined along a second horizontal direction hd2 perpendicular to the first horizontal direction; memory openings 49 that extend vertically through each layer within the alternating stack; a memory opening fill structure 58 located within the memory openings and including a respective vertical stack of memory elements (e.g., multiple portions of a memory film 50) and respective vertical semiconductor channels 60; cavities (169, 269) within the alternating stack that are laterally defined by the tapered sidewalls (TS1, TS2) along a first side and have a bottom surface including a stepped surface S that includes at least some of the conductive layers 46; insulating liners (160, 260) located within the cavities above the tapered sidewalls; and conductive bars 84 that are adjacent to a respective one of the stepped surfaces of the stepped surface at the bottom surface of the cavities (169, 269), extend within the cavities above the insulating liners and the tapered sidewalls, and include respective top portions 84T located above the topmost surface of the alternating stack (32, 46).

[0167] In one embodiment, each of the conductive bars 84 is spaced apart from the tapered sidewalls (TS1, TS2) by a tapered vertical extension portion of the insulating liner (160, 260). The insulating liner (160, 260) further includes a first horizontally extending portion located above the stepped surface S and a second horizontally extending portion located between the topmost surface (e.g., horizontal plane HP1) of the alternating stack (32, 46) and the top portion 84T of the conductive bar 84.

[0168] In one embodiment, each conductive bar of the conductive bars includes: a first horizontally extending portion 84T that is the top portion; a tapered vertical extension portion 84V that is located above the tapered sidewalls (TS1, TS2); and a second horizontally extending portion 84B that is the bottom portion and is adjacent to a respective one of the stepped surfaces of the conductive layer 46 within the cavity (169, 269). Optionally, each of the conductive bars 84 further includes: a vertically extending portion 84X that is adjacent to the second horizontally extending portion; and a third horizontally extending portion 84Y that is adjacent to the vertically extending portion 84V and adjacent to the bottom end of the tapered vertical extension portion 84X.

[0169] In one embodiment, the dielectric fill structures (165, 265) are located in the cavities (169, 269) above the conductive bars 84 and above the stepped surface S. In one embodiment, each of the conductive bars 84 and a corresponding one of the conductive layers 46 are formed as an integral structure that includes a portion of conductive material that extends continuously between the volume of the corresponding conductive bar and the corresponding one of the conductive layers in the conductive layer.

[0170] In one embodiment, the lateral isolation structures (20, 73, 173) are located in the cavities (169, 269), extend vertically from the stepped surface S to at least the topmost surface HP1 of the alternating stack (32, 46), and each is located between a corresponding adjacent pair of conductive bars 84 along a first horizontal direction hd1. The first lateral isolation trench fill structures (74, 76) have a first longitudinal sidewall that contacts each layer of the alternating stack and extends laterally along the first horizontal direction; and the second lateral isolation trench fill structures (74, 76) have a second longitudinal sidewall that contacts each layer of the alternating stack (32, 46), extends laterally along the first horizontal direction hd1 and is laterally spaced from the first lateral isolation trench fill structures along a second horizontal direction hd2. The lateral isolation structures (20, 73, 173) contact the first lateral isolation trench fill structures and do not contact the second lateral isolation trench fill structures.

[0171] In one embodiment, a first set of memory opening fill structures 58 is located in the first memory array region 100A, and a second set of memory opening fill structures 58 is located in the second memory array region 100B, which is laterally spaced from the first memory array region 100A along the first horizontal direction hd1 by the contact region 200. The cavities (169, 269) and the conductive bars 84 are located in the contact region 200. At least a portion of the conductive layer 46 extends continuously from the first memory array region 100A through the interconnect region 220 to the second memory array region 100B, which is located between the second lateral isolation trench fill structures (74, 76) and the cavities (169, 269) in the contact region 200. The alternating stack (32, 46) extends laterally from the first lateral isolation trench fill structures to the second lateral isolation trench fill structures in the first memory array region 100A and in the second memory array region 100B, and has a smaller extent along the second horizontal direction hd2 within the interconnect region 220 than the lateral spacing between the first lateral isolation trench structure and the second lateral isolation trench structure. The topmost portion 84T of the conductive bars 84 is located above the topmost surface HP1 of the alternating stack (32, 46) in the interconnect region 220.

[0172] In Figure 28GIn one embodiment shown, the memory device further includes a stepped region 300 that is located in an alternating stack (32, 46) adjacent a first end of the second memory array region 100B, the first end being opposite a second end of the contiguous contact region 200 of the second memory array region 100B. The stepped surface is located in the stepped region 300 only in the uppermost set of the conductive layers 46 that serve as the drain-side select gate electrodes 46D. The connecting via structure 86 contacts the topmost portion 84T of the corresponding conductive strip 84, and the select gate via structure 186 contacts the top surface of the corresponding drain-side select gate electrode 46D in the stepped region 300.

[0173] In one embodiment, the cavity (169, 269) is further laterally defined along a second side opposite the first side by a first laterally isolating trench fill structure (74, 76), along a third side by a first tapered end wall (EW1, EW2) that extends along a second horizontal direction hd2 and is inclined along a first horizontal direction hd1, and along a fourth side by a stepped surface S.

[0174] In one embodiment, the first laterally isolating trench fill structure (74, 76) includes: a first insulating wall segment that is laterally spaced apart along the second horizontal direction hd2 and contacts a corresponding subset of the layers within the alternating stack (32, 46); and a second insulating wall segment that contacts the laterally isolating structure.

[0175] In one embodiment, each of the laterally isolating structures in the laterally isolating structure includes at least one support pillar structure 20 and at least one isolation pillar structure 73 that contacts the at least one support pillar structure 20. In another embodiment, each of the laterally isolating structures in the laterally isolating structure includes an isolation wall structure 173 that extends in the second horizontal direction hd2.

[0176] Various embodiments of the present disclosure can be used to provide conductive strips 84 that are integrally formed with and electrically connected to a corresponding one of the conductive layers 46. Reliable electrical contact with the conductive layer 46 can be achieved without using an anisotropic etching process that can penetrate the conductive layer 46 by forming the conductive strips 84.

[0177] Although the foregoing relates to particularly preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to one another. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including". In cases where embodiments employing a particular structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced using any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, the entire text of each such document is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: An alternating stack, the alternating stack including insulating layers and conductive layers that are interleaved along a vertical direction, wherein the alternating stack includes tapered sidewalls that extend laterally along a first horizontal direction and are inclined along a second horizontal direction perpendicular to the first horizontal direction; Memory openings that extend vertically through each layer within the alternating stack; A memory opening fill structure located within the memory openings and including a respective vertical stack of memory elements and respective vertical semiconductor channels; A cavity within the alternating stack, the cavity being laterally bounded along a first side by the tapered sidewalls and having a bottom surface including a stepped surface that includes at least some of the conductive layers within the conductive layers; An insulating liner located within the cavity above the tapered sidewalls; And A conductive bar that abuts a respective one of the stepped surfaces at the bottom surface of the cavity, extends within the cavity above the insulating liner and the tapered sidewalls, and includes a respective topmost portion located above the topmost surface of the alternating stack.

2. The memory device according to claim 1, wherein each of the conductive bars is spaced apart from the tapered sidewalls by a tapered vertical extension portion of the insulating liner.

3. The memory device according to claim 2, wherein the insulating liner further includes a first horizontally extending portion located above the stepped surface, and a second horizontally extending portion located between the topmost surface of the alternating stack and the topmost portion of the conductive bar.

4. The memory device according to claim 1, wherein each of the conductive bars includes: A first horizontally extending portion that is the topmost portion; A tapered vertical extension portion located above the tapered sidewalls; And A second horizontally extending portion that is the bottommost portion and abuts the respective one of the stepped surfaces of the conductive layer within the cavity.

5. The memory device according to claim 4, wherein each of the conductive bars further includes: A vertical extension portion that abuts the second horizontally extending portion; And A third horizontally extending portion that abuts the vertical extension portion and abuts the bottom end of the tapered vertical extension portion.

6. The memory device according to claim 1, the memory device further including a dielectric fill structure located within the cavity above the conductive bar and above the stepped surface.

7. The memory device according to claim 1, wherein each of the conductive bars and a respective one of the conductive layers within the conductive layers are formed as an integral structure, the integral structure including a conductive material portion that extends continuously between the volume of the respective conductive bar and the respective one of the conductive layers within the conductive layers.

8. The memory device according to claim 1, wherein the memory device further comprises a lateral isolation structure located in the cavity, vertically extending from the stepped surface to at least the topmost surface of the alternating stack, and each being located between a corresponding adjacent pair of the conductive bars along the first horizontal direction.

9. The memory device according to claim 8, wherein the memory device further comprises: a first lateral isolation trench fill structure having a first longitudinal sidewall that contacts each layer of the alternating stack and extends laterally along the first horizontal direction; and a second lateral isolation trench fill structure having a second longitudinal sidewall that contacts each layer of the alternating stack, extends laterally along the first horizontal direction, and is laterally spaced from the first lateral isolation trench fill structure along the second horizontal direction, wherein the lateral isolation structure contacts the first lateral isolation trench fill structure and does not contact the second lateral isolation trench fill structure.

10. The memory device according to claim 9, wherein: a first set of the memory opening fill structures is located in a first memory array region; a second set of the memory opening fill structures is located in a second memory array region, the second memory array region being laterally spaced from the first memory array region along the first horizontal direction by a contact region; the cavity and the conductive bars are located in the contact region; at least a portion of the conductive layer continuously extends from the first memory array region to the second memory array region through an interconnect region located between the second lateral isolation trench fill structure and the cavity in the contact region; the alternating stack is in the first memory array region and extends laterally from the first lateral isolation trench fill structure to the second lateral isolation trench fill structure in the second memory array region, and has a range smaller than the lateral spacing between the first lateral isolation trench structure and the second lateral isolation trench structure along the second horizontal direction in the interconnect region; and the topmost portion of the conductive bar is located above the topmost surface of the alternating stack in the interconnect region.

11. The memory device according to claim 10, wherein the memory device further comprises: a stepped region located in the alternating stack adjacent to a first end of the second memory array region, the first end being opposite to a second end of the second memory array region adjacent to the contact region; a stepped surface located only in the uppermost set of the conductive layer serving as a drain-side select gate electrode in the stepped region; a connection via structure that contacts the topmost portion of the corresponding conductive bar; and a select gate via structure that contacts the top surface of the corresponding drain-side select gate electrode in the stepped region.

12. The memory device according to claim 9, wherein the cavity is further laterally defined by the first laterally isolating trench filling structure along a second side opposite the first side, further laterally defined by a first tapered end wall extending along the second horizontal direction and inclined along the first horizontal direction along a third side, and further laterally defined by the stepped surface along a fourth side.

13. The memory device according to claim 9, wherein: the first laterally isolating trench filling structure includes: a first insulating wall segment that is laterally spaced apart along the first horizontal direction and contacts a corresponding subset of the layers within the alternating stack; and a second insulating wall segment that contacts the laterally isolating structure.

14. The memory device according to claim 8, wherein each of the laterally isolating structures in the laterally isolating structure includes at least one support pillar structure and at least one isolation pillar structure that contacts the at least one support pillar structure.

15. The memory device according to claim 8, wherein each of the laterally isolating structures in the laterally isolating structure includes an isolation wall structure extending in the second horizontal direction.

16. A method of forming a memory device, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers that are staggered along a vertical direction; forming a cavity in the alternating stack such that a stepped surface of the sacrificial material layer of the alternating stack is exposed at a bottom surface of the cavity; forming an insulating liner above the stepped surface, above a tapered sidewall of the alternating stack, and above a topmost layer of the alternating stack; forming an elongate opening through the insulating liner, wherein a segment of the stepped surface is exposed through the elongate opening through the insulating liner; forming a sacrificial liner on the segment of the stepped surface and above the elongate opening such that the sacrificial liner includes a top portion located above the alternating stack; forming a dielectric filling structure above the sacrificial liner; forming memory openings that extend at least vertically through the alternating stack; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures in the memory opening filling structures includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming an array of laterally isolating trenches and isolation cavities through the alternating stack, wherein the laterally isolating trenches and the isolation cavity array divide the sacrificial liner into sacrificial liner strips that are laterally spaced apart from each other; and partially replacing a remaining portion of the sacrificial material layer and the sacrificial liner strips with a conductive material, wherein a conductive layer is formed in a volume from which the remaining portion of the sacrificial material layer is removed and conductive strips are formed in volumes from which the sacrificial liner strips are removed.

17. The method according to claim 16, the method further comprising filling the laterally isolating trenches and the isolation cavities with a laterally isolating trench filling structure and a laterally isolating structure, respectively.

18. The method according to claim 16, the method further comprising: Form through the dielectric-filled structure and the alternately stacked support openings; And Form a support pillar structure including a dielectric filling material in the support openings, wherein the sacrificial liner strips are laterally spaced apart from each other by the combination of the support pillar structure and the isolation cavity array.

19. The method according to claim 16, the method further comprising: Form a contact-level dielectric layer over the conductive strip and over the memory opening filling structure; And Form a connection via structure on the top surface of the conductive strip.

20. The method according to claim 16, wherein: The elongated opening through the insulating liner extends laterally along a first horizontal direction; The lateral isolation trenches extend laterally along the first horizontal direction and are laterally spaced apart from each other along a second horizontal direction; The lateral isolation trenches include a first lateral isolation trench that is laterally offset from the cavity along the second horizontal direction, and a second lateral isolation trench that cuts through the cavity; And The sacrificial liner strip is exposed in the second lateral isolation trench when the second lateral isolation trench is formed.

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