Long-time impact signal storage test device and method based on heterogeneous memory
By combining heterogeneous memory with ferroelectric memory and NAND FLASH memory, the problems of insufficient memory capacity and data loss in the prior art are solved, and the complete storage of long-term impact signals under high-frequency response signals is realized.
Patent Information
- Application Number
- CN202510391979.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-22
AI Technical Summary
In the existing storage test devices, the small capacity of the ferroelectric memory cannot meet the long-term impact data recording requirements under multi-channel high-frequency sampling. The repeated erasing and writing operations of NAND FLASH memory before the negative delay triggers can easily lead to data loss, and cannot effectively ensure the complete storage of the long-term impact signal.
A heterogeneous memory combination of ferroelectric memory and NAND FLASH memory is used to cyclically store the impact acceleration signal into the ferroelectric memory in the negative delay stage, and then store it in the NAND FLASH memory in sequence after triggering, and data is transmitted to the upper computer after the test is completed.
It realizes effective storage of long-term impact signals under high-frequency response signals, ensures data integrity and reliability, and avoids data loss.
Smart Images
Figure CN120352097A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of embedded storage testing, and particularly to a long-time impact signal storage testing device and method based on heterogeneous memories. Background Art
[0002] In abnormal environmental tests such as dropping, impact, artillery, rocket sled, and static detonation, it is necessary to test the impact response of the internal structure of the product under test under the action of impact; due to the presence of high-speed collisions or high-impact processes in the test, it is necessary to use a storage testing method to test the impact response signal, that is, an embedded storage testing device with impact resistance is built into the product under test, the impact signal is collected during the test, and the data is stored in a non-volatile memory. After the test, the test data is read back.
[0003] Since the storage testing device is built into the product under test, usually only data acquisition can be started in advance and wait for the test, and the test time is uncertain. The impact signal is a high-frequency response signal, and generally requires the data acquisition frequency to be above 100KHz. For this reason, a negative-delay trigger acquisition and storage method is generally used to collect and store the test data. Its working principle is: allocate a certain proportion of the storage space in the memory to store the data before the trigger, and repeatedly store the collected data into this space before the trigger. When it is detected that the impact signal exceeds the trigger threshold, the cyclic storage is stopped, and the impact response data collected after the trigger is stored in the subsequent storage space in sequence; if the ferroelectric memory is used as the memory, due to its high-speed random read and write and non-erasable characteristics, it becomes the preferred choice, but limited by the small capacity, usually <1MB, it cannot meet the demand for recording long-time impact data for dozens of seconds under multi-channel high-frequency sampling (such as 100kHz); if a large-capacity NAND FLASH memory is used, due to the problem of easy generation of bad blocks and data loss during the repeated erasing and writing operations before the negative-delay trigger, it cannot meet the requirement of real-time overwrite writing, resulting in the contradiction between reliability and storage demand being difficult to reconcile, and it is impossible to effectively ensure the complete storage test of the long-time impact signal. Summary of the Invention
[0004] The main object of the present invention is to provide a long-time impact signal storage testing device based on heterogeneous memories, aiming to solve the problem that the memory in the existing storage testing device cannot meet the requirement of real-time overwrite writing, resulting in the contradiction between reliability and storage demand being difficult to reconcile, and it is impossible to effectively ensure the complete storage test of the long-time impact signal.
[0005] To achieve the above object, the present invention proposes a long-time impact signal storage testing device based on heterogeneous memories, and the long-time impact signal storage testing device based on heterogeneous memories includes: A ferroelectric memory and a NAND FLASH memory; A acquisition circuit, which is used to acquire the impact acceleration of the device under test and output a corresponding impact acceleration signal; A control circuit, which is connected to the acquisition circuit, is respectively connected to the ferroelectric memory and the NAND FLASH memory, and is also communicatively connected to a host computer; the control circuit is used to perform an erasing operation on the NAND FLASH memory according to a data erasing signal sent by the host computer and control the acquisition circuit to work; when the impact acceleration value corresponding to the impact acceleration signal does not exceed a preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, the impact acceleration signal is stored in the NAND FLASH memory; it is also used to, according to a data reading signal sent by the host computer, first transmit the impact acceleration signal stored in the ferroelectric memory to the host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.
[0006] In one embodiment, the long-time impact signal storage test device based on heterogeneous memories further includes an RS485 interface chip, which is used to establish a communication connection between the control circuit and the host computer.
[0007] In one embodiment, the long-time impact signal storage test device based on heterogeneous memories further includes a protection structure, which is used to protect the long-time impact signal storage test device based on heterogeneous memories.
[0008] In one embodiment, the control circuit is an FPGA.
[0009] In one embodiment, the acquisition circuit includes a high-speed AD chip, and the output end of the high-speed AD chip is connected to the control circuit.
[0010] The present invention also proposes a long-time impact signal storage test method based on heterogeneous memories, which is applied to the long-time impact signal storage test device based on heterogeneous memories as described above. The long-time impact signal storage test method based on heterogeneous memories includes the following steps: Obtain a data erasing signal; Perform an erasing operation on the NAND FLASH memory according to the data erasing signal and control the acquisition circuit to work to acquire an impact acceleration signal; In the negative delay stage, when the impact acceleration value corresponding to the impact acceleration signal does not exceed a preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; After the impact acceleration value corresponding to the impact acceleration signal exceeds a preset impact acceleration value and is triggered, the impact acceleration signal is stored in a NAND FLASH memory; Obtain a data reading signal, and according to the data reading signal, first transmit the impact acceleration signal stored in the ferroelectric memory to a host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.
[0011] The technical solution of the present invention collects an impact acceleration signal through a collection circuit. In the negative delay stage, that is, when the impact acceleration value corresponding to the impact acceleration signal does not exceed the preset impact acceleration value, the impact acceleration signal data is stored in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value and is triggered, the impact acceleration signal test data is sequentially stored in the NAND FLASH memory; after the test is completed, the impact acceleration signal data stored in the ferroelectric memory and the impact acceleration signal test data stored in the NAND FLASH memory are sequentially transmitted to the host computer, realizing the effective storage test of the long-term impact acceleration signal. Description of the Drawings
[0012] Figure 1 is the overall block diagram of the long-term impact signal storage test device based on heterogeneous memories of the present invention; Figure 2 is the module schematic diagram of the ferroelectric memory of the long-term impact signal storage test device based on heterogeneous memories of the present invention. Detailed Embodiments
[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.
[0014] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.
[0015] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0016] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.
[0017] In addition, the terms "first", "second", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0018] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, terms such as "arrangement", "connection", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0019] Since the existing storage test device is built into the device under test, it is necessary to start data acquisition in advance and wait for the test. The test time is uncertain. The impact signal is a high-frequency response signal, and the data acquisition frequency is above 100KHz. If a ferroelectric memory is used, it becomes a preferred choice because of its high-speed random read and write and non-erasable characteristics. However, it is limited by its small capacity, usually <1MB, and cannot meet the long-term impact data recording requirements for multi-channel high-frequency sampling (such as 100kHz) for dozens of seconds. If a large-capacity NAND FLASH memory is used, due to the problem that bad blocks are easily generated during the repeated erasing and writing operations before negative-delay triggering, resulting in data loss, it cannot meet the requirement of real-time overwrite writing, leading to the contradiction between reliability and storage requirements being difficult to reconcile, and it is impossible to effectively ensure the complete storage test of long-term impact signals.
[0020] To solve the above problems, the present invention proposes a long-term impact signal storage test device based on a heterogeneous memory. The following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.
[0021] As Figure 1-2 shown, the long-term impact signal storage test device based on a heterogeneous memory includes: A ferroelectric memory and a NAND FLASH memory; An acquisition circuit, which is used to acquire the impact acceleration of the device under test and output a corresponding impact acceleration signal; A control circuit, which is connected to the acquisition circuit, is respectively connected to the ferroelectric memory and the NAND FLASH memory, and is also communicatively connected to a host computer; the control circuit is configured to perform an erasing operation on the NAND FLASH memory according to a data erasing signal sent by the host computer, and control the acquisition circuit to work; when the impact acceleration value corresponding to the impact acceleration signal does not exceed a preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, the impact acceleration signal is stored in the NAND FLASH memory; it is also configured to, according to a data reading signal sent by the host computer, first transmit the impact acceleration signal stored in the ferroelectric memory to the host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.
[0022] In one embodiment, the control circuit is an FPGA.
[0023] In one embodiment, the acquisition circuit includes a high-speed AD chip, and an output end of the high-speed AD chip is connected to the control circuit.
[0024] In this embodiment, the acquisition circuit can adopt any acquisition circuit capable of acquiring impact acceleration signals, such as a high-speed AD chip. The acquisition circuit in this embodiment uses a high-speed AD chip to synchronously acquire multiple channels of impact acceleration signals; the control circuit in this embodiment uses an FPGA (Field Programmable Gate Array) to implement the control of the acquisition circuit, the ferroelectric memory, and the NAND FLASH memory; a lithium battery is also provided in this embodiment to provide a working power supply for the storage test device.
[0025] In this embodiment, the ferroelectric memory has a fast read / write speed, is convenient for randomly reading and writing data, and does not require an erasing operation before data writing, but its storage capacity is small; the NAND FLASH memory has a large storage capacity, but an erasing operation is required before writing data. Therefore, in this embodiment, a heterogeneous memory based on the ferroelectric memory and the NAND FLASH memory is used for negative-delay data storage. Among them, negative-delay data storage is to allocate a certain proportion of the storage space in the memory to store the data before triggering, repeatedly and circularly store the collected data into this space before triggering, and when it is detected that the data value exceeds the triggering threshold, stop circular storage and sequentially store the test data collected after triggering into the subsequent storage space; that is, during the negative-delay stage, the data is repeatedly and circularly written into the ferroelectric memory, and after triggering, the test data is sequentially written into the NAND FLASH memory to achieve an effective and complete storage test for long-time impact signals.
[0026] It can be understood that before the test, the host computer sends a data erasing signal to the FPGA. The FPGA performs an erasing operation on the NAND FLASH memory according to the data erasing signal, sets the triggering threshold and starts the data acquisition task; during the negative-delay acquisition stage, the FPGA controls the high-speed AD chip to synchronously acquire multiple-channel impact acceleration signals, and circularly stores the collected data into the ferroelectric memory. When the FPGA detects that the impact acceleration value exceeds the set triggering threshold, that is, when the impact acceleration value exceeds the preset impact acceleration value, stop writing data into the ferroelectric memory and sequentially write the data collected after triggering into the NAND FLASH memory; after the test ends, the host computer sends a data reading signal to the FPGA. The FPGA first uploads the impact acceleration signal data stored in the ferroelectric memory to the host computer according to the data reading signal, and then uploads the impact acceleration signal test data in the NAND FLASH memory to the host computer, thus effectively ensuring the complete storage test of the long-time impact acceleration signal.
[0027] Such as Figure 2As shown, the test data is stored in sequence. Among them, the first storage unit of the ferroelectric memory is used to store the address at the triggering moment, and this address at the triggering moment is used for the host computer to read the data and then combine the data. Specifically, before triggering, the control circuit stores the data in the ferroelectric memory in a cyclic manner. After the control circuit detects that the impact acceleration value exceeds the preset impact acceleration value, the test data after triggering is written into the NAND FLASH memory in sequence. It can be understood that assuming the address corresponding to the ferroelectric memory at the triggering moment is 0xXXXX, A represents the data stored in the ferroelectric memory from address 0x0001 to address 0xXXXX, B represents the data stored in the ferroelectric memory from address 0Xxxxx + 1 to address 0xFFFF, and C represents the data stored in the NAND FLASH. When the host computer combines the data, it combines them in the order of B→A→C to obtain the complete test data.
[0028] The long-time impact signal storage test device based on heterogeneous memories of the present invention collects the impact acceleration signal through the acquisition circuit. In the negative delay stage, that is, when the impact acceleration value corresponding to the impact acceleration signal does not exceed the preset impact acceleration value, the impact acceleration signal data is stored in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value and is triggered, the impact acceleration signal test data is stored in the NAND FLASH memory in sequence; after the test is completed, the impact acceleration signal data stored in the ferroelectric memory and the impact acceleration signal test data stored in the NAND FLASH memory are sequentially transmitted to the host computer to realize the effective storage test of the long-time impact acceleration signal.
[0029] In an embodiment, the long-time impact signal storage test device based on heterogeneous memories further includes an RS485 interface chip, and the RS485 interface chip is used to establish a communication connection between the control circuit and the host computer.
[0030] In this embodiment, the control circuit establishes a communication connection with the host computer through the RS485 interface chip to receive the data erasure signal and data read signal sent by the host computer, and transmit the impact acceleration signal stored in the ferroelectric memory and the impact acceleration signal stored in the NAND FLASH memory to the host computer; compared with the RS232 chip, the RS485 interface chip has a longer transmission distance, higher transmission rate and stronger anti-interference ability.
[0031] In an embodiment, the long-time impact signal storage test device based on heterogeneous memories further includes a protection structure for protecting the long-time impact signal storage test device based on heterogeneous memories.
[0032] In this embodiment, the protection structure can adopt any protection structure that can protect the storage test device to prevent the storage test device from being damaged during the test.
[0033] The present invention also provides a long-time impact signal storage and test method based on a heterogeneous memory. The long-time impact signal storage and test method based on a heterogeneous memory is applied to the above-mentioned long-time impact signal storage and test device based on a heterogeneous memory. The long-time impact signal storage and test method based on a heterogeneous memory includes the following steps: Obtain a data erasure signal; Perform an erasure operation on the NAND FLASH memory according to the data erasure signal, and control the acquisition circuit to work to acquire impact acceleration signals; In the negative delay stage, when the impact acceleration value corresponding to the impact acceleration signal does not exceed the preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; After being triggered when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, the impact acceleration signal is stored in the NAND FLASH memory; Obtain a data read signal, and according to the data read signal, first transmit the impact acceleration signal stored in the ferroelectric memory to the host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.
[0034] In this embodiment, the long-time impact signal storage and test device based on a heterogeneous memory uses a negative delay storage method to store long-time impact acceleration signals. Specifically, in the negative delay stage, the control circuit stores the impact acceleration data in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, that is, after being triggered, the impact acceleration signal test data is sequentially stored in the NAND FLASH memory. After the test is completed, the impact acceleration signal data stored in the ferroelectric memory and the impact acceleration signal test data stored in the NAND FLASH memory are sequentially transmitted to the host computer to achieve effective storage and test of long-time impact acceleration signals. Of course, the long-time impact signal storage and test device based on a heterogeneous memory can also be used for the storage and test of short-time transient impact signals.
[0035] In this embodiment, the test data is stored in sequence. Specifically, the first storage unit of the ferroelectric memory is used to store the address at the trigger moment. If the address corresponding to the trigger moment in the ferroelectric memory is 0xXXXX, let A represent the data stored in the ferroelectric memory from address 0x0001 to address 0xXXXX, B represent the data stored in the ferroelectric memory from address 0Xxxxx + 1 to address 0xFFFF, and C represent the data stored in the NAND FLASH. When the host computer combines the data, it combines them in the order of B→A→C to obtain the complete test data.
[0036] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.
Claims
1. A long-time impact signal storage and testing device based on heterogeneous memories, characterized in that The long-term impact signal storage and testing device based on heterogeneous memories includes: A ferroelectric memory and a NAND FLASH memory; An acquisition circuit, which is used to acquire the impact acceleration of the device under test and output a corresponding impact acceleration signal; A control circuit, the control circuit is connected to the acquisition circuit, the control circuit is respectively connected to the ferroelectric memory and the NAND FLASH memory, and the control circuit is also communicatively connected to a host computer; the control circuit is used to perform an erasure operation on the NAND FLASH memory according to a data erasure signal sent by the host computer and control the operation of the acquisition circuit; when the impact acceleration value corresponding to the impact acceleration signal does not exceed a preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, the impact acceleration signal is stored in the NAND FLASH memory; it is also used to, according to a data reading signal sent by the host computer, first transmit the impact acceleration signal stored in the ferroelectric memory to the host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.
2. The long-time shock signal storage and testing device based on heterogeneous memories according to claim 1, characterized in that The long-term impact signal storage and testing device based on heterogeneous memories further includes an RS485 interface chip, and the RS485 interface chip is used to establish a communication connection between the control circuit and the host computer.
3. The long-time impact signal storage and testing device based on heterogeneous memory according to claim 1, characterized in that The long-term impact signal storage and testing device based on heterogeneous memories further includes a protection structure for protecting the long-term impact signal storage and testing device based on heterogeneous memories.
4. The long-time impact signal storage and testing device based on heterogeneous memories according to claim 1, wherein The control circuit is an FPGA.
5. The long-time impact signal storage and testing device based on heterogeneous memory according to claim 1, characterized in that The acquisition circuit includes a high-speed AD chip, and the output end of the high-speed AD chip is connected to the control circuit.
6. A long-term impact signal storage and testing method based on heterogeneous memory, which is applied to the long-term impact signal storage and testing device based on heterogeneous memory according to any one of claims 1-5, and is characterized in that, The long-term impact signal storage and testing method based on heterogeneous memories includes the following steps: Obtain a data erasure signal; Perform an erasure operation on the NAND FLASH memory according to the data erasure signal and control the acquisition circuit to work to acquire an impact acceleration signal; In the negative delay stage, when the impact acceleration value corresponding to the impact acceleration signal does not exceed a preset impact acceleration value, the impact acceleration signal is cyclically stored in the ferroelectric memory; After being triggered when the impact acceleration value corresponding to the impact acceleration signal exceeds the preset impact acceleration value, the impact acceleration signal is stored in the NAND FLASH memory; Obtain a data reading signal, and according to the data reading signal, first transmit the impact acceleration signal stored in the ferroelectric memory to the host computer, and then transmit the impact acceleration signal stored in the NAND FLASH memory to the host computer.