Low-voltage stabilizing circuit based on N-type depletion transistor

Abstract

The invention aims to provide a low-voltage voltage stabilizing circuit based on an N-type depletion transistor, which belongs to the technical field of analog circuits and comprises a resistor R0, a resistor R1, a PMOS (P-channel Metal Oxide Semiconductor) transistor P1, an NMOS (N-channel Metal Oxide Semiconductor) transistor N1, an N-type depletion transistor N0 and an N-type depletion transistor N2. One end of the resistor R0 is connected with the power supply VDD, and the other end of the resistor R0 is connected with the source electrode of the PMOS tube P1; the grid electrode and the drain electrode of the PMOS tube P1 are connected with the drain electrode of the N-type depletion tube N0 and the grid electrode of the NMOS tube N1; the source electrode, the grid electrode and the substrate of the N-type depletion transistor N0 are all grounded; the drain electrode of the NMOS transistor N1 is connected with the source electrode of the PMOS transistor P1 and the grid electrode of the N-type depletion transistor N2; the drain electrode of the N-type depletion transistor N2 is connected with the power supply VDD, and the source electrode is connected with one end of the resistor R1 to serve as an output end VOUT. The constant current source is constructed through the N-type depletion transistor N0, the PMOS transistor P1 is controlled to work at a fixed bias point, the voltage stabilization function is achieved through the grid-source voltage superposition principle, and the constant current source has the advantages of being low in working voltage, simple in structure and small in chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, and particularly to a low-voltage regulated power supply circuit based on an N-type depletion transistor. Background Art

[0002] In the field of analog circuit design, a regulated power supply circuit is an essential and indispensable part. The main function of a regulated power supply circuit is to convert an unstable input voltage into a stable output voltage, providing a reliable power supply for various electronic devices and integrated circuits. In the prior art, a low-dropout linear regulator (LDO) has become one of the most commonly used regulated power supply circuits due to its excellent ripple suppression performance and fast transient response characteristics.

[0003] Traditional LDO regulators typically include multiple functional modules such as a reference voltage source, an error amplifier, a power transistor, and a feedback network. The reference voltage source is used to generate a stable reference voltage. The error amplifier compares the reference voltage with the feedback voltage and amplifies the error signal. The power transistor adjusts according to the output of the error amplifier to maintain a stable output voltage. Although this structure has excellent performance, it has the following several significant problems:

[0004] First, traditional LDOs require complex analog circuit modules such as operational amplifiers and reference voltage sources. These modules usually require a relatively high operating voltage, generally around 3V. With the continuous progress of integrated circuit technology and the urgent demand for low power consumption in products, this relatively high operating voltage limits its use in low-voltage application scenarios.

[0005] Second, modules such as operational amplifiers and reference voltage sources require a large number of MOS transistors and capacitors, which will occupy a relatively large chip area in layout design. This not only increases the manufacturing cost of the chip but also limits the miniaturization development of products.

[0006] In addition, the feedback loop of traditional LDOs is relatively complex and may have stability problems in some application scenarios, and reasonable compensation design is required to ensure the stable operation of the system.

[0007] With the rapid development of emerging applications such as the Internet of Things and wearable devices, higher requirements are put forward for regulated power supply circuits. The market urgently needs a regulated power supply circuit solution with a simple structure, low operating voltage, and small chip area. Therefore, how to simplify the circuit structure, reduce the operating voltage, and decrease the chip area while ensuring the regulated power supply performance has become a technical problem to be solved urgently at present. Summary of the Invention

[0008] The object of the present invention is to overcome the deficiencies in the prior art and provide a low-voltage regulated power supply circuit based on an N-type depletion transistor. By utilizing the characteristics of the N-type depletion transistor to construct a constant current source and skillfully combining the gate-source voltage characteristics of PMOS and NMOS transistors, a stable output voltage is achieved. Not only is the operating voltage reduced to about 1.2V, but also the voltage regulation function can be completed with only two N-type depletion transistors, one PMOS transistor, one NMOS transistor and two resistors, significantly simplifying the circuit structure and reducing the chip area.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] A low-voltage regulated power supply circuit based on an N-type depletion transistor, comprising: a constant current source biasing circuit, a voltage regulation circuit and a voltage regulation output driving circuit;

[0011] The constant current source biasing circuit is connected to the voltage regulation circuit to provide a constant current source, and respectively clamps the gate-source voltage Vgsp of the PMOS transistor P1 and the gate-source voltage Vgsn of the NMOS transistor N1 through the saturation region operating characteristics of the PMOS transistor P1 and the NMOS transistor N1 in the voltage regulation circuit. After the gate-source voltage Vgsp and the gate-source voltage Vgsn are superimposed, they are output through the voltage regulation output driving circuit to form a stable voltage that can drive a load.

[0012] Further, the constant current source biasing circuit includes an N-type depletion transistor N0, and the output end of the constant current source biasing circuit is the drain of the depletion-type NMOS transistor N0;

[0013] The voltage regulation circuit includes a resistor R0, a PMOS transistor P1, and an NMOS transistor N1;

[0014] The voltage regulation output driving circuit includes a resistor R1 and an N-type depletion transistor N2;

[0015] One end of the resistor R0 is connected to the power supply VDD, and the other end is connected to the source of the PMOS transistor P1;

[0016] The gate of the PMOS transistor P1 is connected to the drain of the N-type depletion transistor N0 and the gate of the NMOS transistor N1; the drain of the PMOS transistor P1 is connected to the drain of the N-type depletion transistor N0 and the gate of the NMOS transistor N1; the source of the PMOS transistor P1 is connected to the substrate of the PMOS transistor P1, the gate of the N-type depletion transistor N2, and the drain of the NMOS transistor N1;

[0017] The drain of the NMOS transistor N1 is connected to the source of the PMOS transistor P1 and the gate of the N-type depletion transistor N2, and the source and substrate of the NMOS transistor N1 are both grounded;

[0018] The source, gate and substrate of the N-type depletion transistor N0 are all grounded;

[0019] For the N-type depletion transistor N2, although its drain is connected to the power supply VDD, its substrate is grounded, and its source is connected to one end of the resistor R1 as the output terminal VOUT, and the other end of the resistor R1 is grounded;

[0020] The PMOS transistor P1 is forced to operate in the saturation region due to the diode connection method, and its gate-source voltage Vgsp remains constant; the drain-source voltage Vdsn of the NMOS transistor N1 is designed to be greater than its gate-source voltage Vgsn to ensure that the NMOS transistor N1 operates in the saturation region; the gate-source voltage Vgsn of the NMOS transistor N1 satisfies the saturation region current formula, so that the change in the power supply voltage VDD is isolated through the saturation region characteristics of the NMOS transistor N1, thereby maintaining the stability of Vgsn. The N-type depletion transistor N2 adopts a source follower connection method, and its gate voltage is composed of the superposition of Vgsp and Vgsn. The output terminal VOUT satisfies:

[0021] V OUT =V gsp +V gsn

[0022] where Vgsp is the absolute value of the gate-source voltage of the PMOS transistor P1, and Vgsn is the gate-source voltage of the NMOS transistor N1;

[0023] The voltage of the power supply VDD is greater than the sum of Vgsp and Vgsn, and the typical value is 1.2V, so that the circuit can still operate stably under ultra-low voltage. The voltage of the power supply VDD satisfies:

[0024] V DD >V gsp +V gsn

[0025] The saturation region current I d of the NMOS transistor N1 satisfies the square-law relationship:

[0026]

[0027] where μ n is the electron mobility, C ox is the gate oxide capacitance, is the width-to-length ratio, and V thn is the threshold voltage of the NMOS transistor N1.

[0028] Furthermore, the voltage of the power supply VDD is greater than the sum of the gate-source voltage of the PMOS transistor P1 and the gate-source voltage of the NMOS transistor N1.

[0029] Furthermore, the typical value of the voltage of the power supply VDD is 1.2V.

[0030] Further, even when the voltage between the gate and the source of the N-type depletion transistor N0 is zero volts, it operates in the conducting state to form a constant current source.

[0031] Further, the N-type depletion transistor N2 is used as an output power transistor, and its gate voltage is controlled by the voltage obtained by superimposing the gate-source voltage of the PMOS transistor P1 and the gate-source voltage of the NMOS transistor N1.

[0032] The resistor R0 is used as a current-limiting resistor, and the resistance value of the resistor R0 is used to limit the magnitude of the current flowing through the PMOS transistor P1.

[0033] Further, the resistor R1 is used as a load resistor, and the resistor R1 is connected in series with the N-type depletion transistor N2 to form an output voltage dividing network.

[0034] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0035] (1) Since traditional LDO circuits require complex modules such as a reference voltage source and an operational amplifier, their operating voltage usually needs to be about 3V. However, the present invention innovatively uses an N-type depletion transistor to construct a constant current source and combines the gate-source voltage superposition characteristics of PMOS and NMOS transistors, so that the minimum operating voltage of the entire circuit only needs to be greater than the sum of two gate-source voltages, and the typical value can reach 1.2V, which is 60% lower than the traditional scheme. This fundamentally solves the problem of high operating voltage, and this significant reduction in operating voltage opens up new possibilities for low-voltage applications.

[0036] (2) Different from traditional LDOs that require a large number of MOS transistors and capacitors to construct modules such as a reference source and an operational amplifier, the present invention realizes a complete voltage regulation function only by using two N-type depletion transistors (N0, N2), one PMOS transistor (P1), one NMOS transistor (N1), and two resistors (R0, R1). The streamlined structure design of the present invention not only reduces the complexity of the circuit, but also significantly reduces the layout area of the chip, and it is expected to save more than 50% of the area, thus effectively reducing the manufacturing cost. Secondly, the present invention greatly simplifies the circuit structure and reduces the chip area.

[0037] (3) The present invention achieves excellent voltage regulation performance while ensuring a simple circuit. The constant current source constructed by the N-type depletion transistor N0 controls the PMOS transistor P1 to operate at a fixed bias point, so that the output voltage is mainly determined by two stable gate-source voltages. Since the influence of the power supply voltage change on these two gate-source voltages is extremely small, the output voltage has strong anti-power supply fluctuation ability. At the same time, using the N-type depletion transistor N2 as the output power transistor ensures that the circuit has good load driving ability.

[0038] In summary, based on the innovative structure of the N-type depletion transistor, the present invention breaks through the design idea of traditional LDOs, provides a brand-new technical route for low-voltage applications, and offers new ideas and inspiration for circuit design in similar scenarios. The present invention has strong practicality and scalability. With the rapid development of low-power applications such as the Internet of Things and wearable devices, the practical value of the present invention will be more prominent. The simple structure design of the present invention not only reduces the difficulty of circuit implementation but also improves the yield rate, making it particularly suitable for large-scale production. In addition, due to the removal of the complex compensation network, the stability of the circuit is also increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings forming a part of this specification depict embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0040] Referring to the drawings, the present invention can be more clearly understood from the following detailed description, wherein:

[0041] Figure 1 is the circuit diagram of the low-voltage voltage regulator circuit based on the N-type depletion transistor provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The technical solutions of the present invention will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. Without conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present invention.

[0043] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0044] Embodiment 1

[0045] 2. Figure 1 is the circuit diagram of the low-voltage voltage regulator circuit based on the N-type depletion transistor provided by the present invention. This embodiment is a typical implementation manner of the present invention, providing a low-voltage voltage regulator circuit based on the N-type depletion transistor, including: a constant current source biasing circuit, a voltage regulator circuit, and a regulated output driving circuit;

[0046] The constant current source biasing circuit is connected to the voltage stabilizing circuit to provide a constant current source. By the working characteristics of the saturation region of PMOS transistor P1 and NMOS transistor N1 in the voltage stabilizing circuit, the gate-source voltage Vgsp of PMOS transistor P1 and the gate-source voltage Vgsn of NMOS transistor N1 are clamped respectively. After the gate-source voltage Vgsp and the gate-source voltage Vgsn are superimposed, they are output through the voltage stabilizing output driving circuit to form a stable voltage that can drive a load.

[0047] Further, the constant current source biasing circuit includes an N-type depletion transistor N0, and the output terminal of the constant current source biasing circuit is the drain of the depletion-type NMOS transistor N0;

[0048] The voltage stabilizing circuit includes a resistor R0, a PMOS transistor P1, and an NMOS transistor N1;

[0049] The voltage stabilizing output driving circuit includes a resistor R1 and an N-type depletion transistor N2;

[0050] One end of the resistor R0 is connected to the power supply VDD, and the other end is connected to the source of the PMOS transistor P1;

[0051] The gate of the PMOS transistor P1 is connected to the drain of the N-type depletion transistor N0 and the gate of the NMOS transistor N1; the drain of the PMOS transistor P1 is connected to the drain of the N-type depletion transistor N0 and the gate of the NMOS transistor N1; the source of the PMOS transistor P1 is connected to the substrate of the PMOS transistor P1, the gate of the N-type depletion transistor N2, and the drain of the NMOS transistor N1;

[0052] The drain of the NMOS transistor N1 is connected to the source of the PMOS transistor P1 and the gate of the N-type depletion transistor N2, and the source and substrate of the NMOS transistor N1 are both grounded;

[0053] The source, gate, and substrate of the N-type depletion transistor N0 are all grounded;

[0054] The drain of the N-type depletion transistor N2 is connected to the power supply VDD, the substrate of the N-type depletion transistor N2 is grounded, and the source of the N-type depletion transistor N2 is connected to one end of the resistor R1 as the output terminal VOUT, and the other end of the resistor R1 is grounded.

[0055] The present invention uses an N-type depletion transistor N0 to form a constant current source structure. As long as there is a working voltage VDD, a constant current source will be formed, so that the working current of the PMOS transistor P1 remains constant;

[0056] Since the PMOS transistor P1 is connected in diode configuration (gate and drain are shorted), P1 must work in the saturation region, so its gate-source voltage Vgsp remains stable;

[0057] The drain-source voltage Vdsn of the NMOS transistor N1 is designed to be greater than its gate-source voltage Vgsn (i.e., Vdsn > Vgsn - Vthn), causing N1 to operate in the saturation region. The gate-source voltage Vgsn of the NMOS transistor N1 is determined by the saturation region current formula. According to the MOS transistor saturation region current formula:

[0058]

[0059] where I d is the saturation region current, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, is the width-to-length ratio of the NMOS transistor N1, V thn is the threshold voltage of the NMOS transistor N1;

[0060] In the above formula, it can be seen that Vgs and Id have a square-law relationship. As Id increases, Vgsn will increase at a square root rate. When the change in the power supply voltage VDD causes a change in the current Id on the NMOS transistor N1, the impact on Vgsn of the NMOS transistor N1 is very small and remains basically constant. Then, a stable voltage is obtained at the gate terminal of the NMOS transistor N2, and this voltage is equal to Vgsp + Vgsn. Although there are process deviations for the two voltages Vgsp and Vgsn, they are basically around 0.6V. When VDD is around 1.2V, the entire circuit can operate.

[0061] The gate voltage Vg2 of the NMOS transistor N2 is obtained by superimposing Vgsp of the PMOS transistor P1 and Vgsn of the NMOS transistor N1 (Vg2 = Vgsp + Vgsn), and the typical value is about 1.2V. The NMOS transistor N2 is connected in the common-drain amplifier configuration (source follower), and its source output voltage is about 1.2V. The load resistor R1 provides a path to the ground for the output terminal to stabilize the output voltage VOUT.

[0062] In the present invention, an N-type depletion transistor N0 forms a constant current source to control the current of the PMOS transistor to be constant, so as to fix the VGS of the PMOS transistor P1 and the VGS of the NMOS transistor N1 (VGS refers to the voltage difference between the gate and the source). After the two fixed voltages are superimposed, they are given to the gate of the N-type depletion output power transistor N2. The N-type depletion output power transistor N2 follows to output a stable voltage, which is a gate-source voltage Vgsp plus a gate-source voltage Vgsn. At this time, the output voltage is hardly affected by the power supply because the voltage change of VDS brought by the power supply has a very small impact on the change of the two Vgs voltages, and the N-type depletion output power transistor has the same driving ability as the traditional LDO.

[0063] Furthermore, the voltage of the power supply VDD is greater than the sum of the gate-source voltage of the PMOS tube P1 and the gate-source voltage of the NMOS tube N1. Specifically, the supply voltage of the power supply voltage terminal VDD satisfies: VDD>Vgsp+Vgsn, wherein Vgsp is the absolute value of the gate-source voltage of the PMOS tube P1, and Vgsn is the gate-source voltage of the NMOS tube N1.

[0064] Furthermore, a typical value of the voltage of the power source VDD is 1.2V.

[0065] Specifically, although the voltage between the gate and source of the N-type power supply N0 is zero volt, it works in the on state to form a constant current source.

[0066] Furthermore, the N-type power transistor N2 is used as an output power transistor, and its gate voltage is controlled by the voltage obtained by superimposing the gate-source voltage of the PMOS transistor P1 and the gate-source voltage of the NMOS transistor N1. When the N-type power transistor N2 operates in the source follower mode, its source output terminal VOUT is connected to the load resistor R1. Since the source follower has the characteristic of low output impedance, the output voltage VOUT can remain relatively stable even when the load current changes greatly. Specifically, when the load current changes from 10mA to 100mA, the change in output voltage is less than 50mV, showing excellent load regulation capability. In terms of transient response, when the load current changes in a step, such as from 10mA to 100mA, the N-type power transistor N2 can restore the output voltage to a stable value within 2μs. This fast transient response characteristic originates from the positive feedback effect of the source follower mode. When the output voltage decreases due to load changes, the gate-source voltage difference increases, and the on-current increases accordingly, thereby quickly compensating for the drop in output voltage.

[0067] Specifically, the resistor R1 is used as a load resistor. The resistor R1 and the N-type resistor N2 are connected in series to form an output voltage divider network. Preferably, the load resistor R1 is made of polysilicon material.

[0068] When in use, resistor R0 is used as a current limiting resistor, one end of which is connected to the power supply VDD, and the other end is connected to the source of PMOS tube P1, which is used to limit the current flowing through the PMOS tube. The gate and drain of PMOS tube P1 are simultaneously connected to the drain of N-type power supply N0 and the gate of NMOS tube N1. The source, gate and substrate of N-type power supply N0 are all grounded, forming a constant current source, providing a stable bias current for the entire circuit.

[0069] The drain of NMOS transistor N1 is connected to the source of PMOS transistor P1 and the gate of N-type depletion transistor N2, and its source and substrate are grounded. The N-type depletion transistor N2 serves as the output power transistor, with its drain connected to the power supply VDD and its source connected to one end of resistor R1 as the output terminal VOUT, and the other end of resistor R1 is grounded. The substrate of PMOS transistor P1 is connected to its source, and the substrate of N-type depletion transistor N2 is grounded.

[0070] The working principle of the present invention is as follows: The constant current source formed by N-type depletion transistor N0 ensures that PMOS transistor P1 operates at a fixed bias point, thereby generating a stable gate-source voltage Vgsp. This voltage, when superimposed with the gate-source voltage Vgsn of NMOS transistor N1, serves as the gate control voltage of N-type depletion transistor N2. Since N-type depletion transistor N2 operates in the source follower mode, its source voltage (i.e., the output voltage VOUT) will follow the change of the gate voltage, and finally output a stable voltage, with a value approximately equal to Vgsp plus Vgsn.

[0071] In practical applications, the change in the power supply voltage VDD has little effect on the two gate-source voltages Vgsp and Vgsn. Therefore, the output voltage VOUT can remain stable. At the same time, since the minimum operating voltage of the circuit only needs to be greater than the sum of Vgsp of PMOS transistor P1 and Vgsn of NMOS transistor N1, and the typical value can reach 1.2V, it is very suitable for low-voltage application scenarios.

[0072] In summary, compared with the prior art, the present invention provides a constant current source structure capable of operating in an ultra-low voltage environment, significantly reducing the working voltage requirement of the circuit. By cleverly using the superposition of the gate-source voltages of PMOS transistor P1 and NMOS transistor N1 as the control voltage, the minimum working voltage of the entire circuit only needs to be greater than the sum of the gate-source voltages of the two transistors, and the typical value can reach about 1.2V. This is 60% lower than the 3V working voltage required by traditional LDOs, providing an ideal solution for low-voltage applications. The present invention greatly simplifies the circuit structure and realizes the complete voltage regulation function only by using two N-type depletion transistors (N0, N2), one PMOS transistor (P1), one NMOS transistor (N1) and two resistors (R0, R1). Compared with traditional LDOs, complex modules such as the reference voltage source and operational amplifier are omitted, which can save more than about 50% of the chip area and effectively reduce the manufacturing cost. In terms of voltage regulation performance, the present invention controls the current of PMOS transistor P1 through the constant current source constructed by N-type depletion transistor N0, making it operate at a fixed bias point. This makes the output voltage mainly determined by the gate-source voltages of PMOS transistor P1 and NMOS transistor N1, and is hardly affected by the power supply voltage fluctuation because the influence of the power supply voltage change on the two gate-source voltages is extremely small. At the same time, using N-type depletion transistor N2 as the output power transistor has good driving ability and can meet the power supply requirements of the load, providing an ideal voltage regulation solution for low-voltage and small-area application scenarios and having important practical value.

[0073] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A low-voltage regulated circuit based on an N-type depletion transistor, which is used to achieve a stable low-voltage output of the power supply VDD. It is characterized in that, It includes: A constant current source biasing circuit, a voltage stabilizing circuit, and a voltage stabilizing output driving circuit; The constant current source biasing circuit is connected to the voltage stabilizing circuit to provide a constant current source, and by the working characteristics of the saturation region of PMOS transistor P1 and NMOS transistor N1 in the voltage stabilizing circuit, the gate-source voltage Vgsp of PMOS transistor P1 and the gate-source voltage Vgsn of NMOS transistor N1 are clamped respectively. After the gate-source voltage Vgsp and the gate-source voltage Vgsn are superimposed, they are output through the voltage stabilizing output driving circuit to form a stable voltage that can drive a load.

2. The low-voltage voltage stabilizing circuit based on N-type depletion transistors according to claim 1, wherein The constant current source biasing circuit includes an N-type depletion transistor N0, and the output terminal of the constant current source biasing circuit is the drain of depletion-type NMOS transistor N0; The voltage stabilizing circuit includes a resistor R0, a PMOS transistor P1, and an NMOS transistor N1; The voltage stabilizing output driving circuit includes a resistor R1 and an N-type depletion transistor N2; One end of the resistor R0 is connected to the power supply VDD, and the other end is connected to the source of the PMOS transistor P1; The gate of the PMOS transistor P1 is connected to the drain of the N-type depletion transistor N0, the gate of the NMOS transistor N1, and the drain of the PMOS transistor P1, so that the PMOS transistor P1 operates in the saturation region in a diode connection method, and its gate-source voltage Vgsp remains constant; The source, gate, and substrate of the N-type depletion transistor N0 are all grounded to form a constant current source; The drain of the NMOS transistor N1 is connected to the source of the PMOS transistor P1 and the gate of the N-type depletion transistor N2. The source and substrate of the NMOS transistor N1 are both grounded, and the NMOS transistor N1 operates in the saturation region, and the drain-source voltage Vds of the NMOS transistor N1 is greater than the gate-source voltage Vgsn, so that the influence of the change of the power supply voltage VDD on Vgsn is suppressed; The drain of the N-type depletion transistor N2 is connected to the power supply VDD, the substrate is grounded, and the source is connected to one end of the resistor R1 as the output terminal VOUT, and the other end of the resistor R1 is grounded; the gate voltage of the N-type depletion transistor N2 is controlled by the superposition of the gate-source voltage Vgsp of the PMOS transistor P1 and the gate-source voltage Vgsn of the NMOS transistor N1, and the output voltage VOUT is stabilized at the sum of Vgsp and Vgsn.

3. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 1, wherein The voltage of the power supply VDD is greater than the sum of the gate-source voltage of the PMOS transistor P1 and the gate-source voltage of the NMOS transistor N1.

4. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 3, wherein, The typical value of the voltage of the power supply VDD is 1.2V.

5. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 1, characterized in that The voltage between the gate and the source of the N-type depletion transistor N0 is zero volts, so that it operates in the conducting state to form a constant current source.

6. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 1, characterized in that The N-type depletion transistor N2 is used as an output power transistor, and its gate voltage is controlled by the voltage obtained by superimposing the gate-source voltage of the PMOS transistor P1 and the gate-source voltage of the NMOS transistor N1.

7. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 1, wherein, The resistor R0 is used as a current limiting resistor, and the resistance value of the resistor R0 is used to limit the magnitude of the current flowing through the PMOS transistor P1.

8. The low-voltage voltage stabilizing circuit based on an N-type depletion transistor according to claim 1, characterized in that The resistor R1 is used as a load resistor, and the resistor R1 and the N-type depletion transistor N2 are connected in series to form an output voltage dividing network.

9. The low-voltage voltage-stabilizing circuit based on an N-type depletion transistor according to claim 1, characterized in that, The saturation region current formula of the NMOS transistor N1 is: Among them, I d is the saturation region current, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, is the width-to-length ratio of NMOS transistor N1, V thn is the threshold voltage of NMOS transistor N1.

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