Reference voltage optimization method, circuit and device

Abstract

The invention relates to a reference voltage optimization method, circuit and device, and the method comprises the steps: carrying out the sampling of data transmitted on at least one data line through changing the phase of a sampling clock, and obtaining a sampling clock phase interval under the condition that the sampling data on the at least one data line are all correct; obtaining an optimized sampling clock phase according to the sampling clock phase interval; sampling data transmitted on each data line in the at least one data line by optimizing a sampling clock phase and changing a sampling voltage to obtain an effective reference voltage interval of each data line; and obtaining an optimized reference voltage of each data line according to the effective reference voltage interval of each data line. According to the invention, the identification accuracy of the signal receiving end on the received signal can be improved, and the anti-interference capability of the signal receiving end on receiving the signal can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a method, a circuit, and a device for optimizing a reference voltage. Background Art

[0002] A reference voltage is a very important parameter in an integrated circuit system. In an application scenario, a signal receiving end compares a received signal with the reference voltage. When the signal level value is higher than the reference voltage, it is determined that the received signal value is 1, and when the signal level value is lower than the reference voltage, it is determined that the received signal value is 0. Therefore, the magnitude of the reference voltage determines the accuracy of the signal receiving end's recognition of the received signal.

[0003] However, with the continuous improvement of the complexity and operating frequency of integrated circuits, the amplitude of the signal received by the signal receiving end may deviate from the preset amplitude due to factors such as the power supply state, circuit layout, and operating frequency, and the timing of signal sampling at the signal receiving end may also deviate due to the deviation of the sampling clock phase at the sampling moment caused by the perturbation of the operating frequency, which may lead to a decrease in the signal recognition accuracy rate. Summary of the Invention

[0004] In view of this, the present disclosure provides a method, a circuit, and a device for optimizing a reference voltage to help widen the margin of signal sampling at the signal receiving end in terms of voltage and clock phase, thereby helping to improve the recognition accuracy of the signal received by the signal receiving end and helping to improve the anti-interference ability of the signal receiving end when receiving signals.

[0005] The technical solution of the present disclosure is implemented as follows:

[0006] According to an aspect of an embodiment of the present disclosure, a method for optimizing a reference voltage is provided, including:

[0007] Sampling the data transmitted on at least one data line by changing the sampling clock phase to obtain a sampling clock phase interval when the sampling data on the at least one data line is all correct;

[0008] Obtaining an optimized sampling clock phase according to the sampling clock phase interval;

[0009] Using the optimized sampling clock phase, sampling the data transmitted on each of the at least one data line by changing the sampling voltage to obtain an effective reference voltage interval for each of the at least one data line;

[0010] Obtaining an optimized reference voltage for each of the at least one data line according to the effective reference voltage interval for each of the at least one data line.

[0011] In a possible implementation, sampling the data transmitted on at least one data line by changing the sampling clock phase to obtain a sampling clock phase interval when the sampling data on the at least one data line are all correct includes:

[0012] Obtain a first sampling clock phase, a second sampling clock phase, and a clock phase step size;

[0013] From the first sampling clock phase to the second sampling clock phase, using the clock phase step size as a unit, sample the data transmitted on the at least one data line with different sampling clock phases respectively to obtain first sampling data on the at least one data line corresponding to different sampling clock phases;

[0014] Obtain the sampling clock phase interval by judging the correctness of the first sampling data.

[0015] In a possible implementation, the step of from the first sampling clock phase to the second sampling clock phase, using the clock phase step size as a unit, sampling the data transmitted on the at least one data line with different sampling clock phases respectively to obtain first sampling data on the at least one data line corresponding to different sampling clock phases includes:

[0016] Take the first sampling clock phase as the current sampling clock phase;

[0017] Sample the data transmitted on the at least one data line with the current sampling clock phase to obtain first sampling data on the at least one data line in the case of using the current sampling clock phase;

[0018] Loop and execute the following process until the updated current sampling clock phase is the second sampling clock phase:

[0019] Increase the current sampling clock phase by the clock phase step size as the updated current sampling clock phase;

[0020] Sample the data transmitted on the at least one data line with the updated current sampling clock phase to obtain first sampling data on the at least one data line in the case of using the updated current sampling clock phase.

[0021] In a possible implementation, the step of sampling the data transmitted on the at least one data line with different sampling clock phases respectively to obtain first sampling data on the at least one data line corresponding to different sampling clock phases includes:

[0022] When sampling the data transmitted on any one of the at least one data line using any one sampling clock phase, the data transmitted on the any one data line is sampled using a plurality of preset sampling reference voltages, and a plurality of first sampled sub-data on the any one data line corresponding to the any one sampling clock phase are obtained, wherein the plurality of sampling reference voltages are within a preset reference voltage range, and the first sampling data includes the first sampled sub-data;

[0023] The obtaining of the sampling clock phase interval by judging the correctness of the first sampling data includes:

[0024] For the any one data line, judge the correctness of the plurality of first sampled sub-data;

[0025] Determine the any one sampling clock phase when at least any one of the plurality of first sampled sub-data is correct as the effective sampling clock phase of the any one data line;

[0026] According to the plurality of effective sampling clock phases of the any one data line determined, obtain the minimum effective sampling clock phase and the maximum effective sampling clock phase of the any one data line;

[0027] Determine the maximum value among all the minimum effective sampling clock phases of the at least one data line as the first clock phase boundary value, determine the minimum value among all the maximum effective sampling clock phases of the at least one data line as the second clock phase boundary value, and determine the interval between the first clock phase boundary value and the second clock phase boundary value as the sampling clock phase interval.

[0028] In a possible implementation manner, the obtaining of the optimized sampling clock phase according to the sampling clock phase interval includes:

[0029] Determine the middle value of the sampling clock phase interval as the optimized sampling clock phase.

[0030] In a possible implementation manner, the using of the optimized sampling clock phase to sample the data transmitted on each of the at least one data line by changing the sampling voltage to obtain the respective effective reference voltage intervals of each data line includes:

[0031] Obtain a first sampling voltage, a second sampling voltage, and a voltage step;

[0032] For any one of the at least one data line, starting from the first sampling voltage to the second sampling voltage, with the voltage step as the unit, different sampling voltages are respectively used to sample the data transmitted on any one of the data lines, and second sampling data corresponding to different sampling voltages are obtained;

[0033] By judging the correctness of the second sampling data, an effective reference voltage range of any one of the data lines is obtained.

[0034] In a possible implementation manner, the step of starting from the first sampling voltage to the second sampling voltage, with the voltage step as the unit, using different sampling voltages to sample the data transmitted on any one of the data lines respectively, and obtaining second sampling data corresponding to different sampling voltages includes:

[0035] Taking the first sampling voltage as the current sampling voltage;

[0036] Using the current sampling voltage to sample the data transmitted on any one of the data lines, and obtaining the second sampling data on any one of the data lines in the case of using the current sampling voltage;

[0037] The following process is cyclically executed until the updated current sampling voltage is the second sampling voltage:

[0038] Increasing the current sampling voltage by the voltage step as the updated current sampling voltage;

[0039] Using the updated current sampling voltage to sample the data transmitted on any one of the data lines, and obtaining the second sampling data on any one of the data lines in the case of using the updated current sampling voltage.

[0040] In a possible implementation manner, the step of obtaining the optimized reference voltage of each data line according to the effective reference voltage range of each data line includes:

[0041] Determining the intermediate value of the effective reference voltage range of each data line as the optimized reference voltage of each data line.

[0042] According to another aspect of the embodiments of the present disclosure, a reference voltage optimization circuit is provided, including:

[0043] A data sending module, coupled to one end of at least one data line, for sending data through the at least one data line;

[0044] A data sampling module, coupled to the other end of the at least one data line, for sampling the data transmitted on the at least one data line;

[0045] A control module, coupled to the data sending module and the data sampling and detection module, is configured to: control the data sending of the data sending module, and by changing the sampling clock phase, control the data sampling module to sample the data transmitted on the at least one data line, so as to obtain a sampling clock phase interval when the sampling data on the at least one data line is all correct; obtain an optimized sampling clock phase according to the sampling clock phase interval; use the optimized sampling clock phase, and by changing the sampling voltage, control the data sampling module to sample the data transmitted on each of the at least one data line respectively, so as to obtain an effective reference voltage interval for each of the data lines; and obtain an optimized reference voltage for each of the data lines according to the effective reference voltage interval for each of the data lines.

[0046] According to another aspect of the embodiments of the present disclosure, a reference voltage optimization device is provided, including:

[0047] A clock phase interval obtaining module, configured to perform sampling the data transmitted on at least one data line by changing the sampling clock phase, so as to obtain a sampling clock phase interval when the sampling data on the at least one data line is all correct;

[0048] An optimized sampling clock phase obtaining module, configured to perform obtaining an optimized sampling clock phase according to the sampling clock phase interval;

[0049] An effective reference voltage interval obtaining module, configured to perform sampling the data transmitted on each of the at least one data line respectively by using the optimized sampling clock phase and changing the sampling voltage, so as to obtain an effective reference voltage interval for each of the data lines;

[0050] An optimized reference voltage obtaining module, configured to perform obtaining an optimized reference voltage for each of the data lines according to the effective reference voltage interval for each of the data lines.

[0051] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, including:

[0052] A processor;

[0053] A memory for storing executable instructions of the processor;

[0054] Wherein, the processor is configured to execute the executable instructions to implement the reference voltage optimization method as described in any one of the above.

[0055] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the reference voltage optimization method described in any one of the above.

[0056] As can be seen from the above solutions, by using the reference voltage optimization method, circuit and device of the present disclosure, a relatively large margin can be maintained in time between the optimized sampling clock phase and the data phase on at least one data line. When a phase perturbation occurs in the data signal on any one data line, the optimized sampling clock phase helps to ensure accurate sampling of the data signal with the phase perturbation. Therefore, if the signal receiving end uses this optimized sampling clock phase, it helps to improve the anti-interference ability of the signal receiving end against signal phase perturbations when receiving signals. For a signal receiving end that needs to receive data transmitted on multiple data lines simultaneously, using the optimized sampling clock phase obtained by the present disclosure can improve the comprehensive anti-interference ability of the signal receiving end against timing perturbations of the received signals. On this basis, a relatively large margin can be maintained in the signal voltage amplitude between the optimized reference voltage of each of the at least one data line and the data transmitted on each of the at least one data line. When a signal amplitude jitter occurs in the data signal on any one data line, the optimized reference voltage of this data line helps to maintain accurate sampling when the signal amplitude jitter occurs. Therefore, if the signal receiving end uses this optimized reference voltage, it helps to improve the anti-interference ability of the signal receiving end against signal amplitude jitter when receiving signals. The reference voltage optimization method, circuit and device of the present disclosure help to broaden the margin of the signal sampling on the data line by the signal receiving end in terms of voltage and clock phase, help to improve the recognition accuracy of the signals received by the signal receiving end, and help to improve the anti-interference ability of the signal receiving end when receiving signals. Especially when the number of data lines is more than one, it can help to improve the recognition accuracy of the signals received by the signal receiving end on multiple data lines simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic circuit structure diagram for determining the reference voltage of a data line in the related art;

[0058] Figure 2 is an eye diagram schematic of the relative relationship between the voltage value of the data line after voltage division and the reference voltage;

[0059] Figure 3 is an eye diagram schematic in a case where the signal quality deteriorates;

[0060] Figure 4A is one of the principle eye diagram schematics of the reference voltage optimization method shown according to a schematic embodiment;

[0061] Figure 4B It is the second schematic eye diagram of the principle of the reference voltage optimization method shown according to a schematic embodiment;

[0062] Figure 5 It is a schematic flowchart of the reference voltage optimization method shown according to a schematic embodiment;

[0063] Figure 6 It is a schematic diagram of the relationship between a data line, the reference voltage scanning range, and the sampled data shown according to a schematic embodiment;

[0064] Figure 7 It is a schematic flowchart of obtaining the sampling clock phase interval shown according to a schematic embodiment;

[0065] Figure 8 It is a schematic diagram of the relationship between the sampling clock and the data eye diagram shown according to a schematic embodiment;

[0066] Figure 9 It is an eye diagram schematic when there is no sampling clock phase interval between each data line;

[0067] Figure 10 It is a schematic flowchart of obtaining the first sampled data on at least one data line corresponding to different sampling clock phases shown according to a schematic embodiment;

[0068] Figure 11 It is a schematic flowchart of obtaining the sampling clock phase interval shown according to a schematic embodiment;

[0069] Figure 12 It is a schematic flowchart of obtaining the effective reference voltage interval for each data line shown according to a schematic embodiment;

[0070] Figure 13 It is a schematic diagram of the relationship between the effective reference voltage interval, the reference voltage, and the eye diagram shown according to a schematic embodiment;

[0071] Figure 14 It is a schematic flowchart of obtaining the second sampled data corresponding to different sampling voltages shown according to a schematic embodiment;

[0072] Figure 15 It is a schematic flowchart of obtaining the effective reference voltage interval for any one data line shown according to a schematic embodiment;

[0073] Figure 16 It is a schematic diagram of the structure of a reference voltage acquisition circuit shown according to a schematic embodiment;

[0074] Figure 17 It is a schematic diagram of the structure of a reference voltage optimization device shown according to a schematic embodiment;

[0075] Figure 18 It is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. Specific embodiments

[0076] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the following examples are given with reference to the accompanying drawings to further elaborate on the present disclosure in detail.

[0077] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0078] The reference voltage is a highly stable voltage parameter used as a voltage reference in a circuit. With the continuous increase in the scale of integrated circuits, especially the development of system integration technology, the reference voltage has also become an indispensable basic circuit parameter in large-scale, very large-scale integrated circuits and almost all digital-analog systems.

[0079] Figure 1 It is a schematic structural diagram of a circuit for determining the reference voltage of a data line in the related art. As Figure 1 shown, a first voltage-dividing resistor Rd and a second voltage-dividing resistor Rt are respectively connected to both ends of the data line lane (which can also be referred to as a data transmission channel). The first voltage-dividing resistor Rd is connected to the power supply Vdd, and the second voltage-dividing resistor Rt is grounded. In an integrated circuit structure, the data line lane is a data transmission line between modules. According to Figure 1 the shown structure, the voltage value of the data line lane after voltage division is:

[0080]

[0081] wherein, V max is the maximum voltage value of the data line lane, V dd is the voltage value of the power supply Vdd, R d is the resistance value of the first voltage-dividing resistor Rd, and R t is the resistance value of the second voltage-dividing resistor Rt. Based on this, the reference voltage set for the data line lane is usually set to half of the maximum voltage value V max of the data line lane, that is:

[0082]

[0083] Figure 2 It is an eye diagram schematic diagram of the relative relationship between the voltage value of the data line after voltage division and the reference voltage. As Figure 2 shown, in the related art, the reference voltage is set to 0V (volt) and V maxThe intermediate value. The level signal of the data transmitted on the data line fluctuates above and below this reference voltage. When the signal receiving end receives the signal from the data line, if the level value of the received signal is higher than this reference voltage, it is considered that the value of the received signal is 1. For example, if the level value of the received signal is between this reference voltage and V max If it is between them, it is considered that the value of the received signal is 1; if the level value of the received signal is lower than this reference voltage, it is considered that the value of the received signal is 0. For example, if the level value of the received signal is between 0 and this reference voltage, it is considered that the value of the received signal is 0.

[0084] By adjusting the resistance value of the first voltage-dividing resistor Rd and the resistance value of the second voltage-dividing resistor Rt, the reference voltage of this data line can be adjusted, so as to realize the judgment of the signal value of the signal transmitted in this data line by the signal receiving end.

[0085] The above reference voltage setting is an idealized method. In this idealized method, the reference voltage is exactly located at the middle position of the rising edge and the falling edge of the signal. This ideal situation does not consider the possible delay of the signal resulting in phase drift of the rising edge and / or the falling edge. When the signal is transmitted at a relatively high rate, due to environmental and design reasons, the signal quality may deteriorate, and the rising edge and / or the falling edge may have phase drift. At this time, using the reference voltage determined by the idealized method to receive and judge the data transmitted in the data line may result in incorrect situations, leading to a decrease in the recognition accuracy rate of the signal received by the signal receiving end.

[0086] Figure 3 It is a schematic diagram of an eye diagram in the case of deteriorated signal quality. As Figure 3 shown, as the signal rate increases, the voltage of the signal will show unstable phenomena, making the actual optimal reference voltage deviate from the ideal reference voltage. For example Figure 3 shown, the actual optimal reference voltage may be lower than the ideal reference voltage. In this case, if the reference voltage is still set at the ideal reference voltage, it will lead to a decrease in the recognition accuracy rate of the signal received by the signal receiving end.

[0087] In addition, as the signal rate increases, the signal phase drift phenomenon in the circuit may also become obvious, and the phase of the signal may advance or lag. In this case, if the signal receiving end samples the signal due to signal phase drift and the sampling timing falls into the rising edge or falling edge region of the signal, it will also lead to a decrease in the recognition accuracy rate of the signal received by the signal receiving end.

[0088] In addition, with the development of integrated circuit technology, the data lines between the signal sending end and the signal receiving end have also been extended from a single channel to a multi-channel structure. There will also be a situation of signal phase drift between the data transmitted in multiple data lines, resulting in inconsistent signal phases between the data transmitted in multiple data lines. In this case, for the signal receiving end, the difficulty of accurately sampling the data transmitted in multiple data lines simultaneously will also increase accordingly.

[0089] In view of this, the embodiments of the present disclosure provide a reference voltage optimization method, circuit and device to help widen the margin of the signal receiving end for sampling the signals in the data lines in terms of voltage and clock phase, thereby helping to improve the recognition accuracy of the signals received by the signal receiving end and helping to improve the anti-interference ability of the signal receiving end when receiving signals. Especially when the number of data lines is more than one, it can help to improve the recognition accuracy of the signals received by the signal receiving end in multiple data lines simultaneously.

[0090] Figure 4A is one of the principle eye diagram schematics of the reference voltage optimization method shown according to a schematic embodiment. Figure 4B is the second principle eye diagram schematic of the reference voltage optimization method shown according to a schematic embodiment. The sampling of the signal by the signal receiving end is related not only to the reference voltage but also to the sampling clock phase. As Figure 4A shown, the signal receiving end samples at the rising edge of the sampling clock. When the phase relationship of the clock is poor (at the edge of the eye diagram, close to the intersection of the rising edge and the falling edge of the signal in the eye diagram), the effective reference voltage range of the signal that the signal receiving end can sample from the data line will be affected by the rising edge and the falling edge of the signal and be between v1 and v2. At this time, the margin for determining the optimal reference voltage is small. When the signal in the data line jitters, the signal receiving end is very likely to sample an incorrect signal value and generate an error code. For example, once the rising edge or the falling edge of the signal in the data line suddenly advances or delays, then the result of sampling the signal using the ideal reference voltage at the rising edge of the sampling clock by the signal receiving end is very likely to be incorrect. As Figure 4B shown, when there is a good phase relationship between the sampling clock phase and the signal phase, a better reference voltage for the sampled signal can be found, and the margin is large. For example, Figure 4B shown, when the sampling clock phase is located at the middle position between the rising edge and the falling edge of the signal phase, if the rising edge or the falling edge of the signal in the data line suddenly appears to advance or delay, it is very difficult for the sampling clock to fall into the rising edge or the falling region of the signal. At this time, the result of sampling the signal using the ideal reference voltage is still very likely to be correct.

[0091] Based on the above principle, the embodiments of the present disclosure combine the method of scanning and determining the sampling clock phase with the method of scanning and determining the reference voltage to obtain an optimized reference voltage that can help improve the data sampling accuracy for one data line or multiple data lines simultaneously.

[0092] Figure 5 It is a flowchart of a reference voltage optimization method shown according to a schematic embodiment. As Figure 5 shown, the reference voltage optimization method mainly includes the following steps 501 to 504.

[0093] Step 501: By changing the sampling clock phase, sample the data transmitted on at least one data line to obtain a sampling clock phase interval when the sampling data on at least one data line is all correct.

[0094] Step 502: Obtain an optimized sampling clock phase according to the sampling clock phase interval.

[0095] Step 503: Adopt the optimized sampling clock phase and, by changing the sampling voltage, sample the data transmitted on each data line in at least one data line respectively to obtain an effective reference voltage interval for each data line.

[0096] Step 504: Obtain an optimized reference voltage for each data line according to the effective reference voltage interval for each data line.

[0097] In the schematic embodiment, within the sampling clock phase interval, the sampling data on at least one data line is all correct, and outside the sampling clock phase interval, the sampling data on at least one data line is incorrect.

[0098] In the schematic embodiment, within the effective reference voltage interval of any one data line in at least one data line, the sampling data sampled on any one data line is all correct, and outside the effective reference voltage interval of any one data line, the sampling data sampled on any one data line is incorrect.

[0099] Subsequently, taking 64 data lines as an example, the technical solution of the present disclosure will be illustrated.

[0100] In the schematic embodiment, during step 501, the data transmitted on at least one data line is sampled using a preset reference voltage scanning range (including multiple sampling reference voltages).

[0101] Specifically, in step 501, for each data line at each sampling clock phase, a plurality of sampling reference voltages can be obtained by scanning within the reference voltage scanning range, and the data transmitted on each data line is sampled respectively using the plurality of sampling reference voltages.

[0102] Figure 6 FIG. 4 is a schematic diagram showing the relationship among a data line, a reference voltage scanning range, and sampled data according to an exemplary embodiment, as Figure 6 shown. The 64 data lines include data line lane0, data line lane1, data line lane2,..., data line lane63. The reference voltage scanning range is from vref0 to vref n , and the plurality of sampling reference voltages obtained by scanning between vref0 and vref n include vref0, vref1, vref2,..., vref n-1 , vref n . The sampled data corresponding to vref0, vref1, vref2,..., vref n-1 , vref n for data line lane0 are result00, result01, result02,..., result0 n-1 , result0 n . The sampled data corresponding to vref0, vref1, vref2,..., vref n-1 , vref n for data line lane1 are result10, result11, result12,..., result1 n-1 , result1 n . The sampled data corresponding to vref0, vref1, vref2,..., vref n-1 , vref n for data line lane2 are result20, result21, result22,..., result2 n-1 , result2 n . The sampled data corresponding to vref0, vref1, vref2,..., vref n-1 , vref n for data line lane63 are result630, result631, result632,..., result63 n-1 , result63 n .

[0103] In a schematic embodiment, during step 501, when sampling the data transmitted on at least one data line using any one of the sampling clock phases, if the sampled data on any one of the data lines is correct using any one of the sampling reference voltages within the reference voltage scanning range, it is determined that the sampled data on the any one of the data lines using the any one of the sampling clock phases is correct.

[0104] For example, referring to Figure 6 as shown, when sampling the data transmitted on 64 data lines using any one of the sampling clock phases; if the sampled data on data line lane0 is correct using any one of the sampling reference voltages vref0, vref1, vref2, ……, vref n-1 , vref n within, that is, any one of result00, result01, result02, ……, result0 n-1 , result0 n is correct, it is determined that the sampled data on data line lane0 using the any one of the sampling clock phases is correct; if the sampled data on data line lane1 is correct using any one of the sampling reference voltages vref0, vref1, vref2, ……, vref n-1 , vref n within, that is, any one of result10, result11, result12, ……, result1 n-1 , result1 n is correct, it is determined that the sampled data on data line lane1 using the any one of the sampling clock phases is correct; and so on, if the sampled data on data line lane63 is correct using any one of the sampling reference voltages vref0, vref1, vref2, ……, vref n-1 , vref n within, that is, any one of result630, result631, result632, ……, result63 n-1 , result63 n is correct, it is determined that the sampled data on data line lane63 using the any one of the sampling clock phases is correct.

[0105] In a schematic embodiment, the sampling clock phase interval can be obtained by means of sampling clock phase scanning. Figure 7 is a schematic flow diagram showing the obtaining of the sampling clock phase interval according to an exemplary embodiment. As Figure 7 shown, in the schematic embodiment, step 501 may specifically include the following steps 701 to step 704.

[0106] Step 701: Obtain the first sampling clock phase, the second sampling clock phase, and the clock phase step size.

[0107] Step 702: From the first sampling clock phase to the second sampling clock phase, with the clock phase step size as the unit, sample the data transmitted on at least one data line using different sampling clock phases respectively, to obtain first sampling data on at least one data line corresponding to different sampling clock phases.

[0108] Step 703: Obtain the sampling clock phase interval through the correctness judgment of the first sampling data.

[0109] In the illustrative embodiment, the first sampling clock phase, the second sampling clock phase, and the clock phase step size can be pre-configured. The first sampling clock phase, the second sampling clock phase, and the clock phase step size can be set according to the phase positions of the signal rising edge and falling edge reflected in the eye diagram of the signal in the data line. Preferably, in order to obtain the maximum sampling clock phase interval, the first sampling clock phase can be ahead of the cross position of the left signal rising edge and falling edge in the eye diagram of the signal in the data line, and the second sampling clock phase can be behind the cross position of the right signal rising edge and falling edge in the eye diagram of the signal in the data line.

[0110] The magnitude of the clock phase step size can determine the accuracy of the sampling clock phase interval and the time taken to obtain the sampling clock phase interval. The larger the clock phase step size is set, the smaller the accuracy of the sampling clock phase interval may be. Correspondingly, the time taken to obtain the effective reference voltage interval is shorter; the smaller the clock phase step size is set, the larger the accuracy of the sampling clock phase interval may be. Correspondingly, the time taken to obtain the effective reference voltage interval is longer. Based on this, the clock phase step size can be set according to the requirements of time consumption and accuracy, so as to achieve the balance between time consumption and accuracy for the sampling clock phase interval.

[0111] Figure 8 is a schematic diagram showing the relationship between the sampling clock and the data eye diagram according to an illustrative embodiment, as Figure 8 shown, in the eye diagrams of 64 data lines, there are differences in the data phases between each data line. Figure 8 In the example shown, the eye diagram of data line lane1 shows that its data phase is relatively ahead, the eye diagram of data line lane63 shows that its data phase is relatively behind, and the eye diagram of data line lane0 shows that its data phase is between the data phase of data line lane1 and the data phase of data line lane63.

[0112] Combined with Figure 8As shown, in step 702, from the left side of the eye diagram (the position relative to the first sampling clock phase) to the right side (the position relative to the second sampling clock phase), with the clock phase step as the unit, through the scanning of the sampling clock phase, the data transmitted on 64 data lines are sampled respectively with different sampling clock phases to obtain the first sampling data on the 64 data lines under different sampling clock phase conditions. In the illustrative embodiment, as Figure 6 shown, the first sampling data includes all result00 to result0 of data line lane0 to data line lane63 n 、result10 to result1 n 、……、result630 to result63 n .

[0113] Combined with Figure 8 shown, in step 703, by judging the correctness of the sampling data on 63 data lines under different sampling clock phase conditions, the obtained sampling clock phase interval is the Figure 8 range between the first boundary phase value pi0 (left dotted line) and the second boundary phase value pi1 (right dotted line) in Figure 8 . Among them, the position of the first boundary phase value pi0 in Figure 8 is just located at the intersection position of the rising edge and the falling edge of the left side signal of data line lane63, and is located between the intersection positions of the rising edge and the falling edge of the left and right side signals of other data lines, which means that using the sampling clock phase at the position of the first boundary phase pi0 in n-1 can ensure that at least one of the sampling data result630, result631, result632, ……, result63 n 、result63 n-1 in data line lane63 is correct, and the sampling data of other data lines are also correct; Figure 8 The position of the second boundary phase value pi1 in Figure 8 is just located at the intersection position of the rising edge and the falling edge of the right side signal of data line lane1, and is located between the intersection positions of the rising edge and the falling edge of the left and right side signals of other data lines, which means that using the sampling clock phase at the position of the second boundary phase value pi1 in n can ensure that at least one of the sampling data result10, result11, result12, ……, result1

[0114] It should be noted that Figure 8In the case of the eye diagram shown, although there may be a situation where the signal phases are inconsistent between each data line, there is at least a sampling clock phase interval in which the sampled data on each data line is correct, and there is an overlapping phase region (i.e., sampling clock phase interval) where the signal sampling is correct between each data line. In this case, since it is possible to ensure that the signal sampling on all data lines is correct, the subsequent steps of step 501 in the embodiments of the present disclosure can be implemented on this basis.

[0115] However, there may also be a situation where there is no overlapping phase region where the signal sampling is correct between each data line, that is, it is impossible to obtain the sampling clock phase interval when the sampled data on all data lines is correct in step 501, and this situation is no longer applicable to the subsequent steps of step 501 in the embodiments of the present disclosure. Figure 9 It is a schematic diagram of an eye diagram in the case where there is no sampling clock phase interval between each data line. As Figure 9 shown, among data line lane0, data line lane1 to data line lane63, although it is possible to ensure that all the sampled data on data line lane0 is correct within the phase interval (hereinafter referred to as the first phase interval) between the rising edge and the falling edge cross positions on the left and right sides of data line lane0, it is impossible to obtain the result that the sampled data of other data lines except data line lane0 is all correct at any phase position within this first phase interval; similarly, although it is possible to ensure that all the sampled data on data line lane1 is correct within the phase interval (hereinafter referred to as the second phase interval) between the rising edge and the falling edge cross positions on the left and right sides of data line lane1, it is impossible to obtain the result that the sampled data of other data lines except data line lane1 is all correct at any phase position within this second phase interval; although it is possible to ensure that all the sampled data on data line lane63 is correct within the phase interval (hereinafter referred to as the third phase interval) between the rising edge and the falling edge cross positions on the left and right sides of data line lane63, it is impossible to obtain the result that the sampled data of other data lines except data line lane63 is all correct at any phase position within this third phase interval. In this case, it is impossible to obtain the sampling clock phase interval through step 501. Based on this, in the illustrative embodiment, when it is impossible to obtain the sampling clock phase interval when the sampled data on at least one data line is all correct in step 501, the subsequent steps of step 501 are no longer executed.

[0116] In the illustrative embodiment, a loop control method can be used to obtain the first sampled data on at least one data line corresponding to different sampling clock phases. Figure 10is a schematic flowchart showing the process of obtaining first sampled data on at least one data line corresponding to different sampling clock phases, as Figure 10 shown. In the illustrative embodiment, step 702 may specifically include the following steps 1001 to 1004.

[0117] Step 1001: Set the first sampling clock phase as the current sampling clock phase;

[0118] Step 1002: Sample the data transmitted on at least one data line using the current sampling clock phase to obtain the first sampled data on at least one data line in the case of using the current sampling clock phase;

[0119] Loop and execute the following process of steps 1003 to 1004 until the updated current sampling clock phase is the second sampling clock phase:

[0120] Step 1003: Increase the current sampling clock phase by a clock phase step as the updated current sampling clock phase;

[0121] Step 1004: Sample the data transmitted on at least one data line using the updated current sampling clock phase to obtain the first sampled data on at least one data line in the case of using the updated current sampling clock phase.

[0122] In the above manner, in the case of setting the first sampling clock phase as the current sampling clock phase, the first sampled data on at least one data line obtained by sampling is the first sampled data on at least one data line in the case of using the first sampling clock phase; in the case of the current sampling clock phase updated after looping through the above steps 1003 to 1004 once, the first sampled data on at least one data line obtained by sampling is the first sampled data on at least one data line in the case of the first sampling clock phase increased by one clock phase step; in the case of the current sampling clock phase updated after looping through the above steps 1003 to 1004 twice, the first sampled data on at least one data line obtained by sampling is the first sampled data transmitted on at least one data line in the case of the first sampling clock phase increased by two clock phase steps; and so on, until the current sampling clock phase is the second sampling clock phase, the first sampled data on at least one data line obtained by sampling is the first sampled data on at least one data line in the case of using the second sampling clock phase.

[0123] In the illustrative embodiment, in step 702, sampling the data transmitted on at least one data line using different sampling clock phases respectively to obtain the first sampled data on at least one data line corresponding to different sampling clock phases may include:

[0124] When sampling the data transmitted on any one of at least one data line using any one sampling clock phase, the data transmitted on any one data line is sampled using a plurality of preset sampling reference voltages to obtain a plurality of first sampled sub-data on any one data line corresponding to any one sampling clock phase, wherein the plurality of sampling reference voltages are within a preset reference voltage range, and the first sampling data includes the first sampled sub-data.

[0125] For example, referring to Figure 6 As shown, when sampling the data transmitted on data line lane0 using any one sampling clock phase, vref0, vref1, vref2,..., vref n-1 , vref n are used to sample the data transmitted on data line lane0, and result00, result01, result02,..., result0 n-1 , result0 n on data line lane0 corresponding to any one sampling clock phase are obtained, where result00, result01, result02,..., result0 n-1 , result0 n are the first sampled sub-data; for example, when sampling the data transmitted on data line lane2 using any one sampling clock phase, vref0, vref1, vref2,..., vref n-1 , vref n are used to sample the data transmitted on data line lane2, and result20, result21, result22,..., result2 n-1 , result2 n on data line lane2 corresponding to any one sampling clock phase are obtained, where result20, result21, result22,..., result2 n-1 , result2 n are the first sampled sub-data; and so on.

[0126] Figure 11 is a schematic flowchart of obtaining a sampling clock phase interval shown according to an exemplary embodiment. As Figure 11 shown, in the exemplary embodiment, step 703 may specifically include the following steps 1101 to 1104.

[0127] Step 1101: For any one data line, judge the correctness of multiple first sampled sub-data;

[0128] Step 1102: When at least any one of the multiple first sampled sub-data is correct, determine any one sampling clock phase as the effective sampling clock phase of any one data line;

[0129] Step 1103: According to the multiple effective sampling clock phases of any one data line determined, obtain the minimum effective sampling clock phase and the maximum effective sampling clock phase of any one data line;

[0130] Step 1104: Determine the maximum value among all the minimum effective sampling clock phases of at least one data line as the first clock phase boundary value, determine the minimum value among all the maximum effective sampling clock phases of at least one data line as the second clock phase boundary value, and determine the interval between the first clock phase boundary value and the second clock phase boundary value as the sampling clock phase interval.

[0131] For example, taking data line lane0 as an example, represent any one sampling clock phase as sampling clock phase pi i , see Figure 6 shown. When using sampling clock phase pi i , in Step 1101, for data line lane0, judge the correctness of result00, result01, result02,..., result0 n-1 , result0 n ; in Step 1102, when at least any one of result00, result01, result02,..., result0 n-1 , result0 n is correct, determine the sampling clock phase pi i as the effective sampling clock phase of data line lane0, that is, when using sampling clock phase pi i , if at least any one of result00, result01, result02,..., result0 n-1 , result0 n is correct, then the sampling clock phase pi i is the effective sampling clock phase of data line lane0, where the sampling clock phase pi irepresents any sampling clock phase; in step 1103, according to the determined multiple valid sampling clock phases of data line lane0, the minimum valid sampling clock phase and the maximum valid sampling clock phase of data line lane0 are obtained; in step 1104, the maximum value among all the minimum valid sampling clock phases of data lines from lane0 to lane63, that is, the maximum value among the minimum valid sampling clock phases of data lines from lane0 to lane63, is determined as the first clock phase boundary value, and the minimum value among all the maximum valid sampling clock phases of data lines from lane0 to lane63, that is, the minimum value among the maximum valid sampling clock phases of data lines from lane0 to lane63, is determined as the second clock phase boundary value, and the interval between the first clock phase boundary value and the second clock phase boundary value is determined as the sampling clock phase interval.

[0132] In the illustrative embodiment, the correctness judgment of the first sampled data may include comparing the first sampled data with known data transmitted on at least one data line to judge the correctness of the first sampled data. Based on this, the known data can be sent through at least one data line and the first sampled data can be obtained by sampling from at least one data line, where the sending position and the sampling position of the known data on the data line are different. For example, the known data can be sent into the data line from one end of the data line and transmitted through the data line, and the first sampled data can be obtained by sampling from the other end of the data line.

[0133] In the illustrative embodiment, step 502 may specifically include: determining the intermediate value of the sampling clock phase interval as the optimized sampling clock phase.

[0134] Combined with Figure 8 As shown, the two boundary values of the sampling clock phase interval are the first boundary phase value pi0 and the second boundary phase value pi1, and the intermediate value of the sampling clock phase interval is the average value of the first boundary phase value pi0 and the second boundary phase value pi1, that is, the optimized sampling clock phase is (pi0 + pi1) / 2.

[0135] Combined with Figure 8 As shown, after completing the above step 502, there is a relatively large margin in time between the obtained optimized sampling clock phase and the data phases on at least one data line (such as 64 data lines). When there is a phase perturbation in the data signal on any one data line, the optimized sampling clock phase helps to ensure accurate sampling of the data signal with phase perturbation. Therefore, if the signal receiving end uses this optimized sampling clock phase, it helps to improve the anti-interference ability of the signal receiving end to signal phase perturbation when receiving signals.

[0136] Figure 12 It is a schematic flowchart showing the process of obtaining the effective reference voltage range for each data line according to a schematic embodiment. As Figure 12 shown, in the schematic embodiment, step 503 may specifically include the following steps 1201 to 1203.

[0137] Step 1201: Obtain a first sampling voltage, a second sampling voltage, and a voltage step size;

[0138] Step 1202: For any one of at least one data line, starting from the first sampling voltage to the second sampling voltage, with the voltage step size as the unit, sample the data transmitted on any one data line using different sampling voltages respectively, and obtain second sampling data corresponding to different sampling voltages;

[0139] Step 1203: Obtain the effective reference voltage range of any one data line by judging the correctness of the second sampling data.

[0140] In the schematic embodiment, the first sampling voltage, the second sampling voltage, and the voltage step size can be pre-configured. The first sampling voltage and the second sampling voltage can be set according to the voltage change range of the signal transmitted in the data line. For example, a certain voltage redundancy range can be extended on the basis of the voltage change range of the signal transmitted in the data line, so that the voltage range between the first sampling voltage and the second sampling voltage can cover the voltage change range of the signal transmitted in the data line lane. The size of the voltage step size can determine the accuracy of the effective reference voltage range. The larger the voltage step size is set, the smaller the accuracy of the effective reference voltage range may be, and the smaller the voltage step size is set, the larger the accuracy of the effective reference voltage range may be.

[0141] In the schematic embodiment, in order to ensure that a relatively accurate effective reference voltage range can be obtained, the first sampling voltage can be set to 0V, and the second sampling voltage can be set to the voltage value of the power supply Vdd. Since the smaller the voltage step size is, the longer the time taken to obtain the effective reference voltage range is, and the larger the voltage step size is, the shorter the time taken to obtain the effective reference voltage range is, therefore, the voltage step size can be set according to the requirements of time consumption and accuracy, so as to achieve a balance between time consumption and accuracy for the effective reference voltage range.

[0142] Figure 13 It is a schematic diagram showing the relationship between the effective reference voltage range, the reference voltage, and the eye diagram according to a schematic embodiment. As Figure 13As shown, in the eye diagrams of 64 data lines, the optimized sampling clock phase of (pi0 + pi1) / 2 obtained by the foregoing steps is used to sample the data on each data line. Taking data line lane0 as an example, in step 1202, for data line lane0, starting from the first sampling voltage value to the second sampling voltage value, with the voltage step as the unit, different sampling voltages are respectively used to sample the data transmitted on data line lane0, and the second sampling data corresponding to different sampling voltages on data line lane0 are obtained; in step 1203, by judging the correctness of the second sampling data corresponding to different sampling voltages on data line lane0, the effective reference voltage range of data line lane0 is obtained.

[0143] In the illustrative embodiment, a loop control method may be adopted to obtain the second sampling data corresponding to different sampling voltages. Figure 14 is a schematic flowchart of obtaining the second sampling data corresponding to different sampling voltages shown according to an illustrative embodiment. As Figure 14 shown, in the illustrative embodiment, step 1202 may specifically include the following steps 1401 to 1404.

[0144] Step 1401: Take the first sampling voltage as the current sampling voltage;

[0145] Step 1402: Use the current sampling voltage to sample the data transmitted on any data line to obtain the second sampling data on any data line under the current sampling voltage;

[0146] Loop and execute the following steps 1403 to 1404 until the updated current sampling voltage is the second sampling voltage:

[0147] Step 1403: Increase the current sampling voltage by the voltage step as the updated current sampling voltage;

[0148] Step 1404: Use the updated current sampling voltage to sample the data transmitted on any data line to obtain the second sampling data on any data line under the updated current sampling voltage.

[0149] In the above - mentioned manner, for any one of at least one data line, when the first sampling voltage is used as the current sampling voltage, the second sampling data on any one of the data lines obtained by sampling is the second sampling data on any one of the data lines when the first sampling voltage is used; when the current sampling voltage updated after one cycle of the above steps 1403 to 1404 is used, the second sampling data on any one of the data lines obtained by sampling is the second sampling data on any one of the data lines when the first sampling voltage is increased by one voltage step; when the current sampling voltage updated after two cycles of the above steps 1403 to 1404 is used, the second sampling data on any one of the data lines obtained by sampling is the second sampling data on any one of the data lines when the first sampling voltage is increased by two voltage steps; and so on, until the current sampling voltage is the second sampling voltage, the second sampling data on any one of the data lines obtained by sampling is the second sampling data on any one of the data lines when the second sampling voltage is used.

[0150] Figure 15 is a schematic flowchart of obtaining the effective reference voltage range of any one data line shown according to an exemplary embodiment, as Figure 15 shown. In the exemplary embodiment, step 1203 may specifically include the following steps 1501 to 1504.

[0151] Step 1501: For any one data line, judge the correctness of the second sampling data corresponding to different sampling voltages respectively.

[0152] Step 1502: Determine the sampling voltage corresponding to the second sampling data with correct judgment as the effective sampling voltage of any one data line.

[0153] Step 1503: According to the multiple effective sampling voltages of any one data line determined, obtain the minimum effective sampling voltage and the maximum effective sampling voltage of any one data line.

[0154] Step 1504: Determine the range between the minimum effective sampling voltage and the maximum effective sampling voltage of any one data line as the effective reference voltage range of any one data line.

[0155] For example, referring to Figure 13 shown, for data line lane0, in step 1503, its minimum effective sampling voltage and maximum effective sampling voltage are Figure 13 the lane0 minimum effective sampling voltage and lane0 maximum effective sampling voltage shown therein; for data line lane1, in step 1503, its minimum effective sampling voltage and maximum effective sampling voltage are Figure 13The minimum valid sampling voltage and the maximum valid sampling voltage of lane1 shown; for data line lane63, in step 1503, obtain its minimum valid sampling voltage and maximum valid sampling voltage as Figure 13 The minimum valid sampling voltage and the maximum valid sampling voltage of lane63 shown. In step 1504, determine the interval between the minimum valid sampling voltage and the maximum valid sampling voltage of lane0 as the valid reference voltage interval of data line lane0, determine the interval between the minimum valid sampling voltage and the maximum valid sampling voltage of lane1 as the valid reference voltage interval of data line lane1, and determine the interval between the minimum valid sampling voltage and the maximum valid sampling voltage of lane63 as the valid reference voltage interval of data line lane63.

[0156] In the illustrative embodiment, the judgment of the correctness of the second sampled data may include comparing the second sampled data with the known data transmitted on at least one data line to judge the correctness of the second sampled data. Based on this, the known data can be sent through at least one data line and the second sampled data can be obtained by sampling from at least one data line.

[0157] In the illustrative embodiment, step 504 may specifically include: determining the middle value of the valid reference voltage interval of each data line as the optimized reference voltage of each data line.

[0158] Combined with Figure 13 As shown, the two boundary values of the valid reference voltage interval of data line lane0 are the minimum valid sampling voltage and the maximum valid sampling voltage of lane0, and the middle value of the valid reference voltage interval of data line lane0 is the average value of the minimum valid sampling voltage and the maximum valid sampling voltage of lane0. In step 504, determine the average value of the minimum valid sampling voltage and the maximum valid sampling voltage of lane0 as the optimized reference voltage of data line lane0, that is, the lane0 optimized reference voltage; similarly, in step 504, determine the average value of the minimum valid sampling voltage and the maximum valid sampling voltage of lane1 as the optimized reference voltage of data line lane1, that is, the lane1 optimized reference voltage; and so on. In step 504, determine the average value of the minimum valid sampling voltage and the maximum valid sampling voltage of lane63 as the optimized reference voltage of data line lane63, that is, the lane63 optimized reference voltage.

[0159] Combined with Figure 13As shown, after completing the above step 504, a relatively generous margin can be maintained between the optimized reference voltage of each of the obtained at least one data line and the data transmitted on each of the at least one data line (for example, 64 data lines) in terms of signal voltage amplitude. When a signal amplitude jitter occurs in the data signal on any one of the data lines, the optimized reference voltage of the any one data line helps to maintain accurate sampling when the signal amplitude jitter occurs. Therefore, if the signal receiving end uses the optimized reference voltage, it helps to improve the anti-interference ability of the signal receiving end to signal amplitude jitter when receiving signals.

[0160] In the illustrative embodiment, at least one data line is located in the integrated circuit and is connected to the signal transmitting end and the signal receiving end. The at least one data line serves as a signal communication path between the signal transmitting end and the signal receiving end. Among them, the signal transmitting end is a functional module in the integrated circuit that generates the transmitted signal, and the signal receiving end is a functional module in the integrated circuit that receives signals from at least one data line. In the illustrative embodiment, refer to Figure 1 As shown, each of the at least one data lines is respectively connected between the power supply and the ground through its own voltage dividing resistor. After obtaining the optimized reference voltage by using the reference voltage optimization method of the present disclosure and configuring the optimized reference voltage at the signal receiving end, the signal receiving end uses the optimized reference voltage to receive the data signal transmitted by the signal transmitting end from the data line.

[0161] All of the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present disclosure, which will not be elaborated one by one here.

[0162] Figure 16 is a schematic structural diagram of a reference voltage optimization circuit shown according to an illustrative embodiment. As Figure 16As shown in the figure, the reference voltage optimization circuit includes a data transmission module 1601, a data sampling module 1602, and a control module 1603. Among them, the data transmission module 1601 is coupled to one end of at least one data line lane and is used to transmit data through at least one data line lane. The data sampling module 1602 is coupled to the other end of at least one data line lane and is used to sample the data transmitted on at least one data line lane. The control module 1603 is coupled to the data transmission module 1601 and the data sampling module 1602. The control module 1603 is used to: control the data transmission of the data transmission module 1601, control the data sampling module 1602 to sample the data transmitted on at least one data line lane by changing the sampling clock phase, and obtain the sampling clock phase interval when the sampling data on at least one data line lane is all correct; according to the sampling clock phase interval, obtain the optimized sampling clock phase; use the optimized sampling clock phase to control the data sampling module 1602 to sample the data transmitted on each data line lane in at least one data line lane respectively by changing the sampling voltage, and obtain the effective reference voltage interval for each data line lane; according to the effective reference voltage interval for each data line lane, obtain the optimized reference voltage for each data line lane.

[0163] In a schematic embodiment, within the sampling clock phase interval, the sampling data on at least one data line lane is all correct, and outside the sampling clock phase interval, there are errors in the sampling data on at least one data line lane; within the effective reference voltage interval of any one data line lane in at least one data line lane, the sampling data sampled on any one data line lane is all correct, and outside the effective reference voltage interval of any one data line lane in at least one data line lane, there are errors in the sampling data sampled on any one data line lane.

[0164] In a schematic embodiment, the data transmission module 1601, the data sampling module 1602, and the control module 1603 can be implemented in a combination of software and hardware. For example, the data transmission module 1601 and the data sampling module 1602 can be implemented by hardware circuits, and the control module 1603 can control the data transmission module 1601 and the data sampling module 1602, change the sampling clock phase, obtain the sampling clock phase interval, obtain the optimized sampling clock phase, obtain the effective reference voltage interval, obtain the optimized reference voltage, etc. by a hardware circuit combined with a program running on the hardware circuit.

[0165] In a schematic embodiment, the control module 1603 is specifically configured to: obtain a first sampling clock phase, a second sampling clock phase, and a clock phase step; control the data sampling module 1602 to sample the data transmitted on at least one data line lane using different sampling clock phases respectively from the first sampling clock phase to the second sampling clock phase in units of the clock phase step, so as to obtain first sampling data on at least one data line lane corresponding to different sampling clock phases; and obtain a sampling clock phase interval by judging the correctness of the first sampling data.

[0166] In a schematic embodiment, the control module 1603 is specifically configured to: use the first sampling clock phase as the current sampling clock phase; control the data sampling module 1602 to sample the data transmitted on at least one data line lane using the current sampling clock phase, so as to obtain first sampling data on at least one data line lane in the case of using the current sampling clock phase; and loop to execute the following process until the updated current sampling clock phase is the second sampling clock phase: increase the current sampling clock phase by the clock phase step as the updated current sampling clock phase; and control the data sampling module 1602 to sample the data transmitted on at least one data line lane using the updated current sampling clock phase, so as to obtain first sampling data on at least one data line lane in the case of using the updated current sampling clock phase.

[0167] In a schematic embodiment, the control module 1603 is specifically configured to: when sampling the data transmitted on any one of at least one data line lane using any one sampling clock phase, control the data sampling module 1602 to sample the data transmitted on any one data line lane using a preset plurality of sampling reference voltages, so as to obtain a plurality of first sampled sub-data on any one data line lane corresponding to any one sampling clock phase, where the plurality of sampling reference voltages are within a preset reference voltage range, and the first sampling data includes the first sampled sub-data.

[0168] In a schematic embodiment, the control module 1603 is specifically configured to: for any data line lane, determine the correctness of a plurality of first sampled sub-data; determine, as the effective sampling clock phase of any data line lane, any one sampling clock phase when at least any one of the plurality of first sampled sub-data is correct; obtain the minimum effective sampling clock phase and the maximum effective sampling clock phase of any data line lane according to the determined plurality of effective sampling clock phases of any data line lane; determine the maximum value among all the minimum effective sampling clock phases of at least one data line lane as the first clock phase boundary value, determine the minimum value among all the maximum effective sampling clock phases of at least one data line lane as the second clock phase boundary value, and determine the interval between the first clock phase boundary value and the second clock phase boundary value as the sampling clock phase interval.

[0169] In a schematic embodiment, the control module 1603 is specifically configured to: determine the intermediate value of the sampling clock phase interval as the optimized sampling clock phase.

[0170] In a schematic embodiment, the control module 1603 is specifically configured to: obtain a first sampling voltage, a second sampling voltage, and a voltage step; for any data line lane in at least one data line lane, control the data sampling module 1602 to sample the data transmitted on any data line lane with different sampling voltages respectively from the first sampling voltage to the second sampling voltage in units of the voltage step, and obtain second sampling data corresponding to different sampling voltages; obtain the effective reference voltage interval of any data line lane through the correctness judgment of the second sampling data.

[0171] In a schematic embodiment, the control module 1603 is specifically configured to: use the first sampling voltage as the current sampling voltage; control the data sampling module 1602 to sample the data transmitted on any data line lane with the current sampling voltage, and obtain the second sampling data on any data line lane when using the current sampling voltage; loop through the following process until the updated current sampling voltage is the second sampling voltage: increase the current sampling voltage by the voltage step as the updated current sampling voltage; control the data sampling module 1602 to sample the data transmitted on any data line lane with the updated current sampling voltage, and obtain the second sampling data on any data line lane when using the updated current sampling voltage.

[0172] In a schematic embodiment, the control module 1603 is specifically configured to: determine the intermediate value of the effective reference voltage interval of each data line lane as the optimized reference voltage of each data line lane.

[0173] Figure 17 is a schematic structural diagram of a reference voltage optimization device shown according to a schematic embodiment, as Figure 17 shown, the reference voltage optimization device includes a clock phase interval obtaining module 1701, an optimized sampling clock phase obtaining module 1702, an effective reference voltage interval obtaining module 1703, and an optimized reference voltage obtaining module 1704. Among them, the clock phase interval obtaining module 1701 is configured to perform sampling on the data transmitted on at least one data line by changing the sampling clock phase, and obtain a sampling clock phase interval when the sampling data on at least one data line is all correct. Among them, within the sampling clock phase interval, the sampling data on at least one data line is all correct, and outside the sampling clock phase interval, there are errors in the sampling data on at least one data line. The optimized sampling clock phase obtaining module 1702 is configured to obtain an optimized sampling clock phase according to the sampling clock phase interval. The effective reference voltage interval obtaining module 1703 is configured to perform sampling on the data transmitted on each data line in at least one data line by changing the sampling voltage using the optimized sampling clock phase, and obtain the respective effective reference voltage intervals of each data line. Among them, within the effective reference voltage interval of any data line in at least one data line, the sampling data sampled on any data line is all correct, and outside the effective reference voltage interval of any data line, there are errors in the sampling data sampled on any data line. The optimized reference voltage obtaining module 1704 is configured to obtain the respective optimized reference voltages of each data line according to the respective effective reference voltage intervals of each data line.

[0174] In the schematic embodiment, the clock phase interval obtaining module 1701 includes:

[0175] a clock parameter obtaining sub-module, configured to obtain a first sampling clock phase, a second sampling clock phase, and a clock phase step size;

[0176] a first sampling data obtaining sub-module, configured to perform sampling on the data transmitted on at least one data line from the first sampling clock phase to the second sampling clock phase in units of the clock phase step size, and obtain first sampling data on at least one data line corresponding to different sampling clock phases;

[0177] a sampling clock phase interval obtaining sub-module, configured to obtain a sampling clock phase interval by judging the correctness of the first sampling data.

[0178] In a schematic embodiment, the first sampling data acquisition sub-module is further configured to perform: taking the first sampling clock phase as the current sampling clock phase; sampling the data transmitted on at least one data line with the current sampling clock phase to obtain first sampling data on at least one data line in the case of using the current sampling clock phase; and looping to perform the following process until the updated current sampling clock phase is the second sampling clock phase: increasing the current sampling clock phase by a clock phase step as the updated current sampling clock phase; sampling the data transmitted on at least one data line with the updated current sampling clock phase to obtain first sampling data on at least one data line in the case of using the updated current sampling clock phase.

[0179] In a schematic embodiment, the first sampling data acquisition sub-module will further be configured to perform: when sampling the data transmitted on any one of at least one data line with any one sampling clock phase, sampling the data transmitted on any one data line with a plurality of preset sampling reference voltages to obtain a plurality of first sampled sub-data on any one data line corresponding to any one sampling clock phase, wherein the plurality of sampling reference voltages are within a preset reference voltage range, and the first sampling data includes the first sampled sub-data.

[0180] In a schematic embodiment, the sampling clock phase interval acquisition sub-module is further configured to perform: for any one data line, judging the correctness of a plurality of first sampled sub-data; determining any one sampling clock phase in the case that at least any one of the plurality of first sampled sub-data is correct as the valid sampling clock phase of any one data line; obtaining the minimum valid sampling clock phase and the maximum valid sampling clock phase of any one data line according to the determined plurality of valid sampling clock phases of any one data line; determining the maximum value among all the minimum valid sampling clock phases of at least one data line as the first clock phase boundary value, determining the minimum value among all the maximum valid sampling clock phases of at least one data line as the second clock phase boundary value, and determining the interval between the first clock phase boundary value and the second clock phase boundary value as the sampling clock phase interval.

[0181] In a schematic embodiment, the optimized sampling clock phase obtaining module 1702 is further configured to perform determining the middle value of the sampling clock phase interval as the optimized sampling clock phase.

[0182] In a schematic embodiment, the valid reference voltage interval obtaining module 1703 includes:

[0183] A sampling voltage parameter acquisition sub-module, configured to perform acquiring a first sampling voltage, a second sampling voltage, and a voltage step.

[0184] The second sampling data acquisition sub-module is configured to perform sampling on the data transmitted on any one of at least one data line from the first sampling voltage to the second sampling voltage, with the voltage step as the unit, and use different sampling voltages to obtain second sampling data corresponding to different sampling voltages respectively.

[0185] The effective reference voltage range acquisition sub-module is configured to perform obtaining the effective reference voltage range of any one data line by judging the correctness of the second sampling data.

[0186] In the illustrative embodiment, the second sampling data acquisition sub-module is further configured to perform: taking the first sampling voltage as the current sampling voltage; sampling the data transmitted on any one data line with the current sampling voltage to obtain the second sampling data on any one data line under the condition of using the current sampling voltage; looping through the following process until the updated current sampling voltage is the second sampling voltage: increasing the current sampling voltage by the voltage step as the updated current sampling voltage; sampling the data transmitted on any one data line with the updated current sampling voltage to obtain the second sampling data on any one data line under the condition of using the updated current sampling voltage.

[0187] In the illustrative embodiment, the optimized reference voltage obtaining module 1704 is further configured to perform determining the middle value of the effective reference voltage range of each data line as the optimized reference voltage of each data line.

[0188] Regarding the reference voltage optimization device in the above embodiments, the specific manners in which each unit performs operations have been described in detail in the embodiments related to the reference voltage optimization method, and will not be elaborated herein.

[0189] It should be noted that: the above embodiments are only illustrated by the division of the above functional modules. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0190] Figure 18It is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 1800 may vary greatly due to configuration or performance differences, and may include one or more processors (Central Processing Units, CPUs) 1801 and one or more memories 1802. Among them, at least one program code is stored in the memory 1802, and the at least one program code is loaded and executed by the processor 1801 to implement the reference voltage optimization method provided in each of the above embodiments. Of course, the electronic device 1800 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. The electronic device 1800 may also include other components for implementing device functions, which will not be elaborated here.

[0191] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the reference voltage optimization method in the above embodiment.

[0192] Optionally, the above computer-readable storage medium may be a non-transitory computer-readable storage medium. For example, the non-transitory computer-readable storage medium may include a ROM (Read-Only Memory), a RAM (Random-Access Memory), a CD-ROM (Compact Disc Read-Only Memory), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0193] The foregoing is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A reference voltage optimization method, comprising: Sampling the data transmitted on at least one data line by changing the sampling clock phase to obtain a sampling clock phase interval when the sampling data on the at least one data line is all correct; Obtaining an optimized sampling clock phase according to the sampling clock phase interval; Using the optimized sampling clock phase, sampling the data transmitted on each of the at least one data line by changing the sampling voltage to obtain an effective reference voltage interval for each of the at least one data line; Obtaining an optimized reference voltage for each of the at least one data line according to the effective reference voltage interval for each of the at least one data line.

2. The reference voltage optimization method according to claim 1, wherein The step of sampling the data transmitted on at least one data line by changing the sampling clock phase to obtain a sampling clock phase interval when the sampling data on the at least one data line is all correct includes: Obtaining a first sampling clock phase, a second sampling clock phase, and a clock phase step; Sampling the data transmitted on the at least one data line with different sampling clock phases from the first sampling clock phase to the second sampling clock phase in units of the clock phase step to obtain first sampling data on the at least one data line corresponding to different sampling clock phases; Obtaining the sampling clock phase interval through the correctness judgment of the first sampling data.

3. The reference voltage optimization method according to claim 2, wherein The step of sampling the data transmitted on the at least one data line with different sampling clock phases from the first sampling clock phase to the second sampling clock phase in units of the clock phase step to obtain first sampling data on the at least one data line corresponding to different sampling clock phases includes: Taking the first sampling clock phase as the current sampling clock phase; Sampling the data transmitted on the at least one data line with the current sampling clock phase to obtain first sampling data on the at least one data line in the case of using the current sampling clock phase; Repeating the following process until the updated current sampling clock phase is the second sampling clock phase: Increasing the current sampling clock phase by the clock phase step as the updated current sampling clock phase; Sampling the data transmitted on the at least one data line with the updated current sampling clock phase to obtain first sampling data on the at least one data line in the case of using the updated current sampling clock phase.

4. The reference voltage optimization method according to claim 2, wherein: The step of sampling the data transmitted on the at least one data line with different sampling clock phases to obtain first sampling data on the at least one data line corresponding to different sampling clock phases includes: When sampling the data transmitted on any one of the at least one data line using any one sampling clock phase, the data transmitted on the any one data line is sampled using a plurality of preset sampling reference voltages to obtain a plurality of first sampled sub-data on the any one data line corresponding to the any one sampling clock phase, wherein the plurality of sampling reference voltages are within a preset reference voltage range, and the first sampling data includes the first sampled sub-data; The obtaining of the sampling clock phase interval by judging the correctness of the first sampling data includes: For the any one data line, judging the correctness of the plurality of first sampled sub-data; Determining the any one sampling clock phase when at least any one of the plurality of first sampled sub-data is correct as the effective sampling clock phase of the any one data line; According to the plurality of effective sampling clock phases of the any one data line determined, obtaining the minimum effective sampling clock phase and the maximum effective sampling clock phase of the any one data line; Determining the maximum value among all the minimum effective sampling clock phases of the at least one data line as the first clock phase boundary value, determining the minimum value among all the maximum effective sampling clock phases of the at least one data line as the second clock phase boundary value, and determining the interval between the first clock phase boundary value and the second clock phase boundary value as the sampling clock phase interval.

5. The reference voltage optimization method according to claim 1, wherein The obtaining of the optimized sampling clock phase according to the sampling clock phase interval includes: Determining the middle value of the sampling clock phase interval as the optimized sampling clock phase.

6. The reference voltage optimization method according to claim 1, wherein The using of the optimized sampling clock phase to sample the data transmitted on each of the at least one data line by changing the sampling voltage to obtain the respective effective reference voltage ranges of each data line includes: Obtaining a first sampling voltage, a second sampling voltage, and a voltage step; For any one data line among the at least one data line, sampling the data transmitted on the any one data line using different sampling voltages in units of the voltage step from the first sampling voltage to the second sampling voltage to obtain second sampling data corresponding to different sampling voltages; By judging the correctness of the second sampling data, obtaining the effective reference voltage range of the any one data line.

7. The reference voltage optimization method according to claim 6, wherein The sampling the data transmitted on the any one data line using different sampling voltages in units of the voltage step from the first sampling voltage to the second sampling voltage to obtain second sampling data corresponding to different sampling voltages includes: Taking the first sampling voltage as the current sampling voltage; Sampling the data transmitted on the any one data line using the current sampling voltage to obtain the second sampling data on the any one data line in the case of using the current sampling voltage; Looping to execute the following process until the updated current sampling voltage is the second sampling voltage: Increase the current sampling voltage by the voltage step as the updated current sampling voltage; Sample the data transmitted on any one of the data lines using the updated current sampling voltage to obtain second sampling data on any one of the data lines under the condition of using the updated current sampling voltage.

8. The reference voltage optimization method according to claim 1, wherein The obtaining of the optimized reference voltage for each data line according to the effective reference voltage range of each data line includes: Determine the middle value of the effective reference voltage range of each data line as the optimized reference voltage for each data line.

9. A reference voltage optimization circuit, characterized in that, Includes: A data sending module, coupled to one end of at least one data line, for sending data through the at least one data line; A data sampling module, coupled to the other end of the at least one data line, for sampling the data transmitted on the at least one data line; A control module, coupled to the data sending module and the data sampling module data sampling and detection module, for: controlling the data sending of the data sending module, controlling the data sampling module to sample the data transmitted on the at least one data line by changing the sampling clock phase, obtaining a sampling clock phase range when the sampling data on the at least one data line is all correct; obtaining an optimized sampling clock phase according to the sampling clock phase range; using the optimized sampling clock phase to control the data sampling module to sample the data transmitted on each of the at least one data lines respectively by changing the sampling voltage, obtaining the effective reference voltage range for each data line; obtaining the optimized reference voltage for each data line according to the effective reference voltage range for each data line.

10. A reference voltage optimization device, characterized in that, Includes: A clock phase range obtaining module, configured to execute sampling the data transmitted on at least one data line by changing the sampling clock phase to obtain a sampling clock phase range when the sampling data on the at least one data line is all correct; An optimized sampling clock phase obtaining module, configured to execute obtaining an optimized sampling clock phase according to the sampling clock phase range; An effective reference voltage range obtaining module, configured to execute sampling the data transmitted on each of the at least one data lines respectively by changing the sampling voltage using the optimized sampling clock phase to obtain the effective reference voltage range for each data line; An optimized reference voltage obtaining module, configured to execute obtaining the optimized reference voltage for each data line according to the effective reference voltage range for each data line.

11. An electronic device, characterized in that, Includes: A processor; A memory for storing executable instructions of the processor; Wherein, the processor is configured to execute the executable instructions to implement the reference voltage optimization method according to any one of claims 1 to 8.

12. A computer-readable storage medium, characterized in that, When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the reference voltage optimization method according to any one of claims 1 to 8.

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